CN1822397A - 非易失性半导体存储装置及其制造方法 - Google Patents
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Abstract
提供一种非易失性半导体存储装置及其制造方法,通过均匀地形成纳米点,提供高可靠性的纳米点存储器。另外,通过在隧道绝缘膜上采用硅氧化膜替代材料,提供高速、高可靠性的纳米点存储器。其特征在于,在硅或者锗基板,最好是硅或者锗的(111)基板上,具有使HfO2、ZrO2或者CeO2的高介电常数绝缘膜外延生长而成的隧道绝缘膜和在上述隧道绝缘膜上形成的CoSi2或者NiSi2的硅化物纳米点。
Description
技术领域
本发明涉及非易失性半导体存储器。
背景技术
闪速存储器、EEPROM等半导体存储器因为其非易失性、并可电擦除重写而作为程序用、数据用存储器被广泛应用于数字家电、车载控制器等中。在这些半导体非易失性存储器的现有产品中,要想高速化、大容量化,元件微细化是必需的,但是众所周知为了保持数据保持特性而对特别是用于隧道绝缘膜的硅氧化膜进行微细化是有极限的。另外在重写时,由于经由隧道绝缘膜向浮栅(floating gate)注入热载流子,因而将引起隧道绝缘膜劣化,当前隧道绝缘膜的微细化正在达到极限。
为了解决上述问题,进行了各种新方式的非易失性存储器的研究开发,其中之一有代替浮栅的多晶硅膜,将多晶硅形成为点状的硅纳米点存储器。该硅纳米点存储器由于将电子蓄积在离散点中,因此即使由于重写在隧道氧化膜中出现漏电路径(leak path),由于仅仅是去掉被蓄积在一部分点中的电子,因此可期待其高可靠性。另外,通过有选择地向一部分点中写入电子,可期待利用写入区域的不同所产生的阈值电压的不同,使1个存储单元存储多个位信息(S.Tiwari等:IEEE International Electron Devices Meeting,PP 521-524(1995))。
但是,由于硅纳米点存储器伴随点的不均匀性产生元件特性偏差的问题,因此需要形成均匀的点。另外,即使重写耐性提高,只要是将硅氧化膜用于隧道绝缘膜,就不能本质地解决克服用于保持数据保持特性的隧道绝缘膜厚度的微细化极限的问题。
[非专利文献1]S.Tiwari等:IEEE International ElectronDevices Meeting,pp 521-524(1995)
发明内容
本发明的目的在于在纳米点存储器中均匀地形成纳米点,以谋求高可靠性。另外,通过在隧道绝缘膜上采用硅氧化膜代替材料,以谋求器件的高速、高可靠性。
发明人再次研究了纳米点存储器中的材料结构,注意到HfO2、ZrO2或者CeO2这样的高介电常数绝缘材料与CoSi2或者NiSi2这样的硅化物在晶体结构上是相同的(CaF2结构),仅仅是晶格常数有百分之几的不同(晶格常数:a=0.512nm(HfO2),0.507nm(XrO2),0.541nm(CeO2),0.536nm(CoSi2),0.540nm(NiSi2),(R.W.G.Wyckoff:CRYSTAL STRUCTURS Second Edition,Vol.1,John Wiley&Sons,Inc.)),发现了通过将上述高介电常数材料用于隧道绝缘膜,将上述硅化物用于存储器用纳米点,可谋求纳米点的均匀性和器件的高速化。更具体地,首先,在硅或者锗基板上外延生长上述高介电常数绝缘膜,形成隧道绝缘膜。此时基板优选是(111)基板。由此,形成结晶性好的高介电常数绝缘膜,且在表面上出现上述高介电常数绝缘膜的最致密面,在此之上通过用CVD(化学汽相沉积)形成相同晶体结构、晶格常数相差百分之几的上述硅化物,可岛状地形成均匀的硅化物。另外,通过使用高介电常数隧道绝缘膜,比起将氧化硅用于隧道绝缘膜时,可谋求实现器件的高速化和隧道绝缘膜的厚膜化。
[非专利文献2]R.W.G.Wyckoff:CRYSTAL STRUCTURSSecond Edition,Vol.1,John Wiley & Sons,Inc.
根据本发明,在纳米点存储器中,硅或者锗基板,最好是通过在硅或者锗的(111)基板上使用HfO2、ZrO2或者CeO2的高介电常数绝缘膜,在上述高介电常数绝缘膜上形成CoSi2或者NiSi2的硅化物点,来形成均匀的硅化物点,制造元件特性偏差少,可靠性高的器件。另外,由于使用结晶性好的高介电常数绝缘膜,可实现器件的高速化。
附图说明
图1是第一实施例中的硅化物点存储器的存储单元的截面图。
图2是第一实施例中的硅化物点存储器的存储单元的截面图。
图3是第一实施例中的硅化物点存储器的存储单元的截面图。
图4是第一实施例中的硅化物点存储器的存储单元的截面图。
图5是第一实施例中的硅化物点存储器的存储单元的截面图。
图6是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图7是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图8是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图9是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图10是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图11是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图12是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图13是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图14是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图15是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图16是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图17是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图18是第一实施例中的硅化物点存储器的存储单元的制造方法的说明图。
图19是第二实施例中的硅化物点存储器的存储单元的截面图。
图20是第二实施例中的硅化物点存储器的存储单元的截面图。
图21是第二实施例中的硅化物点存储器的存储单元的截面图。
图22是第二实施例中的硅化物点存储器的存储单元的截面图。
图23是第二实施例中的硅化物点存储器的存储单元的截面图。
具体实施方式
以下使用图1-图23详细说明本发明的实施方式。
(实施例1)
图1是本实施例中纳米点存储器的存储单元的截面图。在P型硅基板1上形成源漏扩散层2、3,在上述硅基板上通过外延生长制作由HfO2、ZrO2或者CeO2构成的高介电常数绝缘膜4。上述硅基板也可以是锗基板。这种情况下,由于锗比硅的迁移率大,因此器件的高速化优异。另外,上述硅或者锗基板最好是(111)基板。由此,可形成结晶性好的高介电常数绝缘膜。在上述高介电常数绝缘膜上,CoSi2或者NiSi2的硅化物5被形成在点上,在上述硅化物点上制作由SiO2等构成的层间绝缘膜6,在上述层间绝缘膜上制作控制栅7。上述控制栅7是例如多晶硅膜、金属薄膜、金属硅化物膜或者这些的层叠结构。特别是如果考虑抑制在与上述栅绝缘膜之间的界面上的相互扩散,并且为了高速化而将栅电极低电阻化,那么优选是在上述栅绝缘膜上使用粘接性好的TiN、TaN等的薄阻挡金属(barrier metal),且在其上使用W、Mo、Ta、Ti等的金属薄膜的结构。此时,在重视低电阻性的情况下使用W、Mo。在这两者的情况下,W因熔点高而热稳定性好,而Mo膜平坦性好。另外,在重视和阻挡金属的粘接性的情况下,采用在TiN上使用Ti的结构,或者在TaN上使用Ta的结构。
另外,上述源漏扩散层2、3上连接着由W、Al、多晶硅等构成的接触栓塞8、9。但是,为了上述接触栓塞和硅基板界面之间的粘接性以及为了防止在界面上的相互扩散、剥离,最好在接触区域界面上形成接触层10、11,且在上述接触层上部及与层间绝缘层12之间的界面上形成阻挡金属13、14后,形成上述接触栓塞。上述接触层10、11的构成材料是钴硅化物(CoSi2)、钛硅化物(TiSi2)等,上述阻挡金属13、14的构成材料是TiN、TaN等。上述接触栓塞8、9被连接到以Al、Cu等作为构成材料的布线层15、16上,但是为了防止上述布线层15、16在界面上的相互扩散、剥离,最好在上下具有由TiN、TaN等构成的阻挡金属17、18。
另外,本实施例中的纳米点存储器的存储单元也可以如图2所示那样,具有由用STI(浅槽分离)、LOCOS(硅的局部氧化)等形成的SiO2等构成的元件分离层19、20。这种情况下,由于进行了单元间的绝缘分离,因此可高集成化。或者,也可以如图3所示那样,具有由SiN、SiO2等构成的侧壁21、22。这种情况下,可降低源漏扩散层2、3形成时的绝缘膜的注入损伤,抑制注入的杂质向隧道方向扩散引起短隧道效应。或者也可以如图4所示那样,使用晶体管上的由SiN构成的层间绝缘膜23与元件分离层19、20上的由SiN构成的层间绝缘膜24、25的图形,自匹配地形成接触栓塞8、9。这种情况,具有即使用于光刻的掩模对齐有所偏差,也可正确地保持接触孔的位置的优点。或者也可以如图5所示那样,在相邻的存储单元中使源漏扩散层2、3共有化。这种情况,因为每单位面积的单元数目增加,因此可实现高集成化。另外,由于源漏扩散层的共有化,结构变得简单,可降低制造成本。
本实施例的硅化物点存储器通过在硅或者锗基板上、最好是硅或者锗的(111)基板上利用外延生长制作由HfO2、ZrO2或者CeO2构成的高介电常数绝缘膜,形成结晶性好的高介电常数隧道绝缘膜,且可在表面上出现上述高介电常数隧道绝缘膜的最致密的面。进而,通过在最致密的面出现在表面上的上述高介电常数隧道绝缘膜上,利用CVD形成晶体结构相同、晶格常数相差百分之几的CoSi2或者NiSi2的硅化物,可岛状地形成均匀的硅化物。通过形成均匀的纳米点,制造元件特性偏差少、高可靠性、高成品率的纳米点存储器。另外,通过采用结晶性好的高介电常数隧道绝缘膜,即使比现有的硅氧化膜的厚度要厚,也能够使硅氧化膜换算膜厚(EOT)减少,保持良好的数据保持特性,同时使晶体管的动作速度提高。
然后,说明本实施例的硅化物点的存储单元的制造方法。在这里,描述图3结构的硅化物点的制造方法。首先,利用STI或者LOCOS在P型硅或者锗基板1上形成元件分离层19、20(图6)。然后利用CVD或者ALD(原子层淀积法)外延生长来制作由HfO2、ZrO2或者CeO2构成的高介电常数绝缘膜(图7)。此时,上述硅或者锗基板最好是(111)基板。由此,形成结晶性好的高介电常数绝缘膜。接着,利用CVD或者ALD形成CoSi2或者NiSi2的硅化物纳米点5(图8)。此时,为了使硅化物纳米点之间不相连,最好使点的直径小于等于20nm。然后,为了使硅化物纳米点之间以及硅化物纳米点与上述硅化物纳米点上部的电极之间电气地绝缘,利用CVD或者ALD淀积由SiO2构成的层间绝缘膜27(图9)。由此,明显抑制了被存储到点内部的电荷在点之间、向栅方向或者基板方向的移动。其后,利用CVD方法等形成作为控制栅所使用的包含P或者B的杂质的多晶硅膜、金属薄膜、金属硅化物膜或者这些的层叠膜28(图10)。
接着,将光刻胶膜用作掩模,通过蚀刻将层叠膜加工成存储单元结构(图11)。之后利用CVD或者热氧化形成膜厚大约2nm左右的SiO2或者SiN膜29、30,然后通过离子注入As或者P形成浅的源漏区域31、32。这个工序用于形成连接源漏扩散层和隧道部分的延伸(extension)区域。形成上述SiO2或者SiN膜的目的是缓和由于离子注入对基板的损伤(图12)。然后,利用溅射或者CVD淀积了膜厚200nm左右的SiO2或者SiN膜后再进行蚀刻,形成侧壁21、22(图13)。之后,通过离子注入As或者P,形成源漏扩散层2、3(图14)。
接着,利用CVD或者溅射淀积了层间绝缘层12后,通过蚀刻形成到达源漏扩散层2、3的接触孔33、34(图15)。之后,通过溅射等使Co、Ti等淀积在接触孔开口部,并进行热处理,在与Si连接的部分上形成由CoSi2、TiSi2等构成的接触层10、11。然后去除与层间绝缘层连接的部分的Co、Ti等,利用溅射等形成由TiN、TaN等构成的阻挡金属13、14后,再利用溅射形成接触栓塞8、9,通过CMP进行平坦化处理后,变成如图16所示那样。接着,利用溅射淀积由TiN、TaN等构成的阻挡金属35、由Al、Cu等构成的布线层36、由TiN、TaN等构成的阻挡金属37(图17),在由CMP进行了平坦化之后,通过利用蚀刻进行如图18所示那样加工,形成布线层15、16。其后,通过进一步淀积层间绝缘层,形成如图3所示的硅化物点存储器的存储单元。并且,图3中仅明确描述了1层布线层,但是在上部可以有1层或者多层布线层,布线层间也可以用由W、Cu、Al等构成的通路栓塞连接。另外,上述制造方法使用了P型基板,但是也能够适用于使用N型基板的情况。
通过上述过程,制造具有结晶性好的高介电常数隧道绝缘膜以及均匀的硅化物纳米点的、高可靠性、高成品率的纳米点存储器。
(实施例2)
图19是本实施例中的纳米点存储器的存储单元的截面图。在本实施例中,在P型硅或者锗基板1上形成源漏扩散层2、3,在上述硅或者锗基板上利用外延生长来制作由HfO2、ZrO2或者CeO2构成的高介电常数绝缘膜4。并且,上述硅或者锗基板最好是(111)基板。由此,形成结晶性好的高介电常数绝缘膜。在上述高介电常数绝缘膜上,CoSi2或者NiSi2的硅化物5被形成在点上,在上述硅化物点上制作由HfO2、ZrO2或者CeO2构成的高介电常数层间绝缘膜50,在上述高介电常数层间绝缘膜上制作控制栅7。这是一种实施例1的存储单元(图1)的层间绝缘膜6置换为高介电常数层间绝缘膜50的结构,利用外延生长制作上述高介电常数层间绝缘膜。由此,通过在上述硅化物点上也采用结晶性好的高介电常数层间绝缘膜,即使是膜厚比现有的硅氧化膜厚,也能够使硅氧化膜换算膜厚(EOT)减少,在保持良好的数据保持特性的同时,进一步提高晶体管的动作速度。另外,本实施例中的纳米点存储器的存储单元,如图20所示,也可以具有由用STI、LOCOS等形成的SiO2等构成的元件分离层19、20。这种情况下,由于进行了单元间的绝缘分离,因此可以实现高集成化。或者,也可以如图21所示那样,具有由SiN、SiO2等构成的侧壁21、22。这种情况下,可降低源漏扩散层2、3形成时的绝缘膜的注入损伤,抑制注入的杂质向隧道方向扩散引起短隧道效应。或者,也可以如图22所示那样,使用由晶体管上的SiN构成的层间绝缘膜23和由元件分离层19、20上的SiN构成的层间绝缘膜24、25的图形,自匹配地形成接触栓塞8、9。这种情况下,具有即使用于光刻的掩模对齐有所偏差,也能够正确地保持接触孔的位置的优点。或者,也可以如图23所示那样,在相邻的存储单元上使源漏扩散层2、3共有化。这种情况,因为每单位面积的单元数目增加,因此可实现高集成化。另外,由于源漏扩散层的共有化,结构变得简单,可降低制造成本。
(工业上可利用性)
本发明能够适用于非易失性存储器。
Claims (12)
1、一种非易失性半导体存储器,其特征在于:
基板是硅或者锗基板,
上述基板上的隧道绝缘膜由高介电常数绝缘材料HfO2、ZrO2或者CeO2构成,
上述隧道绝缘膜上的电荷蓄积部为纳米点状,
上述纳米点由硅化物CoSi2或者NiSi2构成。
2、如权利要求1所述的非易失性半导体存储器,其特征在于:上述基板是硅或者锗的(111)基板。
3、一种非易失性半导体存储器的制造方法,其特征在于具有:
准备硅或者锗基板的步骤;
在上述基板上利用HfO2、ZrO2或者CeO2的外延生长,形成隧道绝缘膜的步骤;以及
通过CVD或者ALD在上述隧道绝缘膜上形成由硅化物CoSi2或者NiSi2构成的纳米点的步骤。
4、如权利要求3所述的非易失性半导体存储器的制造方法,其特征在于:
准备(111)基板作为上述基板。
5、如权利要求3所述的非易失性半导体存储器的制造方法,其特征在于具有:
形成直径小于等于约20nm的上述纳米点的步骤。
6、如权利要求4所述的非易失性半导体存储器的制造方法,其特征在于具有:
形成直径小于等于约20nm的上述纳米点的步骤。
7、一种非易失性半导体存储器,其特征在于:
基板是硅或者锗基板,
上述基板上的隧道绝缘膜由高介电常数绝缘材料HfO2、ZrO2或者CeO2构成,
上述隧道绝缘膜上的电荷蓄积部为纳米点状,
上述纳米点由硅化物CoSi2或者NiSi2构成,
上述纳米点上的与控制栅之间的层间绝缘膜由高介电常数绝缘材料HfO2、ZrO2或者CeO2构成。
8、如权利要求7所述的非易失性半导体存储器,其特征在于:
上述基板是(111)基板。
9、一种非易失性半导体存储器的制造方法,其特征在于具有:
准备硅或者锗基板的步骤;
在上述基板上形成利用HfO2、ZrO2或者CeO2的外延生长制作的隧道绝缘膜的步骤;
通过CVD或者ALD在上述隧道绝缘膜上形成由硅化物CoSi2或者NiSi2构成的纳米点的步骤;
通过在上述纳米点上使HfO2、ZrO2或者CeO2外延生长来形成层间绝缘膜的步骤;以及
在上述层间绝缘膜上形成控制栅的步骤。
10、如权利要求9所述的非易失性半导体存储器的制造方法,其特征在于:
准备(111)基板作为上述基板。
11、如权利要求9所述的非易失性半导体存储器的制造方法,其特征在于:
形成直径小于等于约20nm的上述纳米点。
12、如权利要求10所述的非易失性半导体存储器的制造方法,其特征在于具有:
形成直径小于等于约20nm的上述纳米点的步骤。
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US7057881B2 (en) | 2004-03-18 | 2006-06-06 | Nanosys, Inc | Nanofiber surface based capacitors |
JP2007227694A (ja) * | 2006-02-24 | 2007-09-06 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
TWI338914B (en) * | 2006-07-12 | 2011-03-11 | Ind Tech Res Inst | Metallic compound dots dielectric piece and method of fabricating the same |
US7667260B2 (en) * | 2006-08-09 | 2010-02-23 | Micron Technology, Inc. | Nanoscale floating gate and methods of formation |
KR100897515B1 (ko) * | 2007-03-14 | 2009-05-15 | 한국과학기술원 | 비휘발성 메모리 셀 및 그 제조방법. |
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US8395941B2 (en) | 2010-05-17 | 2013-03-12 | Micron Technology, Inc. | Multi-semiconductor material vertical memory strings, strings of memory cells having individually biasable channel regions, memory arrays incorporating such strings, and methods of accessing and forming the same |
US9166004B2 (en) | 2010-12-23 | 2015-10-20 | Intel Corporation | Semiconductor device contacts |
US20130294180A1 (en) | 2011-01-13 | 2013-11-07 | Ramot at Tel-Avlv University Ltd. | Charge storage organic memory system |
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US7262991B2 (en) * | 2005-06-30 | 2007-08-28 | Intel Corporation | Nanotube- and nanocrystal-based non-volatile memory |
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