CN1822356A - 用于电路板上的集成电路去藕的中介层 - Google Patents
用于电路板上的集成电路去藕的中介层 Download PDFInfo
- Publication number
- CN1822356A CN1822356A CNA200510132977XA CN200510132977A CN1822356A CN 1822356 A CN1822356 A CN 1822356A CN A200510132977X A CNA200510132977X A CN A200510132977XA CN 200510132977 A CN200510132977 A CN 200510132977A CN 1822356 A CN1822356 A CN 1822356A
- Authority
- CN
- China
- Prior art keywords
- metal
- group
- intermediary layer
- microchip
- metal structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 86
- 239000002184 metal Substances 0.000 claims abstract description 86
- 239000003990 capacitor Substances 0.000 claims description 11
- 235000006508 Nelumbo nucifera Nutrition 0.000 claims description 8
- 240000002853 Nelumbo nucifera Species 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 13
- 239000000463 material Substances 0.000 description 9
- 238000005538 encapsulation Methods 0.000 description 4
- 239000011888 foil Substances 0.000 description 3
- 241000446313 Lamella Species 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- CIWBSHSKHKDKBQ-JLAZNSOCSA-N Ascorbic acid Chemical compound OC[C@H](O)[C@H]1OC(=O)C(O)=C1O CIWBSHSKHKDKBQ-JLAZNSOCSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
用于对电路板(30)上的微芯片(10)进行去藕的中介层(20)。该中介层(20)在其上表面和下表面上包含结构化的金属层(26a-26d),用于分别贴装到微芯片(10)和电路板(30)。在该中介层的内部有两组互相绝缘的延伸的金属结构(21,22),该金属结构的延伸实质上垂直于所述中介层(20)的上表面和下表面。该第一组(21)延伸得比第二组(22)更靠近上表面,而所述第二组(22)延伸得比所述第一组(21)更靠近下表面。
Description
相关申请的交叉引用
本发明基于优先权申请EP 05290242.6,其在此处并入作为参考。
技术领域
本发明涉及电子领域,更具体地涉及一种在印制电路板上用于集成电路去藕的中介层。
背景技术
随着集成度的增加,需要连接到电路板的集成电路封装的管脚数目变得越来越大。众所周知的一种封装技术被称为球栅阵列(BGA),其为一种微芯片连接方法。球栅阵列芯片是一种在背面具有用于表面安装的锡球的四侧封装。由于允许了更多的表面区域用于贴装,因此BGA的使用使得管芯的封装尺寸减小。较小的封装使得更多的组件安装在一个模块上从而可以获得更大的可用密度。
另一方面,现代集成电路所操作的时钟频率随着微芯片的每一代变得越来越高。对于高速操作的一个基本要求是在集成电路的每一个供电管脚上可以获得足够的能量。这种去藕通常通过将电容器连接到每一个电源管脚来达到,其缓冲了电流源并且提供了短期能量需求。然而,这些电容器在电路板上占用了表面区域因此限制了可获得的集成密度。
已经提出来在微芯片和印刷电路板之间放置中介层。中介层作为小而薄的印刷电路板实现,其包含有安排在中介层内的层上的隐埋的组件例如电容器和电阻器。隐埋的电容器可以通过使用薄的金属化介电箔来实现。这样的薄片可以达到的电容为4-10nF/in2。然而,由于表面区域和中介层的体积是有限的,因此可以隐埋用以对电源管脚进行去藕的电容器的数目和电容值都是受限制的。
因此本发明的一个目的就是提供一种改进的用于电路板上的微芯片的去藕。
发明内容
以下出现的本发明的这些和其它的目的由用于对电路板上的微芯片进行去藕的中介层来实现。该中介层在其上表面和下表面上包含有结构化的金属层,用于分别贴装到微芯片和电路板。在该中介层中,有两组互相绝缘的延伸的金属结构,该金属结构实质上垂直于所述中介层的上表面和下表面。第一组延伸得比第二组更靠近上表面,而第二组延伸得比第一组更靠近下表面。
根据本发明,该两组金属结构以一种规则的、非结构化的模式安排在所述的中介层内,相邻金属结构之间的间隔小于微芯片的两个连接的间距。另外,金属层以一种应用特殊的方式构成,从而通过将金属结构从第一组连接到顶部金属层并且将相邻金属结构从第二组连接到底部金属层而形成电容器。
在本中介层中,通过将金属结构从第一组连接到顶部金属层并且将相邻金属结构从第二组连接到底部金属层而轻易地形成电容器。这就允许了高电容以及对于每个管脚的非常短的连接。该新的中介层为标准的可以灵活使用的基本元件
附图说明
以下结合附图对本发明的优选实施例进行描述,其中:
图1表示电路板上通过中介层贴装的BGA微芯片的第一实施例;
图2表示电路板上通过中介层贴装的BGA微芯片的第二实施例;
图3表示根据本发明的中介层的结构;
图4表示根据本发明的中介层的可选择的结构;
图5表示与微芯片的间距相比较的中介层的截面图;
图6表示根据本发明的中介层的抛光切口图像;
图7表示具有附加的直通连接的实现。
具体实施方式
本发明的第一实施例示意性地表示为图1所示的截面图。球栅阵列(BGA)封装的微芯片10贴装在中介层20上,中介层附着在印刷电路板30上。该微芯片的底侧具有三个锡球11,12和13,其连接到位于中介层顶表面的对应的锡料焊盘26a,26b和26c。电路板30上的锡球31,32和33连接到位于中介层20底表面的对应的锡料焊盘26d,26e和26f。
中介层20本身包含具有交替的垂直金属结构21,22。金属结构21的第一组向着中介层20的顶表面延伸,金属结构22的第二组向着中介层20的底表面延伸。锡料焊盘26b和26c因此连接到一些上部金属结构21,而锡料焊盘26f例如连接到一些下部金属结构22。锡料焊盘26a和26d放置在相应的盲通孔23a和23b(也就是,金属膜盲孔)的顶上,该盲通孔向下到达一些相对侧的金属结构。因此,在锡球11和31之间,在相应的金属结构21和22上存在有捷径,其代表了直通连接。另外,在锡料焊盘26b和26e之下,有一通孔25将这些焊盘直接相连。锡料焊盘26b和26d之间的区域29用作一个电容器。
盲通孔23a和23b和25为机械地或是使用激光钻成。金属膜为电流地或化学地淀积而成并且通过现有技术中已知的湿蚀刻处理制成。
在本简化的例子中,锡球12是微芯片10的电源管脚并且经过直通连接25连接到电路板上的电源提供点32。电路板上的锡球33接到地极,因此由金属结构建立在焊盘26b和26d之间的电容器29用以对电源管脚12进行去藕。
图2表示了一个类似的安装,但是区别在于不是单一顶部和底部的金属层,而是提供有附加的电路板层27和28,其可能包含附加的连接以及元件。该附加的电路板层27和28包括用以贴装微芯片和电路板的顶部和底部金属层,但是其没有单独地表示出来。
由于额外的电路板层27和28,因此就需要不同深度的盲通孔连接到内部金属结构21和22。在锡球13和33之下,有具有第一深度且仅向着较近金属结构延伸的盲通孔24a和24b。相反地,在锡球11和31之下,分别有较深的盲通孔23a和23b,也向着较深的金属结构进行连接,因此这些就形成了如图1的类似的直通连接。
图3表示了根据本发明的中介层的形成。第一类型1的薄片箔以及第二类型2的薄片箔以交替的顺序进行堆叠。类型1的箔承载着金属结构21,其延伸到中介层的顶表面,并且类型2的箔承载着金属结构22,其向着中介层的底表面延伸。箔上的金属结构的宽度加上到下一个金属结构的距离至少小于将被贴装的微芯片的管脚的间距。优选地,该间隔小于微芯片管脚的间距的一半。由于内部金属结构不能导致在任意位置上的捷径,因此并不要求中介层相对于电路板和微芯片的定位。作为一个例子,微芯片管脚的间距可以为1mm。于是金属结构的间距选择为0.4mm。
箔1和箔2可以由例如聚丙烯或是聚苯乙烯制成,并且金属结构21和22的材料的良好的候选物为铜,银,铝或是金。
箔1和箔2堆放在叠层上并接着在热压步骤中一同被熔解或是粘贴。从这样形成的块堆上,可以切割或是锯下薄的切片以构建中介层。
通过将这些金属结构连接起来在中介层上可以达到的容量取决于箔的厚度以及金属结构得以在其上连接并接着激活的表面区域,但是可以在直到20nF的范围内。
图4中,作为替代,沿着箔1和箔2的长度方向卷曲成一个卷,并且结合在一起以形成圆柱体,从其上可以切割或是锯下薄的切片以构建中介层。
图5表示的是通过中介层20的水平横截面。圆形的栅格表示BGA微芯片的间距,小条带的水平行表示垂直的金属结构21和22。
图6表示了中介层20的抛光切口的显微照片,其显示了两种类型的金属结构21和22。
中介层也可以通过生长陶瓷层而不是结合箔层形成,在这些陶瓷层之间淀积且以交替的顺序蚀刻有两组金属结构21和22。这类似于已知陶瓷电容器的制造,但是陶瓷层之间的金属层根据本发明的原理进一步构成。
本发明的另一个实施例如图7所示。在这里中介层由如图6所示类型的包括如上所述垂直金属结构的电容元件C和用作直通连接的导电元件R以棋盘布局构成。元件的宽度d等于有待贴装的微芯片的BGA管脚的间距。顶部以及底部金属层(没有示出)的正确设计允许特定应用所要求的任何电路得以实现。优选地,导电元件R在棋盘布局上仅每两行提供一个。
对本发明的特殊实施例详细地进行了完整的详细说明,对于本领域的技术人员来说,很清楚的是,不脱离本发明的概念可以做出各种修改和改变。
Claims (10)
1.一种用于对电路板上的微芯片进行去藕的中介层,所述中介层在其上表面和下表面上包含有结构化的金属层,用于分别贴装到微芯片和电路板,其中所述的中介层内部包括有两组互相绝缘的延伸的金属结构,所述金属结构的延伸实质上垂直于所述中介层的上表面和下表面,其中所述第一组延伸得比所述第二组更靠近上表面,而所述第二组延伸得比第一组更靠近下表面,并且其中所述两组金属结构以一种规则的、非结构化的模式安排在所述的中介层内,相邻金属结构之间的间隔小于微芯片的两个连接的间距,并且所述的金属层以一种应用特殊的方式构成,从而通过将金属结构从第一组连接到顶部金属层并且将相邻金属结构从第二组连接到底部金属层而形成电容器。
2.根据权利要求1所述的中介层,进一步包括位于所述结构化的顶部金属层和底部金属层之间的直通连接,一个直通连接具有一个从第一表面上的结构化的金属层向下到达一组的金属结构的盲通孔,该组延伸连接到相对侧表面上的结构化的金属层。
3.根据权利要求1所述的中介层,其中相邻金属结构之间的间隔小于微芯片两个连接的间距的一半。
4.根据权利要求1所述的中介层,其中包括承载着所述金属结构的垂直粘合的箔。
5.根据权利要求4所述的中介层,其中所述的箔以交替的顺序分别承载所述的两组金属结构。
6.根据权利要求1所述的中介层,其中所述的中介层包括两个分别承载所述两组金属结构的箔的卷。
7.根据权利要求1所述的中介层,其中所述的中介层包括其间以交替的顺序放置着所述两组金属结构的垂直陶瓷层。
8.根据权利要求1所述的中介层,其中所述金属结构的第一组连接到顶部金属层,所述金属结构的第二组连接到底侧金属层。
9.根据权利要求1所述的中介层,其中顶部金属层通过具有第一深度的盲通孔可以连接到所述金属结构的第一组,并且通过具有第二深度的盲通孔可以连接到所述金属结构的第二组,且其中底部金属层通过具有第一深度的盲通孔可以连接到所述金属结构的第二组,并且通过具有第二深度的盲通孔可以连接到所述金属结构的第一组。
10.一种包括至少一个贴装在其上的微芯片的电路板,其中在所述电路板和所述微芯片之间有中介层,所述中介层包括在其上表面和下表面上的结构化的金属层,用于分别贴装到微芯片和电路板,其中所述的中介层内部包括有两组互相绝缘的延伸的金属结构,所述金属结构的延伸实质上垂直于所述中介层的上表面和下表面,其中所述第一组延伸得比所述第二组更靠近上表面,而所述第二组延伸得比第一组更靠近下表面,并且其中所述两组金属结构以一种规则的、非结构化的模式安排在所述的中介层内,相邻金属结构之间的间隔小于微芯片的两个连接的间距,并且所述的金属层以一种应用特殊的方式构成,从而通过将金属结构从第一组连接到顶部金属层并且将相邻金属结构从第二组连接到底部金属层而形成电容器。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05290242A EP1688995B1 (en) | 2005-02-04 | 2005-02-04 | Interposer for decoupling integrated circuits on a circuit board |
EP05290242.6 | 2005-02-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1822356A true CN1822356A (zh) | 2006-08-23 |
CN100405594C CN100405594C (zh) | 2008-07-23 |
Family
ID=34941928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB200510132977XA Expired - Fee Related CN100405594C (zh) | 2005-02-04 | 2005-12-29 | 用于电路板上的集成电路去藕的中介层 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7964802B2 (zh) |
EP (1) | EP1688995B1 (zh) |
CN (1) | CN100405594C (zh) |
AT (1) | ATE506697T1 (zh) |
DE (1) | DE602005027534D1 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008100940A1 (en) * | 2007-02-12 | 2008-08-21 | Kemet Electronics Corporation | Electronic passive device |
US8723047B2 (en) * | 2007-03-23 | 2014-05-13 | Huawei Technologies Co., Ltd. | Printed circuit board, design method thereof and mainboard of terminal product |
US9282646B2 (en) * | 2012-05-24 | 2016-03-08 | Unimicron Technology Corp. | Interposed substrate and manufacturing method thereof |
JP6084475B2 (ja) * | 2013-02-04 | 2017-02-22 | 株式会社神戸製鋼所 | 溶接金属および溶接構造体 |
US9583426B2 (en) * | 2014-11-05 | 2017-02-28 | Invensas Corporation | Multi-layer substrates suitable for interconnection between circuit modules |
US10283492B2 (en) | 2015-06-23 | 2019-05-07 | Invensas Corporation | Laminated interposers and packages with embedded trace interconnects |
US9852994B2 (en) | 2015-12-14 | 2017-12-26 | Invensas Corporation | Embedded vialess bridges |
US10916493B2 (en) * | 2018-11-27 | 2021-02-09 | International Business Machines Corporation | Direct current blocking capacitors |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2622346B1 (fr) * | 1987-10-23 | 1993-05-28 | Eurofarad | Condensateur pour micro-circuit electronique et montage incorporant un tel condensateur |
JP3701138B2 (ja) * | 1999-04-23 | 2005-09-28 | 松下電器産業株式会社 | 電子部品の製造方法 |
US6292351B1 (en) * | 1999-11-17 | 2001-09-18 | Tdk Corporation | Multilayer ceramic capacitor for three-dimensional mounting |
US6525922B2 (en) * | 2000-12-29 | 2003-02-25 | Intel Corporation | High performance via capacitor and method for manufacturing same |
US6512182B2 (en) * | 2001-03-12 | 2003-01-28 | Ngk Spark Plug Co., Ltd. | Wiring circuit board and method for producing same |
US6791035B2 (en) * | 2002-02-21 | 2004-09-14 | Intel Corporation | Interposer to couple a microelectronic device package to a circuit board |
US7463474B2 (en) * | 2002-04-15 | 2008-12-09 | Avx Corporation | System and method of plating ball grid array and isolation features for electronic components |
US7030481B2 (en) * | 2002-12-09 | 2006-04-18 | Internation Business Machines Corporation | High density chip carrier with integrated passive devices |
KR100467834B1 (ko) * | 2002-12-23 | 2005-01-25 | 삼성전기주식회사 | 커패시터 내장형 인쇄회로기판 및 그 제조 방법 |
US7068490B2 (en) * | 2004-04-16 | 2006-06-27 | Kemet Electronics Corporation | Thermal dissipating capacitor and electrical component comprising same |
US7545623B2 (en) * | 2006-11-27 | 2009-06-09 | Kemet Electronics Corporation | Interposer decoupling array having reduced electrical shorts |
-
2005
- 2005-02-04 AT AT05290242T patent/ATE506697T1/de not_active IP Right Cessation
- 2005-02-04 EP EP05290242A patent/EP1688995B1/en not_active Not-in-force
- 2005-02-04 DE DE602005027534T patent/DE602005027534D1/de active Active
- 2005-12-14 US US11/302,268 patent/US7964802B2/en not_active Expired - Fee Related
- 2005-12-29 CN CNB200510132977XA patent/CN100405594C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1688995A1 (en) | 2006-08-09 |
ATE506697T1 (de) | 2011-05-15 |
DE602005027534D1 (de) | 2011-06-01 |
CN100405594C (zh) | 2008-07-23 |
US7964802B2 (en) | 2011-06-21 |
EP1688995B1 (en) | 2011-04-20 |
US20060176674A1 (en) | 2006-08-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1822356A (zh) | 用于电路板上的集成电路去藕的中介层 | |
US6395996B1 (en) | Multi-layered substrate with a built-in capacitor design | |
CN100350602C (zh) | 带内插器的微电子电路封装 | |
US7889509B2 (en) | Ceramic capacitor | |
CN100359996C (zh) | 印刷电路板及其制造方法 | |
US20070263364A1 (en) | Wiring board | |
JP5460155B2 (ja) | キャパシタ及び配線基板 | |
US6967138B2 (en) | Process for manufacturing a substrate with embedded capacitor | |
CN101213890A (zh) | 多层布线基板及其制造方法 | |
CN102638931B (zh) | 电子组件、使寄生电容最小的方法及电路板结构制造方法 | |
CN101038880A (zh) | 基板的制造方法 | |
WO2005008733A2 (en) | Modular electronic assembly and method of making | |
CN100525578C (zh) | 用于提高电路板的定线密度的方法和这种电路板 | |
US5740010A (en) | Printing and adhering patterned metal on laid-up multi-layer green wafer before firing so as to later form precise integral co-fired conductive traces and pads on top and bottom surfaces of monolithic, buried-substrate, capacitors | |
JPH05299291A (ja) | 高誘電率を有する可撓性シート、並びに該シートを有する多層回路基板、バスバー及び多層コンデンサ | |
JP2008109020A (ja) | 多連チップ部品および多連チップ実装基板 | |
US6011684A (en) | Monolithic integrated multiple electronic components internally interconnected and externally connected by conductive side castellations to the monolith that are of varying width particularly monolithic multiple capacitors | |
CN101038881A (zh) | 一种基板的制造方法 | |
CN1376021A (zh) | 具有内建电容的多层基板及其制造方法 | |
JP4305088B2 (ja) | コンデンサ及びその製造方法、並びにインターポーザーまたはプリント配線板及びその製造方法 | |
CN100343984C (zh) | 可嵌埋电子组件的半导体封装散热件结构 | |
KR100669963B1 (ko) | 다층배선기판 및 그 제조 방법 | |
CN2662448Y (zh) | 具有混合线路的电路模块 | |
JP3081528B2 (ja) | 光電変換装置 | |
CN2922382Y (zh) | 一种表面安装的印制电路板电路模块 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080723 Termination date: 20191229 |