CN1717804A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN1717804A
CN1717804A CNA200480001504XA CN200480001504A CN1717804A CN 1717804 A CN1717804 A CN 1717804A CN A200480001504X A CNA200480001504X A CN A200480001504XA CN 200480001504 A CN200480001504 A CN 200480001504A CN 1717804 A CN1717804 A CN 1717804A
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semiconductor device
passage area
zone
gate electrode
substrate
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CN100508195C (zh
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初大平
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Seiko Epson Corp
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Abstract

一种半导体器件，包括形成在相同衬底上的n通道区域和p通道区域，两个通道区域具有源极和漏极。所述器件还包括为两个通道区域所共有的门电极、并且该门电极通过安置在门电极之下的非极化介电材料区域与衬底分开。

Description

半导体器件
技术领域
本发明涉及一种半导体器件，尤其涉及一种新颖结构的半导体器件，所述器件器件可以以具有减小的器件器件尺寸来实施。本发明也涉及操作这样的器件器件的方法。
背景技术
有利地可以实施本发明的半导体器件的一种形式是反向器。反向器是一种电路元件，所述电路元件广泛使用，尤其是在逻辑应用中。这样的电路通常由两个独立且互补的晶体管所组成，一个n通道，一个是p通道晶体管(诸如MOS-FET)。对于晶体管端子的布置，反向器可以由多种组合构造而成。通常的构造是具有两个独立的晶体管结合在一起的门端子，一个晶体管的源极端子连接到另外一个晶体管的漏极端子。典型的逻辑电路应用可以典型地包括超过一千的反向器电路，这样由这些电路在芯片上占据的空间可能比较显著。
大规模集成(LSI)或者超大规模集成(ULSI)的器件器件密度引起了减小器件器件尺寸的需要。在需要新的器件器件结构和器件器件制造技术的研究中耗费了较多的资源来实现此目标，但是仍然持续需求器件器件的尺寸的减小。
发明内容
本发明提供一种新形式的半导体器件，所述器件器件本质上可以用作两个晶体管并很容易适用于大规模集成技术。所述器件器件可以有利地实施作为反向器，使得所述器件器件的尺寸与反向器的公知的组合相比显著地(典型地超过50％)减小，因为所述器件器件只需要占据传统的单个场效应晶体管(FET)的空间。另外的优点是本发明所述器件器件的制造只涉及传统和公知的经过验证的半导体制造工艺和技术，这样其很容易集成。
根据本发明的第一方面，提供了一种半导体器件，包括形成在相同衬底上的n通道区域和p通道区域，两个通道区域具有源极和漏极，所述器件还包括为两个通道区域所共有的门电极，并且该门电极通过安置在门电极之下的非极化介电材料区域与衬底分开。
有利地，一个通道区域的源极串联连接到另外一个通道区域的漏极，以提供用作反向器的器件。
在可选的实施例中，衬底包括薄薄膜衬底材料，优选地薄薄膜衬底材料被支撑在透明支撑材料上。
根据本发明的第二方面，提供了一种操作根据本发明的第一方面所述的半导体器件的方法，所述方法包括选择施加到门电极上的电压、以可选择地在独立于另一通道区域的非导电和导电条件之间切换其中一个通道区域。根据本发明的另外一方面，提供了一种操作根据本发明的第一方面所述的半导体器件的方法，当衬底包括薄薄膜衬底时，包括把其中一个通道区域作为薄膜区域进行操作，并且将另一通道区域的源极和漏极区域连接到偏置电压，由此在所述的一个通道区域中消除扭折效应。
根据本发明的另外一方面，提供了一种操作根据本发明的第一方面所述的半导体器件的方法，当衬底包括支撑在透明支撑材料上的薄膜衬底材料时，包括将其中一个通道区域作为薄膜区域进行操作，由此将所述器件作为发光器件进行操作。
附图说明
本发明的实施例将通过进一步的实施例并参照附图进行详细说明，其中：本发明的实施例将通过进一步的实例并参照附图进行详细说明，其中：
图1显示了根据本发明的半导体器件；
图2(a)和2(b)显示了当衬底是薄薄膜并且掺杂厚度至少等于衬底的深度时沿着图1中所示的器件器件的p和n掺杂方向的横截面图；
图3(a)和3(b)显示了当掺杂厚度小于衬底的深度时沿着图1中所示器件器件的p和n掺杂方向的横截面图；
图4显示了图1中所示的器件器件的示意平面图，对于门电极和p以及n通道具有典型的尺寸；
图5(a)和5(b)分别是图4所示的器件的n和p通道方向中的示意横截面图；
图6(a)和6(b)显示了当图1中所示的n通道和p通道晶体管的源极和漏极串联连接的两个结构；
图7(a)-7(c)以能带图显示了图1中所示的器件的工作原理；
图8显示了图4中所示的器件的DC特征；以及
图9显示了图4中所示的器件的AC特征。
具体实施方式
根据本发明的半导体器件的示例可以从图1中观察。所述器件包括衬底2，其内形成n类型的掺杂区域4和p型掺杂区域6。掺杂区域可以通过此技术领域中公知的任何适当的制造工艺来形成，诸如通过限定掺杂区域的所需位置的掩模来掺杂。在图1所示的器件中，n和p类型的区域被显示为基本彼此正交安置，但是必须理解可以使用可选的非正交布置，只要保持n和p类型的掺杂区域之间的交叉点。
门电极8设置在n和p类型的掺杂区域的交叉点之上并且此门电极通过非极化介质材料区域10从衬底2、和这种掺杂区域4和6分开。端子A、B、C、D和E设置在n和p类型的掺杂区域上以及如图1所示的门电极8上，适当的导线可以连接到所述器件。
同样，如图1所示，所述器件可选地分别在n和p类型的掺杂区域4、6中设有稍微掺杂的区域12、14。
图2(a)和2(b)分别显示了沿着p和n掺杂方向的所述器件的横截面图，并且在此实施例中，涉及薄膜晶体管(TFT)结构，衬底2的形式为具有厚度小于掺杂深度的薄膜形式。图3(a)和3(b)也显示了沿着p和n的掺杂方向的横截面图，但是在此实施例中，衬底的厚度大于掺杂深度，诸如在绝缘体上有硅(SOI)结构。
从图2、3可见，所述器件在各n和p通道方向上包括场效应晶体管(FET)结构，并且这两个衬底共享相同的门电极8。
必须指出n和p类型掺杂区域被形成在如图2、3所示的实施例中的衬底2上。但是，FET结构可以形成作为有机薄膜晶体管结构，在这种情况下，n和p类型的通道可以通过适当的过程诸如通过使用喷墨技术沉积有机聚合体而形成到衬底2的表面上。
用于图1所示的器件的实际实现的一个示例被显示在图4、5中。图4显示了n和p类型掺杂区域每个具有10μm宽度的器件的平面图，具有方形形式的门电极，所述门电极具有30μm的侧向尺寸。由此，在此实现器件时，n和p类型的掺杂区域具有相同的宽度，即，1∶1比率，并且门电极8具有三倍于n和p类型的区域的宽度，即3∶1的比率。
对于所述器件的n型晶体管，通道宽度通过p型掺杂区域之间的空间所提供，通道长度通过n型掺杂区域之间的空间所提供。同样，对于所述器件的p类型晶体管，通道宽度通过n类型掺杂区域之间的空间所提供，并且通道长度通过p型掺杂区域之间的空间所提供。因此在如图4、5所示的实施例中，n和p类型晶体管每个都具有通道宽度(W)和长度(L)的比值为(W/L)1∶1。但是，通过在器件制造的过程中适当控制n和p类型的掺杂区域，可以对晶体管提供不同的通道宽度和长度的比值。
相似地，门电极8可以以与图4所示的不同比值制造，并且不一定需要是方形形状。此外，门电极的尺寸可以相对通道区域的二者或者之一来进行选择。
在n型和p型掺杂区域中图4所示的横截面显示在图5中。所述器件典型地包括一层形成在衬底2上的二氧化硅(SiO2)。然后多硅层被形成在SiO2层上。介电区域10然后通过进一步沉积另外的SiO2层和导电层而提供，然后被成图案以暴露多硅层。N和p类型的掺杂区域然后通过穿过适当的掩模进行掺杂而提供在被暴露的多硅层中。
作为如上所述在逻辑应用中非常广泛使用的电路结构的反向器包括n型晶体管和p型晶体管，典型地具有连接在一起的两个晶体管门以及串联连接到另一晶体管漏极的一个晶体管的源极。如图1所示的半导体器件本质上包括具有相同的门电极的n型晶体管和p型晶体管。因此，所述器件的两个晶体管的门电极通过固有的器件结构连接在一起；即共用门电极。因此，如果如图1所示器件的一个晶体管的源极被连接到另一晶体管的漏极，以串联连接晶体管，所述器件可以作为反向器。两个具有串联连接的晶体管的反向器的结构被显示在图6(a)和6(b)中，电源连接到端子A和D，通过连接端子B和C来获得连接到端子E(相同的门电极8)的反向器输入端和反向器输出端。
图7(a)-7(c)显示了图6中所示的反向器的工作原理。如果门电极8上的电压小于0V，如图7A所示，p类型区域中的能级20相对费米(Fermi)能级EF被移动到更高的能带，同时n类型区域中的能级22相对费米能级被移动到较低的能带上。因此，p类型的通道被接通(ON)，n类型通道保持断开(OFF)。
如图4、5所示的器件用的典型的DC和AC特征如图8、9所示，并且普通技术人员可以理解这些是FET用的典型特征。因此，可以看出，尽管n和p类型的掺杂区域在门电极之下的衬底上共享相同的通道区域，但它们仍然作为单独的晶体管操作。
这样，可以看出本发明提供了一种新类型的器件，本质上包括共享相同的门电极的n和p类型晶体管。因此，与单独的晶体管相比，所述器件的尺寸较小；典型地小于两个独立的晶体管的脚印尺寸的一半。此外，所述器件很容易使用传统的半导体制造技术集成到电路布置中。
此外，由于提供用于n通道和p通道操作的相同区域的器件的布置，阀值电压平移ΔVth对两个通道将是相同的；即，对于n类型和p类型的晶体管器件。
在独立的n通道和p通道器件的情况下，阀值电压ΔVth的总方差可以表达为：
ΔV2 th，comb＝ΔV2 th，n-ch+ΔV2 th，p-ch
本发明的器件：
ΔVth，n-ch＝ΔVth，p-ch＝ΔVth
并且因此，总的方差为
ΔV2 th，单个器件＝ΔV2 th＝ΔV2 th，comb/2
阀值电压平移的这种减小可以有利地被用于克服阀值电压方差的负面效果、并且因此提供了实际应用中改良的器件性能，特别在阀值电压方差对反向器电路导致问题的TFT结构中。
所述器件结构也提供了一种方式来最小化“扭折效应”，都知道其在使用绝缘体上有硅(SOI)和/或者多晶硅薄膜晶体管(TFT)技术所制造的n通道晶体管中特别明显。
这可以通过使用n掺杂区域4和作为n通道场效应晶体管的门端子8来实现，并且同时，在适于应用到端子A和B的偏压之下使用p掺杂区域6来移除靠近被构造的n通道FET的漏极区域的冲击电离作用所产生的空穴，由此减小“扭折效应”。
由于所述器件是共享门电极之下的相同控制区域的n类型和p类型晶体管，电子和空穴在此中心区域中共存。这些电子和空穴可以在此中心区域中重新组合，这样所述器件可以用作发光器件。在此情况下，直接带隙材料可以有利地用于衬底材料。此外，透明支撑层可以提供在衬底材料、或者透明介电材料10以及透明门电极8之下，以允许发生所产生的光。
此外，公知的是n通道器件比p通道器件更容易导电。因此，本发明的器件也可以使用不同的门电压电平来操作，以选择性地接通和断开n通道和p通道晶体管。
前述说明只是通过示例给出，普通技术人员可以在不偏离本发明的精神的情况下进行修改。例如，可以使用不同的衬底材料，包括任何的无定形、多晶和水晶形式的有机和无机材料。
修改的特定示例如下所述：
门介电材料可以由有机介电材料所形成。
门导电材料可以由有机导电材料所形成。
源极和漏极触点可以由有机导电材料所形成。
半导体材料可以由磁性类型的材料所形成。
门介电材料可以由磁性类型材料所形成。
源极和漏极触点可以由磁性类型材料所形成。
铁电材料层可以设置在薄膜衬底材料之下，电触点位于另外一侧上。
一层磁性材料可以设置在薄薄膜衬底材料之下，其可以通过附近的器件或者外部器件所磁化。

Claims (17)

1.一种半导体器件，包括形成在相同衬底上的n通道区域和p通道区域，两个通道区域具有源极和漏极，所述器件还包括为两个通道区域所共有的门电极，并且该门电极通过安置在门电极之下的非极化介电材料区域与衬底分开。
2.根据权利要求1所述的半导体器件，其特征在于，其中一个通道区域的至少一个长度和/或者宽度与另一通道区域不同。
3.根据权利要求1或者2所述的半导体器件，其特征在于，门电极的尺寸被设置成相对于其中一个通道区域的宽度和长度具有特定的比率。
4.根据权利要求1-3任一项所述的半导体器件，其特征在于，至少n通道和p通道区域之一具有另外的区域，所述另外的区域被安置在源极和/或者漏极区域之一、和通道区域之间，具有小于源极和/或者漏极区域的掺杂浓度。
5.根据前述任一项权利要求所述的半导体器件，其特征在于，分离n通道区域的n类型源极和n类型漏极、以及p通道区域的p类型源极和p类型漏极的衬底的区域只具有固有的掺杂。
6.根据前述任一所述的半导体器件，其特征在于，至少n通道和p通道区域之一包括薄膜区域。
7.根据权利要求6所述的半导体器件，其特征在于，薄膜区域包括有机半导体材料。
8.根据权利要求1-6任一项所述的半导体器件，其特征在于，衬底包括薄膜衬底材料。
9.根据权利要求8所述的半导体器件，其特征在于，薄膜衬底材料包括直接带隙材料。
10.根据权利要求8或者9所述的半导体器件，其特征在于，薄膜衬底材料支撑在透明支撑材料上。
11.根据权利要求8或者9所述的半导体器件，其特征在于，门电极和非极化介电材料包括透明材料。
12.根据前述任一项权利要求的半导体器件，其特征在于，衬底的厚度设置成使得门电极之下的n通道区域和p通道区域用作完全或者部分的耗尽区域。
13.根据前述任一项权利要求的半导体器件，其特征在于，一个区域的源极与另外一个区域的漏极串联连接，以提供用作反向器的器件。
14.一种操作根据前述任一项权利要求的半导体器件的方法，所述方法包括选择施加到门电极上的电压，以可选择地在独立于另一通道区域的非导电和导电条件之间切换通道区域之一。
15.一种操作根据权利要求8-11任一项所述的半导体器件的方法，包括：把其中一个通道区域作为薄膜区域进行操作，并且将另一通道区域的源极和漏极区域连接到偏置电压，由此在所述的一个通道区域中消除扭折效应。
16.一种将根据权利要求10或者11所述的操作半导体器件作为发光器件进行操作的方法。
17.一种根据权利要求10或者11的半导体器件，其特征在于半导体器件是发光器件器件。
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