CN1595646A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN1595646A CN1595646A CNA2004100368185A CN200410036818A CN1595646A CN 1595646 A CN1595646 A CN 1595646A CN A2004100368185 A CNA2004100368185 A CN A2004100368185A CN 200410036818 A CN200410036818 A CN 200410036818A CN 1595646 A CN1595646 A CN 1595646A
- Authority
- CN
- China
- Prior art keywords
- lead
- semiconductor chip
- pressure welding
- welding area
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 2
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- 229910000881 Cu alloy Inorganic materials 0.000 description 2
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
Abstract
提供了用于安装半导体芯片的半导体芯片安装区,通过以相同间隔在半导体芯片安装区的整个周边上配置内引线的末端,可使内引线末端更接近于半导体芯片安装区。沿半导体芯片安装区的整个周边配置内引线的末端,使对应于半导体芯片安装区的角部的内引线的末端处的引线间距比在其他内引线末端的引线间距宽。
Description
本申请是株式会社日立制作所和日立北海半导体株式会社于1997年3月17日递交的、申请号为97103312.9、发明名称为“引线框、使用该引线框的半导体器件及其制造方法”的发明专利申请的分案申请。
[技术领域]
本发明涉及半导体器件,更具体地说,涉及能有效使用包含多个引线的引线框技术的半导体器件。
[背景技术]
随着集成度的改善,在诸如大规模集成电路(LSI)的半导体器件中安装了更复杂的电路,其功能也大为提高。由于达到这样高的功能,半导体器件变得需要更多的外部端子,这样,在半导体芯片上设置的压焊区电极和本身是半导体器件的外部端子的引线的数目也相应地增加。例如,在逻辑型半导体器件中,外部端子的数目甚至达到几百个。作为这样一种多引线半导体器件,已知有四方扁平封装(QFP)型半导体器件。由于在QFP型半导体器件中分别对密封半导体芯片的密封体的四个侧面上设置有多个引线,故这种器件适合于形成多引线,并且具有下述优点,即当半导体器件在封装基板上进行封装时可有效地利用半导体器件周围的间距。
用于组装这种QFP型半导体器件的引线框已在1993年5月31日出版的“VLSL封装技术(VLSI Packaging Technique)(第一卷)”的第155至164页中给出,特别是在第157至159页中示明了具体的图形。
此外,由于上述的改进使半导体芯片上形成的元件数目增加,同时这些元件是在较高的速度下工作,故从半导体芯片产生的热量也增加。作为为了解决上述问题已使散热性能得到改善的半导体器件,例如在“VLSL封装技术(最后一卷)”的第200至203页中,已描述了一种备有散热器的半导体器件。在这种半导体器件中,它的散热性能通过在半导体芯片上安装散热器得到了改善。
为了解决上述的多引线形成中的问题,需要在引线框中减少引线间距,即引线中的间隔,同时减小引线的宽度尺寸。
此外,类似于上面所述,由于要实现所述的高功能,在半导体芯片上设置了多个压焊区电极,并且将压焊区间距,即压焊区电极中的间隔,也形成得更小。一般来说,存在半导体芯片压焊区的多种电极间距,但希望芯片尺寸小,以便增加在每个晶片上可得到的芯片数目,因此就显示出这样一种趋势,即也将各个压焊区电极中的间距设置得更小。
存在这样一个问题:当使用金等焊丝将多个引线和各个压焊区电极互相键合时,由于间隔变得较小,就易于产生因邻近的焊丝互相接触而引起的短路。特别是由于在半导体芯片的角部处,沿相对于半导体芯片的斜方向,键合到压焊区电极的焊丝拉长,故即使当压焊区间距相同时,在焊丝之间的间隔也变小,因此前述趋势表现得更明显。
此外还存在有这样的问题:在焊丝键合后进行树脂模塑的情况下,有时会产生因各个焊丝的机械强度下降由于模塑树脂的流动使焊丝变形致焊丝移动,或焊丝间隔的减少,而且因这种变形产生焊丝的短路。
再有,在QFP中引线的配置区域,越接近安装在中心的半导体芯片时会变得越窄。其结果是,当引线间距由于引线的加工精度的限制不能相对于半导体芯片的压焊区间距充分地变细时,就不可能使引线的末端接近于半导体芯片。因而,用于使压焊区电极和引线互相键合的焊丝不得不加长。当焊丝以这种方式加长时,上述短路或焊丝移动产生的可能性变得更大。
还由于引线的这种变细降低了各个引线的机械强度,使引线变得易因小的力而被变形,并且也因这种变形产生短路。
[发明内容]
本发明的一个目的是提供一种能在具有多引线的半导体器件中防止发生短路或引线移动和使键合变得稳定的技术。
本发明的另一个目的是提供一种能在具有多引线的半导体器件中改善散热特性的技术。
通过本说明书的描述和附图,本发明上述的和其他的研究对象和特征将变得显而易见。
在本申请书内公开的发明中,有代表性的发明内容将概述如下。
在将半导体芯片安装在支撑体上和将内引线通过绝缘体固定到该支撑体上的半导体器件中,将内引线的末端用设置在上述支撑体的整个表面上的粘附层固定到半导体芯片安装区的整个周边。
对各个内引线末端处的引线间距而言,将最大引线间距设置成小于最小引线间距的两倍。
使对应于半导体芯片角部处内引线末端的引线间距比在其他引线末端处的引线间距宽。
在对应于半导体芯片的角部的内引线中,设置不引出密封体之外的虚设引线。
使位于半导体角部处压焊区电极的压焊区间距比其他压焊区电极的压焊区间距宽。
根据上述办法,通过将内引线末端固定到半导体芯片安装区的整个周边,可使内引线末端更接近于半导体芯片安装区。因而,可减少邻近的焊丝互相接触的短路或因模塑树脂的流动致焊丝被变形而产生的焊丝移动。
再有,由于可使对应于半导体芯片角部处内引线末端的引线间距比在其他引线末端处的引线间距宽,故可减少邻近的焊丝因互相接触短路或由于模塑树脂的流动致焊丝被变形而产生的焊丝移动。
再由于通过设置虚设电极使得在树脂流中难以产生紊流,可减少因空洞引起的的树脂注入不充分。
还因为没有悬挂翼片的引线,故可容易地进行交叉键合。
此外,通过事先在支撑体的整个表面上形成粘附层来固定内引线,可使带有支撑体的引线框的制造过程简化和减少生产成本。
进一步,通过在支撑体上安装半导体芯片,在半导体芯片内产生的热量就可通过支撑体散发到外部,这样可改善半导体芯片的散热特性。
[附图说明]
图1是示明本发明一个实施例的引线框的平面图;
图2是图1中所示引线框的纵截面图;
图3是示明本发明一实施例的引线框制造方法的纵向截面图;
图4是示明本发明一个实施例的半导体器件的纵截面图;
图5是示明本发明的另一个实施例的半导体器件中所用半导体芯片的平面图;
图6是示明局部放大了的图5的平面图;
图7是局部地示明本发明另一个实施例的QFP型半导体器件中所用引线框的平面图;
图8是示明本发明另一实施例的引线框的截面图;
图9是示明使用图8中所示引线框制造的半导体器件的纵截面图;
图10是示明本发明另一实施例的引线框的截面图;
图11是示明使用图10中所示引线框制造的半导体器件的纵截面图;
图12是示明本发明另一实施例的引线框的截面图;
图13是示明使用图12中所示引线框制造的半导体器件的纵截面图;
图14是示明用于本发明另一实施例的引线框的支撑体8的平面图;
图15是示明图14中所示支撑体8上安装半导体芯片10的状态的平面图;
图16是局部地示明本发明另一实施例的半导体器件的平面图;
图17是局部地示明本发明又一实施例的半导体器件的平面图;
图18是局部地示明本发明人在先于本发明的阶段中研究过的半导体器件的平面图;
而
图19是局部地示明本发明另一实施例中半导体器件的平面图。
[具体实施方式]
以下将描述本发明的实施例。此外,在所有用于说明实施例的附图中,将相同的标号赋予具有相同功能的部件,并略去其重复的描述。
实施例1
图1是本发明的一个实施例的QFP型半导体器件中所用引线框的平面图,图2是图1中所示引线框的纵截面图。引线框1由例如Fe-Ni合金组成,在中心处的半导体芯片的半导体芯片(用虚线示出)安装区2的整个周边上配置有多个引线3的内引线4的末端。此外,引线框1可由Cu合金组成。
各个引线3用变成引线框框体的闭合杆6或联结杆19形成为一个整体,各个引线3的闭合杆6的内部和外部分别用作内引线4和外引线5。
这种引线构型是通过众所周知的刻蚀技术或冲压技术等形成的,在通常的QFP型半导体器件中,配置有几十条至几百条引线3,在本实施例中配置了104条引线3。将各个引线3的内引线4的末端通过在支撑体整个表面上形成的绝缘粘接层7固定到支撑体8的表面上。
在本发明的引线框1中,将半导体芯片固定到支撑体8的半导体芯片安装区2上,内引线4固定于该支撑体8。因此,就不设置用于支撑安装半导体芯片的翼片(管心底座)的悬挂翼片引线,但是已被设置成翼片悬挂引线的区域则用来配置内引线4。
其结果是,在迄今被用来设置翼片悬挂引线的角部处也配置内引线4,而且相对于引线间距,即在各个内引线的末端处的间隔而言,最大引线间距小于沿包括角部的整个周边的最小引线间距的一倍,而且在各个内引线4中没有配置其他引线的余地。简言之,本实施例的引线框是这样形成的,在相邻内引线的末端处所容许的最大引线间隔(L)、最小内引线间隔(W1)和事先由引线框的加工精度或设计值确定的最小内引线宽度(W2)中的关系满足下式1。
(L)<2×(W1)+(W2) ... (式1)
于是,在本实施例中,即使对于通过以相同间隔在包括已设置翼片悬挂引线的位置的半导体芯片安装区的整个周边上,以相同引线间距配置内引线,也可使内引线4的末端更接近于半导体芯片安装区2。因此,当在安装半导体芯片之后进行焊丝键合时可缩短焊丝长度,这样就可在树脂密封时减少焊丝移动和减少焊丝中的短路。
这里,通过将例如Cu或Al料等具有高热导率的材料用作支撑体8,可改善半导体器件的散热性。
此外,由于通过将多个引线3的内引线4固定到支撑体8上而改善了各个引线3的机械强度,故即使在将内引线4的引线间距做得很小,也难以发生因外力引起的内引线的变形。结果,可防止产生键合焊丝中的短路。
再者,虽然在现有技术中已有采用散热器的无翼片器件,但迄今该散热器只被用作散热对象。按照本发明,这种器件已被可靠地用于解决引线间距问题,以便改善键合的稳定性。
下面将参照图2、图3和图4,描述图1和图2中所示的引线框和制造使用该引线框的半导体器件的方法。
首先,如图3(a)所示,通过对支撑体8的事先已粘有内引线4的整个表面上涂敷来形成粘接层7。作为粘接层,例如可使用热固性树脂,如环氧树脂和苯酚树脂;或使用热塑性树脂,如聚乙烯树脂和氯乙烯树脂。支撑体8可通过对金属薄板等进行冲切得到,但可在这种加工之前或之后涂敷上粘接层7。在将粘接层涂敷到上述整个表面上的期间,可在涂敷粘接层时制成掩模等和减少带有支撑体8的引线框的制造成本。再有,粘接层7也可以是膜状的聚酰亚胺树脂。在这种情况下,在将膜状的聚酰亚胺粘到变成支撑体8的基体金属板上之后,只需通过冲切加工就可。
其次,如图3(b)所示,将引线框1中形成构型的各个内引线4粘到带有粘接层7的支撑体8上。该状态在图2中示出。在本实施例的情况下,在粘接之前用约300℃的热处理使粘接层7固化。
然后如图3(c)所示,用银糊剂12将半导体芯片10粘到半导体芯片安装区2上。迄今已采用将粘接层7涂敷到内引线4上和将内引线4粘到支撑体8上的方法,但在该方法中存在因为在涂敷粘接层时内引线变形而产生废品的问题。但在本发明中,通过事先使内引线4与涂敷到支撑体8上的粘接层7粘接,可解决上述问题。
其后,通过金等键合焊丝13将半导体芯片10的压焊区电极11和内引线4互相连接。因为内引线4被固定于支撑体8,故在本实施例中可借助于支撑体8的背部的真空吸力来固定内引线4和进行焊丝键合,因此没有必要如常规引线框那样,使用窗式夹持器以加压方式来固定内引线。
在焊丝键合完成后,借助于由例如环氧树脂组成的密封体14将半导体芯片10、支撑体8、键合焊丝13和内引线4密封起来,并且将闭合杆6和联结杆19切去,由此将各个引线电分离开。之后,作为一个例子在图4中将从密封体14延伸的外引线5形成鸥翅形,这样就完成了半导体器件9。
实施例2
下面参照图5和图6描述作为本发明另一个实施例的半导体器件。图5是用于说明半导体芯片10的压焊区电极11的配置的平面图;图6是用于说明半导体芯片10角部处键合状态的局部放大平面图。
在本发明的半导体器件中,将半导体芯片10固定到支撑体8的半导体芯片安装区上,内引线4固定于该支撑体8上。因此,就不设置用于支撑安装半导体芯片的翼片(管心底座)的悬挂翼片引线,但已被用来设置翼片悬挂引线的区域则用来配置内引线4。
结果,在迄今被用来设置翼片悬挂引线的角部处也配置有内引线4,而且,相对于在沿包括角部的整个周边的各个内引线的末端处显示出间隔的引线间距,内引线在整个周边上以几乎相同的间距进行配置,并且即使在相同的引线间距的情况下,也可使内引线4的末端更接近于半导体芯片10。再有,在各个内引线4的末端处的引线间距P被设置为约180微米至220微米。
沿半导体芯片10的边缘部分设置成为半导体芯片10的外部端子的多个压焊区电极11,但在本实施例中,压焊区间距在越接近半导体芯片的角部时越变宽。
在图6中所示的实施例中,假定到半导体芯片10压焊区电极11内周边部分中心的压焊区间距是P1时,在逐渐接近角部的过程中是以P2=1.1P1、P3=1.2P1和P4=1.3P1的方式使压焊区间距各加宽0.1P1。再有,在用于高集成度的半导体器件的半导体芯片10中,压焊区电极11的间距则设置为80微米至100微米。
进行了用焊丝13连接压焊区电极11至内引线4的末端的键合,但在压焊区电极11中的配置中,越靠近角部,就越使压焊区间距变宽。因此,即使当焊丝13因焊丝移动等产生变形,也可防止在角部的焊丝13与邻近的焊丝13接触而产生短路。再有,是将直径约为25微米至35微米的金细丝等用作键合焊丝13。
此外,在半导体芯片10中,使周边部分外端处的压焊区电极11和在周边部分另一外端处的压焊区电极11,即邻近于压焊区电极11并将半导体芯片的角部置于其间的压焊区电极,之间的压焊区间距P5比其他压焊区间距宽,并使其比在该围绕焊丝13的一个牵引点部分的引线间距P6宽。
再有,由于在本实施例的焊丝键合情况下是将内引线4固定到支撑体8上,故可从支撑体8的背部借助于真空吸力进行与内引线4的焊丝键合。因此,没有必要如常规引线框那样,使用窗式夹持器以加压方式来固定内引线。
在焊丝键合完成后,借助于由例如环氧树脂组成的密封体14将半导体芯片10、支撑体8、键合焊丝13和内引线4密封起来,并且将闭合杆6和联结杆19切去,由此将各个引线电分离开。其后,作为一个例子,在图4中将从密封体14延伸的外引线5形成鸥翅形,这样就完成了半导体器件9。
在半导体器件的这一实施例中,与过去相比可减少约一半由于焊丝移动而产生的次品。
再有,至于扩展上述的压焊区间距,除了从上述的周边部分的中心均匀地扩展压焊区间距的方法外,还可通过局部地扩展角部的方法来实施本发明。
实施例3
其次,参照图7和图16描述作为本发明另一实施例的半导体器件。
图7是局部地示明用于本发明另一实施例的QFP型半导体器件的引线框的平面图,图16是局部地示明半导体器件的平面图。
引线框1例如由Fe-Ni合金或Cu合金组成,多个引线3的内引线4的末端配置在中心处的半导体芯片(用虚线示出)安装区2的整个周边上。
各个引线3的内引线4用绝缘粘合剂固定于支撑体8的表面上。作为粘合剂,例如可使用热固性树脂,如环氧树脂和苯酚树脂,或使用热塑性树脂,如聚乙烯树脂和氯乙烯树脂。
在本发明的半导体器件中,将半导体芯片10固定到支撑体8的半导体芯片安装区上,内引线4固定于该支撑体8。因此,就不设置用于支撑安装半导体芯片的翼片(管心底座)的悬挂翼片引线,但已用来设置翼片悬挂引线的区域则用来配置内引线4。
这样,在本实施例中,可沿半导体芯片安装区2的整个周边配置内引线4的末端,并使在对应于半导体芯片安装区2的角部的内引线4的末端处的引线间距比在其他内引线4处的引线间距宽。这样,当在安装半导体芯片之后进行焊丝键合时,焊丝13互相之间的间隔变宽,焊丝13中的短路减少。
这里,通过使用如Cu或Al料等具有高热导率的材料,可改善半导体器件的散热性。
此外,由于通过将多个引线3的内引线4固定到支撑体8改善了各个引线3的机械强度,故即使在将内引线4的引线间距做得很小时,也难以发生因外力引起的内引线变形。因此可防止产生键合焊丝13中的短路。
沿半导体芯片10的边缘部分设置多个压焊区电极11,但在本实施例中,压焊区间距在越接近半导体芯片的角部时越变宽。再有,在用于高集成度的半导体器件的半导体芯片10中,将压焊区电极11的间距设置为80微米至100微米。
进行了用焊丝13互相连接压焊区电极11至内引线4的末端的键合,但即使当焊丝13因焊丝移动等产生变形时,由于在压焊区电极11中,越靠近角部压焊区间距设置得越宽,故也可防止在角部的焊丝13与邻近的焊丝13接触而产生短路。再有,是将直径约为25微米至35微米的金细丝等用作键合焊丝13。
另外,在半导体芯片10中,使在边缘部分外端处的压焊区电极11和在边缘部分的另一外端处的压焊区电极11之间的压焊区间距比别的压焊区间距宽,以便在一定程度上提供通用性,并使其有时比引线间距还宽。在这种情况下,也可通过使上述在外端的压焊区电极11更靠近角部来扩大压焊区间距。
还有,由于在本实施例的焊丝键合情况下是将内引线4固定到支撑体8上,故可从支撑体8的背部借助于真空吸力进行与内引线4的焊丝键合。因此,没有必要如常规引线框那样,使用窗式夹持器以加压方式来固定内引线。
在焊丝键合完成后,借助于由例如环氧树脂组成的密封体14将半导体芯片10、支撑体8、键合焊丝13和内引线4密封起来,并且将闭合杆6和联结杆19切去,由此将各个引线电分离开而形成从密封体14延伸的外引线5,这样就完成了半导体器件9。
在本实施例的这一半导体器件中,与过去相比,可减少约一半由于焊丝移动而产生的次品。
再有,作为扩展上述的压焊区间距的方法,除了从上述的边缘部分的中心均匀地扩展压焊区间距的方法外,还可通过局部地扩展角部的方法等来实施本发明。
实施例4
其次参照图17描述本发明另一实施例的引线框。图17是用于说明引线框的局部放大平面图。
在本实施例的引线框1中,将半导体芯片(用虚线示出)固定到支撑体8的半导体芯片安装区2上,内引线4固定于该支撑体8。结果,可不设置用于支撑安装半导体芯片10的翼片(管心底座)的悬挂翼片引线,但已被用来设置翼片悬挂引线的区域则用来配置内引线4。
至于在这种内引线4的配置中于角部处配置外引线5时,是将外引线配置成稍微离开密封体14的角部,以便保护外引线5或保护树脂注入通道的安全。因而,有时碰巧会在密封体14的角部处产生一个不配置内引线的间隔。
当这样一种间隔产生时,在树脂注入时将在注入到该部分的树脂流中产生紊流。因此,有时产生空洞和使树脂注入不充分。
为了解决这种问题,根据本实施例,在迄今设置悬挂翼片引线的角部处设置一个虚设引线20,该虚设引线是一个在引线框切去后不引出到密封体之外的虚设内引线。该虚设引线20的宽度比其他内引线4的宽度宽,其末端设置在内引线4的末端之外,并使内引线4的末端配置在半导体芯片安装区2的整个周边上。
在本实施例中,通过该虚设引线20可防止在树脂流中产生紊流。因此,在本实施例的半导体器件中可减少因空洞引起树脂注入不充分的制品的产生。
此外,通过用虚设引线20固定支撑板8的四个角部,可更牢固地支撑该支撑板8。
再有,在引线框的状态下于工艺中来运送引线框的过程中,可在切去引线框之前通过夹住虚设引线20的密封体引出部分来进行运送,通过夹住和运送外引线5可防止外引线5的变形。
实施例5
其次参照图18和图19描述作为本发明另一实施例的半导体器件。图18是描述本发明人在先于本发明的阶段中研究过的半导体器件的局部放大平面图,而图19是用于描述本发明的半导体器件的局部放大平面图。
在图18中所示的半导体器件中,将内引线和在与这些内引线相对的半导体芯片的侧面上设置的压焊区电极互相连接。
但是,当有必要以不同类型的密封体密封相同的半导体芯片时,有时需要进行交叉键合,即将对应于半导体芯片的角部的内引线的末端连接到,沿邻近于与那些内引线相对的半导体芯片的一个侧面的另一侧面上设置的半导体芯片的压焊区电极。
在这种情况下,在常规的如图8中所示的,将半导体芯片10固定到翼片21和由悬挂翼片的引线22支撑该翼片21的半导体器件中,键合焊丝13与悬挂翼片的引线22交叉。因此,为了防止产生由于键合焊丝13与悬挂翼片的引线22之间的接触引起的不良情况,在这种键合中便作出了各种不同的限制,这样就使键合变得困难。
在本实施例的半导体器件中,将半导体芯片10固定到支撑体8上,而将该支持体8固定于内引线4上。因此,不提供用于安装半导体芯片10的翼片21(管心底座)和用于支撑该翼片的悬挂翼片引线22,但已被提供翼片悬挂引线22的区域则用来配置内引线4。
通过这种内引线4的配置,即使在进行上述的交叉键合时,也可消除由于键合焊丝13与悬挂翼片的引线22之间的接触产生不良情况,这样可改善制品的可靠性。
再有,容易进行上述的交叉键合,这样可改善键合的自由度。
实施例6
图8示明按照本发明的引线框的另一个实施例的截面图,图9示明使用该引线框制造的半导体器件的纵截面图。
按照本实施例的引线框1的特征在于,在支撑体8的半导体芯片安装区2与内引线4的末端之间设置有焊丝支撑部分15。
将该焊丝支撑部分15配置在支撑体8的安装区2的周围,在组装半导体器件时,该支撑部分15可以将键合在半导体芯片的压焊区电极和各个引线之间的一圈焊丝支撑于固定的高度上。该焊丝支撑部分15可通过下述方式来形成:用粘合剂等固定诸如聚酰亚胺树脂和环氧树脂的绝缘材料,或对支撑体8进行局部加工以便对至少是与焊丝接触的部分进行绝缘处理。
按照本实施例的这种引线框1,因为设置有用于支撑该键合焊丝的焊丝支撑部分15,故可保证焊丝的弯曲高度为恒定值。因此,可得到减少焊丝中相互短路的效果。
实施例7
图10是示明按照本发明的引线框的另一个实施例的截面图,图11是示明使用该引线框制造的半导体器件的纵截面图。
按照本实施例的引线框1的特征在于:除了具有业已描述的实施例的引线框结构外,还有在夹住支撑体8的半导体芯片安装区2与内引线4的末端之间的支撑体8的夹具16中设置的使焊丝支撑部分15伸出的狭缝17。
当引线框1为夹具16夹住时,在夹具16内设置的焊丝支撑部分15便从该狭缝17伸出。由于焊丝支撑部分15在焊丝键合完成后抽走,故其是否存在绝缘性没有关系。
按照本实施例,通过将设置在夹具16内的焊丝支撑部分15插入引线框1的狭缝17中,可得到稳定键合的效果。
实施例8
图12示明按照本发明的引线框的另一个实施例的截面图,图13示明使用该引线框制造的半导体器件的纵截面图。
按照本实施例的引线框1的特征在于:除了具有业已描述的实施例的引线框的结构外,让支撑体8的半导体芯片安装区2偏移,使得所安装的半导体芯片10的压焊区电极11和内引线4的表面显示出几乎相同的高度。通过使用众所周知的冲压技术等容易地加工出这种偏移结构。经过这种加工使内引线表面的高度位置H1与所安装的半导体芯片10的表面的高度位置H2几乎相等,在半导体芯片10的压焊区电极11和各个内引线4之间的焊丝键合的情况下,可增加被键合的一圈焊丝13的稳定性。由于通过增加焊丝圈13的稳定性使环状结构变得固定,故可减少在树脂模塑时的焊丝移动。
实施例9
图14是示明本发明的另一个实施例的引线框中使用的支撑体8的平面图,图15是示明在该支撑体8上安装半导体芯片10的状态的平面图。
按照本实施例的引线框1的特征在于:除了具有业已描述的实施例的引线框1的结构外,在支撑体8的表面上还设置有多个对应于不同类型的所安装的半导体芯片10的尺寸的标记18。通过印刷、冲压等技术可容易地设置这种标记18。
通过设置对应于待安装半导体芯片的尺寸的标记18来安装半导体芯片,易于确定用于安装半导体芯片的精确位置,从而可改善半导体芯片的芯片键合工作的效率。
再有,由于半导体芯片的位置精度得到改善,故可将焊丝长度保持为恒定,这样就可稳定地保持键合焊丝的环状。由于通过增加焊丝环状的稳定性使环状结构变得固定,故可减少在树脂模塑时的焊丝移动。
基于上述实施例,已具体地描述了本发明者作出的发明,但当然本发明不限于上述实施例,而是可在不偏离其要点的范围内在不同方面进行修正。
例如,在上述实施例中已图示了正方形支撑体作为固定各个引线的支撑体,但也可将圆形的支撑体用作支撑体。当使用这种圆形的支撑体时,由于树脂流在树脂模塑时变得平稳,故可得到减少空洞产生的效果。
此外,通过在用于上述实施例中的支撑体上设置目的在于接地键合的键合区,就可作为能完成接地键合的引线框而能获得更广泛的用途。
再有,在支撑体上安装的半导体芯片不限于一片,而是可安装多片半导体芯片,因此,本发明可应用于多片半导体器件。
已描述了这样一种情况,即主要由本发明人作出的本发明适用于作为本发明的领域的半导体器件,该领域已变成本发明的背景。但本发明不限于此,而是可广泛地适用于那些与使用引线框的电子元件一起进行封装的装置。
以下简要地描述本申请所公开的典型发明可得到的效果。
(1)根据本发明,存在下述效果:通过以相同间隔在半导体芯片安装区的整个周边上配置内引线的末端,可使内引线末端更接近于半导体芯片安装区。
(2)根据本发明,存在下述效果:由于上述(1)项中描述的效果,键合焊丝的长度可缩短。
(3)根据本发明,存在下述效果:沿半导体芯片安装区的整个周边配置内引线的末端,使对应于半导体芯片安装区的角部的内引线的末端的引线间距比在其他内引线的末端的引线间距宽。
(4)根据本发明,存在下述效果:借助于在上述(3)项中描述的效果,使键合焊丝中的相互间隔在角部处加宽。
(5)根据本发明,存在下述效果:借助于在上述(2)和(4)项中描述的效果,可减少邻近的焊丝互相接触引起的短路或焊丝因模塑树脂的流动而变形的焊丝移动。
(6)根据本发明,存在下述效果:通过在支撑体上安装半导体芯片,在半导体芯片中产生的热量可经由支撑体向外散发,因此可改善半导体芯片的散热特性。
(7)根据本发明,存在下述效果:通过设置虚设引线,可防止因注入树脂流的扰动引起的空洞的产生。
(8)根据本发明,存在下述效果:通过除去悬挂翼片的引线,可容易地完成交叉键合。
Claims (10)
1.半导体器件,包括:
衬底;
安装于所述衬底一面上的半导体芯片,所述半导体芯片在其主表面上形成有集成电路和键合压焊区,所述半导体芯片的所述主表面为四边形,所述键合压焊区沿所述半导体芯片的所述主表面的四边布置;
位于所述衬底的所述一面上沿其四边包围所述半导体芯片的多个导体;
将所述键合压焊区分别电连接于所述导体的末端的多条键合焊丝;以及
密封所述半导体芯片和所述多条键合焊丝的树脂体;
其中,所述半导体芯片所述主表面的所述四边限定的四个角部的每一个角部处相邻的第1键合压焊区之间的间距比所述四个角部之外的所述四边每一边的相对中心位置处相邻的第2键合压焊区之间的间距宽。
2.权利要求1的半导体器件,其中,所述半导体芯片用热固性树脂键合于所述衬底。
3.权利要求1的半导体器件,其中,所述衬底包括形成于其所述一面上的绝缘层。
4.权利要求3的半导体器件,其中,所述导体形成于所述衬底的所述绝缘层上。
5.权利要求1的半导体器件,其中,所述导体材料的主要成分为铜。
6.半导体器件,包括:
衬底;
安装于所述衬底一面上的半导体芯片,所述半导体芯片在其主表面上形成有集成电路和键合压焊区,所述半导体芯片的所述主表面为四边形,所述键合压焊区沿所述半导体芯片的所述主表面的四边布置;
位于所述衬底的所述一面上沿其四边包围所述半导体芯片的多个导体;
将所述键合压焊区分别电连接于所述导体的末端的多条键合焊丝;以及
密封所述半导体芯片和所述多条键合焊丝的树脂体;
其中,所述键合压焊区包括位于所述半导体芯片所述主表面的所述四边限定的四个角部的每一个角部处相邻的第1键合压焊区和位于与所述相邻的第1键合压焊区相比离所述四个角部更远的区域处相邻的第2键合压焊区,并且
所述相邻的第1键合压焊区之间的间距比所述相邻的第2键合压焊区之间的间距宽。
7.权利要求6的半导体器件,其中,所述半导体芯片用热固性树脂键合于所述衬底。
8.权利要求6的半导体器件,其中,所述衬底包括形成于其所述一面上的绝缘层。
9.权利要求8的半导体器件,其中,所述导体形成于所述衬底的所述绝缘层上。
10.权利要求7的半导体器件,其中,所述导体材料的主要成分为铜。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP6042196 | 1996-03-18 | ||
JP060421/1996 | 1996-03-18 | ||
JP008964/1997 | 1997-01-21 | ||
JP9008964A JPH09312375A (ja) | 1996-03-18 | 1997-01-21 | リードフレーム、半導体装置及び半導体装置の製造方法 |
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CNB971033129A Division CN1156910C (zh) | 1996-03-18 | 1997-03-17 | 引线框、使用该引线框的半导体器件及其制造方法 |
Publications (2)
Publication Number | Publication Date |
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CN1595646A true CN1595646A (zh) | 2005-03-16 |
CN100359678C CN100359678C (zh) | 2008-01-02 |
Family
ID=26343600
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100368185A Expired - Fee Related CN100359678C (zh) | 1996-03-18 | 1997-03-17 | 半导体器件 |
CNB971033129A Expired - Fee Related CN1156910C (zh) | 1996-03-18 | 1997-03-17 | 引线框、使用该引线框的半导体器件及其制造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB971033129A Expired - Fee Related CN1156910C (zh) | 1996-03-18 | 1997-03-17 | 引线框、使用该引线框的半导体器件及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6265762B1 (zh) |
JP (1) | JPH09312375A (zh) |
KR (2) | KR100475265B1 (zh) |
CN (2) | CN100359678C (zh) |
MY (1) | MY121618A (zh) |
TW (1) | TW347585B (zh) |
Families Citing this family (24)
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US6692989B2 (en) * | 1999-10-20 | 2004-02-17 | Renesas Technology Corporation | Plastic molded type semiconductor device and fabrication process thereof |
JPH11274196A (ja) * | 1998-03-26 | 1999-10-08 | Seiko Epson Corp | 半導体装置の製造方法およびモールドシステム並びに半導体装置 |
KR100350046B1 (ko) * | 1999-04-14 | 2002-08-24 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 방열판이 부착된 반도체패키지 |
US6975021B1 (en) * | 1999-09-03 | 2005-12-13 | Micron Technology, Inc. | Carrier for substrate film |
JP2001230360A (ja) * | 2000-02-18 | 2001-08-24 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US7199477B1 (en) * | 2000-09-29 | 2007-04-03 | Altera Corporation | Multi-tiered lead package for an integrated circuit |
JP2002134674A (ja) * | 2000-10-20 | 2002-05-10 | Hitachi Ltd | 半導体装置およびその製造方法 |
TW462120B (en) * | 2000-11-10 | 2001-11-01 | Siliconware Precision Industries Co Ltd | Tape carrier type semiconductor package structure |
JP2002176131A (ja) * | 2000-12-08 | 2002-06-21 | Hitachi Ltd | 半導体装置の製造方法 |
JP3812447B2 (ja) * | 2002-01-28 | 2006-08-23 | 富士電機デバイステクノロジー株式会社 | 樹脂封止形半導体装置 |
KR100477020B1 (ko) * | 2002-12-16 | 2005-03-21 | 삼성전자주식회사 | 멀티 칩 패키지 |
US7239024B2 (en) * | 2003-04-04 | 2007-07-03 | Thomas Joel Massingill | Semiconductor package with recess for die |
US20050230821A1 (en) * | 2004-04-15 | 2005-10-20 | Kheng Lee T | Semiconductor packages, and methods of forming semiconductor packages |
US7511364B2 (en) * | 2004-08-31 | 2009-03-31 | Micron Technology, Inc. | Floating lead finger on a lead frame, lead frame strip, and lead frame assembly including same |
US7388283B2 (en) * | 2005-02-04 | 2008-06-17 | Avago Technologies Ecbu Ip Pte Ltd | Method and device for integrating an illumination source and detector into the same IC package that allows angular illumination with a common planar leadframe |
JP2006278407A (ja) * | 2005-03-28 | 2006-10-12 | Renesas Technology Corp | 半導体装置の製造方法 |
US8110913B2 (en) * | 2007-06-29 | 2012-02-07 | Stats Chippac Ltd. | Integrated circuit package system with integral inner lead and paddle |
US7750444B2 (en) * | 2008-05-19 | 2010-07-06 | Powertech Technology Inc. | Lead-on-chip semiconductor package and leadframe for the package |
US9337240B1 (en) * | 2010-06-18 | 2016-05-10 | Altera Corporation | Integrated circuit package with a universal lead frame |
CN102332441B (zh) * | 2010-07-12 | 2014-05-14 | 无锡华润安盛科技有限公司 | 一种高线位封装形式的引线框及其封装结构 |
US8450841B2 (en) * | 2011-08-01 | 2013-05-28 | Freescale Semiconductor, Inc. | Bonded wire semiconductor device |
US8841758B2 (en) * | 2012-06-29 | 2014-09-23 | Freescale Semiconductor, Inc. | Semiconductor device package and method of manufacture |
JP6100648B2 (ja) | 2013-08-28 | 2017-03-22 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
CN108735701B (zh) * | 2017-04-13 | 2021-12-24 | 恩智浦美国有限公司 | 具有用于包封期间的毛刺缓解的虚设引线的引线框架 |
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JPS59105349A (ja) * | 1982-12-08 | 1984-06-18 | Hitachi Ltd | 集積回路装置 |
JP2637247B2 (ja) * | 1989-09-12 | 1997-08-06 | 株式会社東芝 | 樹脂封止型半導体装置 |
US4992628A (en) * | 1990-05-07 | 1991-02-12 | Kyocera America, Inc. | Ceramic-glass integrated circuit package with ground plane |
JPH04162556A (ja) * | 1990-10-25 | 1992-06-08 | Mitsubishi Electric Corp | リードフレーム及びその製造方法 |
US5245214A (en) * | 1991-06-06 | 1993-09-14 | Northern Telecom Limited | Method of designing a leadframe and a leadframe created thereby |
US5510649A (en) * | 1992-05-18 | 1996-04-23 | Motorola, Inc. | Ceramic semiconductor package having varying conductive bonds |
JPH07231007A (ja) * | 1994-02-15 | 1995-08-29 | Toshiba Corp | 半導体装置 |
JPH0837252A (ja) * | 1994-07-22 | 1996-02-06 | Nec Corp | 半導体装置 |
US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
JPH0945723A (ja) * | 1995-07-31 | 1997-02-14 | Rohm Co Ltd | 半導体チップおよびこの半導体チップを組み込んだ半導体装置ならびにその製造方法 |
US5691567A (en) * | 1995-09-19 | 1997-11-25 | National Semiconductor Corporation | Structure for attaching a lead frame to a heat spreader/heat slug structure |
US5905299A (en) * | 1996-01-05 | 1999-05-18 | Texas Instruments, Inc. | Thermally enhanced thin quad flatpack package |
US5771157A (en) * | 1996-03-08 | 1998-06-23 | Honeywell, Inc. | Chip-on-board printed circuit assembly using aluminum wire bonded to copper pads |
-
1997
- 1997-01-21 JP JP9008964A patent/JPH09312375A/ja active Pending
- 1997-03-05 TW TW086102661A patent/TW347585B/zh not_active IP Right Cessation
- 1997-03-12 MY MYPI97001026A patent/MY121618A/en unknown
- 1997-03-14 KR KR1019970008685A patent/KR100475265B1/ko not_active IP Right Cessation
- 1997-03-17 CN CNB2004100368185A patent/CN100359678C/zh not_active Expired - Fee Related
- 1997-03-17 CN CNB971033129A patent/CN1156910C/zh not_active Expired - Fee Related
- 1997-03-18 US US08/820,228 patent/US6265762B1/en not_active Expired - Lifetime
-
2004
- 2004-04-02 KR KR1020040022788A patent/KR100473261B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
MY121618A (en) | 2006-02-28 |
CN1164127A (zh) | 1997-11-05 |
KR970067736A (ko) | 1997-10-13 |
CN100359678C (zh) | 2008-01-02 |
KR100473261B1 (ko) | 2005-03-14 |
US6265762B1 (en) | 2001-07-24 |
JPH09312375A (ja) | 1997-12-02 |
TW347585B (en) | 1998-12-11 |
CN1156910C (zh) | 2004-07-07 |
KR100475265B1 (ko) | 2005-07-01 |
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