CN1591832A - 低功率快擦写存储单元及方法 - Google Patents
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Abstract
本发明的目的是降低快擦写存储单元的编程电压。提供了形成快擦写存储单元的方法。该方法包括:在衬底上形成第1多晶硅层的工序;通过第1多晶硅层,直至衬底中形成沟槽的工序;向沟槽中填充氧化物层的工序;在氧化物上堆积第2多晶硅层的工序。得到的结构可进行平面化。高k电介质层可堆积在第1多晶硅层上。第3多晶硅层堆积在高k电介质层上,利用光刻胶形成图形,形成快擦写存储栅极结构。形成图形过程中,露出的第2多晶硅层被蚀刻。结束除去第2多晶硅层时,检测蚀刻停止。残留下第1多晶硅层的薄层,然后利用选择性蚀刻法小心除去。可对高k电介质层形成图形,使非存储晶体管的形成成为可能。
Description
技术领域
交叉引用
本申请是2002年3月29日提出的名为“Method of Making Self-Aligned Shallow Trench Isolation”的美国专利申请第10/112,014号的部分继续申请。本说明书中以该申请作为参考并进行了引用。
背景技术
利用多晶(poly)层间绝缘膜位于浮悬多晶硅栅与控制多晶硅栅之间的双层多晶硅结构可在衬底上形成快擦写存储单元。隧道氧化物位于浮悬多晶硅栅与衬底之间。
发明内容
快擦写存储单元的编程电压由生成流过隧道氧化物的隧道电流所需的场而决定。隧道氧化物位于浮悬多晶硅栅与衬底(例如块状硅)之间。隧道氧化物及多晶层间绝缘膜越薄,编程电压就越低。随着氧化物层变薄,漏电流增大,电荷保持时间降低。所需的电荷保持时间设定隧道氧化物与多晶层间绝缘膜二者厚度的下限。
制造本发明的快擦写存储单元的方法包括:以在衬底上重叠的方式,以隧道氧化物层位于上述衬底与上述第1多晶硅层之间的形式形成具有底面及上面的第1多晶硅层的工序;通过上述第1多晶硅层直至上述衬底中形成沟槽的工序;以在上述衬底上重叠的方式,直至上述沟槽内的上述场氧化物层的上述上面比上述第1多晶硅层的上述底面还高的厚度,形成具有上面的场氧化物层的工序;以在上述场氧化物层上重叠的方式,直至上述沟槽内的上述第2多晶硅层的上述上面比上述第1多晶硅层的上述上面还低的厚度,形成具有上面的第2多晶硅层的工序;在上述第2多晶硅层上形成牺牲氧化物层的工序;将上述第2多晶硅层、上述场氧化物层及上述第1多晶硅层平面化的工序;在上述第1多晶硅层的上述上面及上述第2多晶硅层的上述上面上,停止上述平面化工序的工序;以重叠在上述第1多晶硅层上的方式,堆积高k介电材料的工序;以重叠在上述高k介电材料上的方式,堆积第3多晶硅层的工序。
上述场氧化物层也可以通过下述方法形成,即,使薄的热氧化物生长,利用CVD方法或溅射法来堆积上述氧化物的剩余部分。
上述隧道氧化物层也可以是二氧化硅。
上述高k介电材料也可以是氧化铪或氧化锆。
还可以进一步包括:堆积光刻胶,按照定义栅极结构的方式形成图形的工序;选择性蚀刻上述第3多晶硅层、上述高k介电材料、上述第2多晶硅层、及上述第1多晶硅层的工序;除去上述第2多晶硅层的露出区域后,停止上述选择性蚀刻,并留下露出的第1多晶硅层的薄层的工序。
还可以进一步包括使用选择性高的蚀刻法来选择性蚀刻上述残留并露出的第1多晶硅层,不用过量除去位于下面的上述隧道氧化物层而除去上述残留并露出的第1多晶硅层的工序。
还可以进一步包括:堆积上述第3多晶硅层的工序之前,附加重叠在上述高k介电材料上的光刻胶,并形成图形的工序;从形成非存储晶体管的区域除去上述高k介电材料的工序。
还可以进一步包括:在附加上述光刻胶,形成图形的工序之前,在上述高k介电材料上堆积牺牲多晶硅层的工序;从形成上述非存储晶体管的上述区域除去上述牺牲多晶硅层的工序。
本发明的快擦写存储单元结构具备重叠在衬底上的隧道氧化物、重叠在上述隧道氧化物上的浮悬多晶硅栅、重叠在上述浮悬多晶硅栅上的高k电介质层、重叠在上述高k电介质层上的控制栅极。
上述高k电介质层也可以是氧化铪或氧化锆。
还可以进一步具备通过含有上述隧道氧化物、上述浮悬多晶硅栅、上述高k电介质层及上述控制栅极的栅极叠层(stack)而互相分隔的源极区和漏极区。
通过将二氧化硅多晶层间绝缘膜与具有高k介电常数及低漏电流的材料交换,可降低编程电压。
在控制栅极上施加编程电压(VG)生成浮悬栅极中的电压(VFG)。通过下式可得到浮悬栅极电压。
[数式1]
其中,C为电容,t为厚度,ε为绝缘体的介电常数。下标文字的T及P分别表示与隧道氧化物或多晶层间绝缘膜相关的参数。浮悬栅极电压随着隧道氧化物厚度(tT)的增加、多晶层间绝缘膜厚度(tp)的降低、及多晶层间绝缘膜介电常数(εp)的增加而增加。介电常数的增加及多晶层间绝缘膜厚度的降低是增加浮悬栅极电压的优选方法之一,对应于编程电压的降低。虽然增加隧道氧化物厚度会使浮悬栅极电压也增加,但是该方案会在隧道氧化物厚度增加的同时使隧道电流按指数函数方式降低,因此不优选。为了维持期望的隧道电流,优选尽可能薄地维持隧道氧化物。因此,降低编程电压的优选方法之一是将多晶层间(多晶间)二氧化硅与高k介电材料交换。
因此,提供了位于控制栅极与多晶硅浮悬栅极间的高k介电材料,例如,含有氧化铪或氧化锆的快擦写存储单元结构。隧道氧化物位于浮悬栅极与衬底之间。
还提供了形成快擦写存储单元的方法。该方法包括:在衬底上形成第1多晶硅层的工序;通过第1多晶硅层,直至衬底中形成沟槽的工序;向沟槽中填充氧化物层的工序;按使沟槽内的第2多晶硅层的底部比第1多晶硅层的底部高、使沟槽内的第2多晶硅层的上部比第1多晶硅层的上部低的方式,在氧化物上堆积第2多晶硅层的工序。之后,得到的结构可用CMP方法进行平面化。高k电介质层可堆积在第1多晶硅层上。之后,第3多晶硅层堆积在高k电介质层上,利用光刻胶形成图形,形成快擦写存储栅极结构。形成图形过程中,露出的第2多晶硅层被蚀刻。结束除去第2多晶硅层时,检测蚀刻停止。留下第1多晶硅层的薄层,利用接续其后的选择性蚀刻法小心除去。可对高k电介质层形成图形,以在形成快擦写存储单元的方法的同时使非存储晶体管的形成成为可能。
本发明可降低快擦写存储单元的编程电压(写入电压)。
具体实施方式
根据本发明方法提供了半导体衬底。需要时,可在分离相邻器件区域之前形成n阱(well)或p阱。需要时,也可以调整阈值电压。在此,在有参照图1,n阱或p阱时,在形成n阱或p阱之后,以重叠在半导体衬底14上的方式,生长或生长及堆积隧道氧化物层(二氧化硅)12,以重叠在隧道氧化物层12上的方式,堆积第1多晶硅层16,由此形成器件结构10。在本说明书全文中将第1多晶硅层16称为多晶1。第1多晶硅层16作为浮悬多晶硅栅发挥功能。多晶1的厚度用Tp1来表示。
图2表示的是器件结构10的截面,该器件结构10包含为了形成沟槽18在蚀刻半导体衬底14后的2个相邻器件区域17。沟槽18的深度用XST1表示,从衬底表面20的上部跨至沟槽18的底面22。沟槽深度的不确定性,即偏差,用ΔXST1表示。蚀刻衬底后,为了降低或消除蚀刻损伤,可进行清洁。
图3为表示氧化物层30堆积后的器件结构10的图。为了向沟槽中再填充氧化物,氧化物层30被堆积。氧化物层30具有的厚度的最小值大于沟槽可能有的深度的最大值。用TOX表示氧化物厚度,用ΔTOX表示氧化物厚度的不确定性,即偏差,堆积、处理氧化物层30,以使最终处理的厚度满足下面的条件。
TOX-ΔTOX>XST1+ΔXST1
为了提供场中硅与氧化物间良好的界面,氧化物可含有生长的薄热氧化物,随后接续堆积的氧化物。所堆积的氧化物可由化学汽相淀积(CVD)法,例如包括LTO、HPCVD、PECVD或其他的CVD法的种种方法而形成。也可以使用CVD以外的方法,例如溅射法等。利用任意的适当方法进行了氧化物的堆积后,必要时,或希望时,氧化物在更高温度下被致密化。
如图4所示,按重叠在器件结构10上的方式,第2多晶硅层40被堆积。在本说明书中第2多晶硅层40被称作多晶2,或场多晶。多晶2的厚度用TP2表示。选择多晶2具有的厚度,以使多晶2厚度的最大值加上氧化物层30厚度的最大值,比沟槽深度的最小值加上多晶1厚度的最小值小。因此,多晶2的厚度需要满足以下条件。
TP2+ΔTP2+TOX+ΔTOX<XST1-ΔXST1+TP1-ΔTP1
为了满足该条件,且使多晶2的厚度有意义,希望的氧化物的厚度具有最大值。氧化物层30的最大厚度需要满足以下条件。
TOX+ΔTOX<XST1-ΔXST1+TP1-ΔTP1-TP2-ΔTP2
由此,沟槽内氧化物的上面水平变得高于多晶1的底面水平,沟槽内多晶2的上面水平变得低于多晶1的上面水平。
堆积多晶2后,以重叠在器件结构10上的方式,牺牲氧化物层(未图示)被堆积。牺牲氧化物层,例如,可以是未致密化的TEOS。在某些实施方式中,牺牲氧化物层的厚度为多晶1厚度最大值的1.5倍。在其他的实施方式中,牺牲氧化物层的厚度要使得隧道氧化物层12、多晶1、氧化物层30、多晶2与牺牲氧化物层的组合厚度达到相应于上面的实际物理起伏的有源区特征的总体阶梯(step)高度的大致2倍。
然后,如图5所示,为了研磨氧化物层30,用CMP研磨器件结构10,在场区域中第2多晶硅层40的上部停止。这可以用2步法来实现。在第1工序中,为了除去重叠在上面的氧化物及重叠在器件区域内的有源区上的第2多晶硅层40的一部分,使用非选择性浆料。第2工序继续除去氧化物,并利用在有源区中第1多晶硅层16及场区域中第2多晶硅层40停止的选择性研磨。实际的场氧化物在该停止时不研磨。在选择性研磨过程中,有源区比场区域小得多,可选择以使氧化物的研磨率也比多晶硅的研磨率足够高,例如,大于5∶1的氧化物对多晶硅的蚀刻比。因此,该CMP方法可以很容易实现。
由于TP2+ΔTP2+TOX+ΔTOX<XST1-ΔXST1+TP1-ΔTP1,因此多晶1上的氧化物在场多晶2中CMP停止前完全除去。
如图6所示,CMP后,以重叠在器件结构10上的方式,堆积高k介电材料58。高k介电材料是指介电常数比二氧化硅还高的介电材料。可用的优选高k介电材料含有ZrO2及HfO2。例如ZrO2的厚度为12.9nm的膜的相对介电常数为18,漏电流在2伏下为200nA/cm2。HfO2的厚度为8nm的膜的相对介电常数为15,漏电流在1.5伏下为170nA/cm2。漏电流与厚度的平方根成反比例,按指数函数方式降低。因此,更厚的的ZrO2及HfO2的漏电流不比CVD氧化物膜的漏电流大。高k介电材料可提供现在快擦写存储晶体管使用的多氧化物材料的适当替代品。以重叠在高k介电材料58上的方式,堆积第3多晶硅层60。本说明书中称第3多晶硅层60为多晶3。
虽然没有非存储晶体管也可以制造快擦写存储单元,但在某些实施方式中,在还含有非存储晶体管的衬底上制造了快擦写存储单元。同时制造快擦写存储单元及非存储晶体管时,优选使方法的工序尽可能具有互换性。非存储晶体管与快擦写存储单元同时制造的时候,为了保护快擦写存储单元上重叠的高k介电材料,附加光刻胶层,形成图形。之后,可从重叠在非存储晶体管上的区域蚀刻高k介电材料。之后,剥去光刻胶。在该实施方式中,第3多晶硅层60堆积在形成快擦写存储单元的区域中残留的高k介电材料58上,如图7所示,堆积在非存储晶体管区域中多晶1层16上。非存储晶体管的实际栅极多晶硅厚度相当于多晶3厚度加上CMP后残留的多晶1厚度之和。
在包括与快擦写存储单元同时形成非存储晶体管的别的实施方式中,在附加光刻胶及形成图形之前,将牺牲多晶硅层(未图示)堆积在高k介电材料上。在从重叠在非存储晶体管上的区域除去高k介电材料前,或除去的同时,从这些区域除去牺牲多晶硅。在包括剥去光刻胶的图形形成过程中,该牺牲多晶硅层可保护高k介电材料。之后,当堆积第3多晶硅层60时,重叠在具有高k介电材料的区域上残留的牺牲多晶硅上。牺牲多晶硅及多晶硅60可共同形成快擦写存储单元的控制栅极。
在此,参照图8,附加光刻胶70,形成图形以定义快擦写存储栅极结构72。在几个实施方式中,非存储晶体管栅极结构74可以与快擦写存储栅极结构72同时定义。为了蚀刻多晶3/高k/多晶1叠层、及多晶3/多晶2叠层,在非存储晶体管结构的情况下,或许连同多晶3/多晶1叠层,可以使用具有数道工序的蚀刻方法。一部分多晶2原样位于多晶3及光刻胶的下面,在有高k介电材料的情况下,原样位于高k介电材料下面。由于TOX-ΔTOX>XST1+ΔXST1,如图9所示,多晶1没有从有源区完全被除去。图9是将图8所示的器件结构旋转90度,沿快擦写存储晶体管结构的源极/沟道/漏极的截面看到的截面图。残留的多晶1的厚度不依赖于CMP法。除了光刻胶下残留的部分,除去第2多晶硅层40后,为了蚀刻未由光刻胶覆盖的第1多晶硅层16的剩余部分,使用了选择性高的蚀刻法。在多晶2的底部停止,在隧道氧化物层12上残留多晶1的薄层,实施选择性高的蚀刻法除去残留的多晶1的薄层,由此,微沟槽可以减少或消除。通过利用选择性高的等离子体蚀刻法,不过多地除去源极及漏极区域中的隧道氧化物12,就可选择性地除去多晶1的剩余部分。
之后,如图10所示,残留含有各有源区上的多晶1、高k介电材料、及多晶3的残留部分的快擦写存储栅极结构72,剥去光刻胶。一部分多晶2虽然没有在图10中显示出来,但残留在超出多晶3的有源区而延伸的部分之下。
形成栅极结构后,为了形成相对栅极结构自对准的源极及漏极区,可采用离子注入。按现有方法中常见的那样,可将多晶1、多晶2、及多晶3也变换为n+或p+多晶硅。或者,在蚀刻栅极电极前,且离子注入源极及漏极前,可掺杂快擦写存储栅极结构。另外,可对多晶硅栅极进行自对准硅化。进行包括自对准硅化方法的多晶硅栅极掺杂、硅化、或自对准方法的几种方法可适用于现行方法。掺杂后的快擦写存储栅极结构72如图11所示。图11还显示了埋入的源极及漏极区76。源极及漏极区76被包含隧道氧化物、浮悬多晶硅栅、高k电介质层及控制栅极的栅极叠层相互分隔。
以上说明了包含可能的变形例的例示性实施方式,但本发明并不限于这些实例,本发明的范围是由附录的权利要求书的范围所决定的。
附图说明
[图1]
图1是处理中的器件结构的截面图。
[图2]
图2是处理中的器件结构的截面图。
[图3]
图3是处理中的器件结构的截面图。
[图4]
图4是处理中的器件结构的截面图。
[图5]
图5是处理中的器件结构的截面图。
[图6]
图6是处理中的器件结构的截面图。
[图7]
图7是处理中的器件结构的截面图。
[图8]
图8是处理中的器件结构的截面图。
[图9]
图9是将图8所示的器件结构旋转90度的截面图。
[图10]
图10是进一步处理后的、从与图9相同的方向看到的器件结构的截面图。
[图11]
图11是形成源极及漏极区后的、从与图10相同的方向看到的器件结构的截面图。
符号说明
10器件结构
12隧道氧化物层
14半导体衬底
16第1多晶硅层
30氧化物层
58高k介电材料
60第3多晶硅层
72快擦写存储栅极结构
76源极及漏极区
Claims (11)
1.快擦写存储单元的制造方法,包括:
以重叠在衬底上的方式,按隧道氧化物层位于该衬底与该第1多晶硅层之间的方式形成具有底面及上面的第1多晶硅层的工序;
通过该第1多晶硅层,直至该衬底中形成沟槽的工序;
以重叠在该衬底上的方式,按直至该沟槽内的该场氧化物层的该上面比该第1多晶硅层的该底面还高的厚度,形成具有上面的场氧化物层的工序;
以重叠在该场氧化物层上的方式,按直至该沟槽内的该第2多晶硅层的该上面比该第1多晶硅层的该上面还低的厚度,形成具有上面的第2多晶硅层的工序;
在该第2多晶硅层上形成牺牲氧化物层的工序;
将该第2多晶硅层、该场氧化物层及该第1多晶硅层平面化的工序;
在该第1多晶硅层的该上面及该第2多晶硅层的该上面处,停止该平面化工序的工序;
以重叠在该第1多晶硅层上的方式,堆积高k介电材料的工序;
与
以重叠在该高k介电材料上的方式,堆积第3多晶硅层的工序。
2.权利要求1记载的方法,其中,前述场氧化物层通过使薄的热氧化物生长,利用CVD方法或溅射法来堆积前述氧化物的剩余部分而形成。
3.权利要求1记载的方法,其中,前述隧道氧化物层是二氧化硅。
4.权利要求1记载的方法,其中,前述高k介电材料是氧化铪或氧化锆。
5.权利要求3记载的方法,进一步包括:
堆积光刻胶,按照定义栅极结构的方式形成图形的工序;
选择性蚀刻前述第3多晶硅层、前述高k介电材料、前述第2多晶硅层、及前述第1多晶硅层的工序;与
除去该第2多晶硅层的露出区域后,停止该选择性蚀刻,留下露出的第1多晶硅层的薄层的工序。
6.权利要求5记载的方法,进一步包括使用选择性高的蚀刻法来选择性蚀刻前述残留并露出的第1多晶硅层,不用过量除去位于下面的前述隧道氧化物层而除去前述残留并露出的第1多晶硅层的工序。
7.权利要求1记载的方法,进一步包括:
堆积前述第3多晶硅层的工序之前,附加并成图形化重叠在前述高k介电材料上的光刻胶的工序;与
从形成非存储晶体管的区域除去前述高k介电材料的工序。
8.权利要求7记载的方法,进一步包括:
在附加并成图形化上述光刻胶的工序之前,在前述高k介电材料上堆积牺牲多晶硅层的工序;与
从形成前述非存储晶体管的前述区域除去前述牺牲多晶硅层的工序。
9.快擦写存储单元结构,具备重叠在衬底上的隧道氧化物、重叠在该隧道氧化物上的浮悬多晶硅栅、重叠在该浮悬多晶硅栅上的高k电介质层和重叠在该高k电介质层上的控制栅极。
10.权利要求9记载的快擦写存储单元结构,其中,前述高k电介质层是氧化铪或氧化锆。
11.权利要求9记载的快擦写存储单元结构,进一步具备通过含有前述隧道氧化物、前述浮悬多晶硅栅、前述高k电介质层及前述控制栅极的栅极叠层而彼此分隔的源极区和漏极区。
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JP2003318287A (ja) * | 2002-04-19 | 2003-11-07 | Hitachi Ltd | 不揮発性半導体記憶装置およびその製造方法 |
US6548855B1 (en) * | 2002-05-16 | 2003-04-15 | Advanced Micro Devices, Inc. | Non-volatile memory dielectric as charge pump dielectric |
US6682973B1 (en) * | 2002-05-16 | 2004-01-27 | Advanced Micro Devices, Inc. | Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications |
US6617639B1 (en) * | 2002-06-21 | 2003-09-09 | Advanced Micro Devices, Inc. | Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling |
US6753570B1 (en) * | 2002-08-20 | 2004-06-22 | Advanced Micro Devices, Inc. | Memory device and method of making |
US7122415B2 (en) * | 2002-09-12 | 2006-10-17 | Promos Technologies, Inc. | Atomic layer deposition of interpoly oxides in a non-volatile memory device |
-
2003
- 2003-07-17 US US10/622,667 patent/US6858514B2/en not_active Expired - Lifetime
-
2004
- 2004-07-15 EP EP04016720A patent/EP1498945A3/en not_active Withdrawn
- 2004-07-16 TW TW093121384A patent/TWI248171B/zh not_active IP Right Cessation
- 2004-07-16 JP JP2004210860A patent/JP2005039280A/ja active Pending
- 2004-07-16 KR KR1020040055777A patent/KR100587186B1/ko not_active IP Right Cessation
- 2004-07-19 CN CNB200410069696XA patent/CN100353526C/zh not_active Expired - Fee Related
- 2004-10-29 US US10/976,596 patent/US20050088898A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106057669A (zh) * | 2016-06-24 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | Igbt终端场氧工艺方法 |
Also Published As
Publication number | Publication date |
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US20050088898A1 (en) | 2005-04-28 |
TW200525705A (en) | 2005-08-01 |
TWI248171B (en) | 2006-01-21 |
US20040140504A1 (en) | 2004-07-22 |
EP1498945A2 (en) | 2005-01-19 |
CN100353526C (zh) | 2007-12-05 |
EP1498945A3 (en) | 2007-09-26 |
JP2005039280A (ja) | 2005-02-10 |
KR100587186B1 (ko) | 2006-06-08 |
US6858514B2 (en) | 2005-02-22 |
KR20050009246A (ko) | 2005-01-24 |
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