CN1581493A - 半导体电容器结构及其制造方法 - Google Patents
半导体电容器结构及其制造方法 Download PDFInfo
- Publication number
- CN1581493A CN1581493A CNA2004100574568A CN200410057456A CN1581493A CN 1581493 A CN1581493 A CN 1581493A CN A2004100574568 A CNA2004100574568 A CN A2004100574568A CN 200410057456 A CN200410057456 A CN 200410057456A CN 1581493 A CN1581493 A CN 1581493A
- Authority
- CN
- China
- Prior art keywords
- wall
- layer
- semiconductor device
- sacrifice
- memory node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (44)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030056009A KR100546363B1 (ko) | 2003-08-13 | 2003-08-13 | 콘케이브 형태의 스토리지 노드 전극을 갖는 반도체메모리 소자 및 그 제조방법 |
KR56009/2003 | 2003-08-13 | ||
US10/835,142 | 2004-04-28 | ||
US10/835,192 | 2004-04-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1581493A true CN1581493A (zh) | 2005-02-16 |
CN100454549C CN100454549C (zh) | 2009-01-21 |
Family
ID=37227662
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100574568A Active CN100454549C (zh) | 2003-08-13 | 2004-08-12 | 半导体电容器结构及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7018892B2 (zh) |
KR (1) | KR100546363B1 (zh) |
CN (1) | CN100454549C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107564892A (zh) * | 2017-08-23 | 2018-01-09 | 睿力集成电路有限公司 | 电容器及其形成方法、半导体器件 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100560821B1 (ko) * | 2004-08-17 | 2006-03-13 | 삼성전자주식회사 | 반도체 소자의 캐패시터 형성 방법 |
KR100666387B1 (ko) * | 2005-05-20 | 2007-01-09 | 삼성전자주식회사 | 도전성 패턴의 제조 방법 및 반도체 소자의 제조 방법. |
KR100660880B1 (ko) * | 2005-10-12 | 2006-12-26 | 삼성전자주식회사 | 복수의 스토리지 노드 전극들을 구비하는 반도체 메모리소자의 제조 방법 |
KR100695433B1 (ko) * | 2006-02-21 | 2007-03-16 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 및 그 제조 방법 |
US20070195151A1 (en) * | 2006-02-23 | 2007-08-23 | Anderson Frank E | Hand-held ink jet pen |
US8084367B2 (en) * | 2006-05-24 | 2011-12-27 | Samsung Electronics Co., Ltd | Etching, cleaning and drying methods using supercritical fluid and chamber systems using these methods |
KR100849066B1 (ko) | 2007-02-06 | 2008-07-30 | 주식회사 하이닉스반도체 | 실린더형 엠아이엠 캐패시터 형성방법 |
JP2011108927A (ja) * | 2009-11-19 | 2011-06-02 | Elpida Memory Inc | 半導体装置の製造方法 |
US20130081301A1 (en) * | 2011-09-30 | 2013-04-04 | Applied Materials, Inc. | Stiction-free drying of high aspect ratio devices |
US9868902B2 (en) | 2014-07-17 | 2018-01-16 | Soulbrain Co., Ltd. | Composition for etching |
KR20200136133A (ko) | 2019-05-27 | 2020-12-07 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2590409B1 (fr) * | 1985-11-15 | 1987-12-11 | Commissariat Energie Atomique | Procede de fabrication d'un transistor en couches minces a grille auto-alignee par rapport au drain et a la source de celui-ci et transistor obtenu par le procede |
JP2689031B2 (ja) | 1991-04-01 | 1997-12-10 | 三菱電機株式会社 | 半導体記憶装置およびその製造方法 |
KR960043175A (ko) | 1995-05-15 | 1996-12-23 | 김주용 | 반도체소자의 전하저장전극 제조방법 |
KR19980031090A (ko) | 1996-10-31 | 1998-07-25 | 김영환 | 반도체 소자의 전하 저장전극 형성방법 |
US5843822A (en) * | 1997-02-05 | 1998-12-01 | Mosel Vitelic Inc. | Double-side corrugated cylindrical capacitor structure of high density DRAMs |
JPH10289981A (ja) | 1997-04-11 | 1998-10-27 | Sony Corp | 半導体記憶装置の製造方法 |
TW427013B (en) | 1997-05-06 | 2001-03-21 | United Microelectronics Corp | The structure of the capacitors of DRAM and the manufacturing method of the same |
KR19990075646A (ko) | 1998-03-23 | 1999-10-15 | 윤종용 | 전세정 공정을 수반하는 반도체 장치의 커패시터 형성방법 및이에 이용되는 챔버 장비 |
TW363272B (en) | 1998-04-20 | 1999-07-01 | United Microelectronics Corp | Manufacturing method of capacitors used for memory cells of DRAM |
JP3214449B2 (ja) | 1998-06-12 | 2001-10-02 | 日本電気株式会社 | 半導体記憶装置の製造方法 |
KR100272670B1 (ko) * | 1998-07-02 | 2000-12-01 | 윤종용 | 반도체 장치의 제조 방법 |
US6207524B1 (en) * | 1998-09-29 | 2001-03-27 | Siemens Aktiengesellschaft | Memory cell with a stacked capacitor |
JP4070919B2 (ja) | 1999-01-22 | 2008-04-02 | 富士通株式会社 | 半導体装置及びその製造方法 |
AU6954300A (en) | 1999-07-12 | 2001-01-30 | Asml Us, Inc. | Method and system for in situ cleaning of semiconductor manufacturing equipment using combination chemistries |
KR20010065795A (ko) | 1999-12-30 | 2001-07-11 | 박종섭 | 반도체메모리장치의 스토리지노드 전극 제조방법 |
KR100388682B1 (ko) | 2001-03-03 | 2003-06-25 | 삼성전자주식회사 | 반도체 메모리 장치의 스토리지 전극층 및 그 형성방법 |
KR20020091642A (ko) | 2001-05-31 | 2002-12-06 | 삼성전자 주식회사 | 향상된 캐패시턴스를 갖는 반도체 소자의 캐패시터 형성방법 |
KR100762869B1 (ko) | 2001-06-29 | 2007-10-08 | 주식회사 하이닉스반도체 | 캐패시터의 형성방법 |
US6548853B1 (en) | 2002-02-13 | 2003-04-15 | Samsung Electronics Co., Ltd. | Cylindrical capacitors having a stepped sidewall and methods for fabricating the same |
-
2003
- 2003-08-13 KR KR1020030056009A patent/KR100546363B1/ko active IP Right Grant
-
2004
- 2004-04-28 US US10/835,142 patent/US7018892B2/en not_active Expired - Lifetime
- 2004-08-12 CN CNB2004100574568A patent/CN100454549C/zh active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107564892A (zh) * | 2017-08-23 | 2018-01-09 | 睿力集成电路有限公司 | 电容器及其形成方法、半导体器件 |
CN107564892B (zh) * | 2017-08-23 | 2018-08-24 | 睿力集成电路有限公司 | 电容器及其形成方法、半导体器件 |
Also Published As
Publication number | Publication date |
---|---|
US7018892B2 (en) | 2006-03-28 |
KR100546363B1 (ko) | 2006-01-26 |
CN100454549C (zh) | 2009-01-21 |
US20050037562A1 (en) | 2005-02-17 |
KR20050018074A (ko) | 2005-02-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
CI01 | Publication of corrected invention patent application |
Correction item: Priority Correct: [31]10/835,142 False: [31]10/835,192 Number: 7 Volume: 21 |
|
CI02 | Correction of invention patent application |
Correction item: Priority Correct: [31]10/835.142 False: [31]10/835.192 Number: 7 Page: The title page Volume: 21 |
|
COR | Change of bibliographic data |
Free format text: CORRECT: PRIORITY; FROM: [31]10/835.192 TO: [31]10/835.142 |
|
ERR | Gazette correction |
Free format text: CORRECT: PRIORITY; FROM: [31]10/835,192 TO: [31]10/835,142 |
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C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |