CN1551341A - 半导体装置、电子器件、电子机器及半导体装置的制造方法 - Google Patents

半导体装置、电子器件、电子机器及半导体装置的制造方法 Download PDF

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CN1551341A
CN1551341A CNA200410038693XA CN200410038693A CN1551341A CN 1551341 A CN1551341 A CN 1551341A CN A200410038693X A CNA200410038693X A CN A200410038693XA CN 200410038693 A CN200410038693 A CN 200410038693A CN 1551341 A CN1551341 A CN 1551341A
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projected electrode
line segment
projected
semiconductor chip
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汤泽秀树
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明提供一种半导体装置、电子器件、电子机器及半导体装置的制造方法，该半导体装置的构成为交错排列的第2列凸起电极(4′)的底面的宽度(W2)小于第1列凸起电极(4)的底面的宽度(W1)，同时第2列凸起电极(4′)的底面的长度(L2)大于第1列凸起电极(4)的底面的长度(L1)。根据本发明能够进行布线部的细间距化，同时缓和半导体芯片的安装位置的精度。

Description

半导体装置、电子器件、电子机器及半导体装置的制造方法
技术领域
本发明涉及一种半导体装置、电子器件、电子机器及半导体装置的制造方法，特别适合用于倒装式(flip chip)安装。
背景技术
在以往的半导体装置中，例如，如特开2000-269611号公报所公开，有通过在形成于布线基板上的连接端子上接合凸起电极，在布线基板上安装半导体芯片的方法。
图4(a)是表示以往的连接端子及凸起电极的配置方法的俯视图，图4(b)是表示安装在布线基板上的半导体芯片的构成的剖面图。
在图4中，在布线基板41上，形成有与布线部42′及连接在布线部42′的连接端子42，在半导体芯片43上设置矩形状的凸起电极44。此时，连接端子42及凸起电极44，例如，如图4(a)所示，能够交错状排列。然后，通过在连接端子42上接合设在半导体芯片43上的凸起电极44，在布线基板41上面朝下(face down)安装半导体芯片43。之后，通过在半导体芯片43和布线基板41的之间注入封装树脂45，能够封装半导体芯片43的表面。
但是，随着电路图形的微细化，如果使布线部42′细间距化，就得使在与和布线部42′邻接的凸起电极44′间的间隔D3变窄。因此，存在半导体芯片43的安装位置的精度要求严格，布线部42′的细间距化受到制约的问题。
发明内容
为此，本发明的目的是，提供一种半导体装置、电子器件、电子机器及半导体装置的制造方法，能够使布线部细间距化，同时也能够缓和半导体芯片的安装位置的精度。
为解决上述问题，采用本发明的一实施方式的半导体装置，其特征在于，具有：半导体芯片；第1凸起电极列，从上述半导体芯片的表面突出设置，各自含有多个具有第1重心的第1凸起电极，设置在连结上述第1重心的第1线段上；第2凸起电极列，从上述半导体芯片的表面突出设置，各自含有多个具有第2重心的第2凸起电极，设置在连结上述第2重心的第2线段上；上述第1线段和上述第2线段间隔地位于上述第1线段和上述第2线段的短方向；上述第1凸起电极的宽度小于上述第2凸起电极的宽度；上述第1凸起电极的长度大于上述第2凸起电极的长度。
由此，能够增大第1列凸起电极的宽度，能够使第1列的凸起电极稳定地接合在连接端子上，同时能够减小第2列凸起电极的宽度，能够扩大与第2列凸起电极邻接的布线部的间隔。因此，能够使布线部细间距化，同时也能够缓和半导体芯片的安装位置的精度，抑制增加安装工序的负担，同时能够促进布线部的细间距化。
此外，采用本发明的一实施方式的半导体装置，其特征在于：对于上述第1凸起电极和上述第2凸起电极，上述基板侧的表面的面积实质上相等。
由此，即使具有宽度和长度不同的第1凸起电极和第2凸起电极，也能够均匀分散施加给第1凸起电极和第2凸起电极的负荷。因此，能够避免对凸起电极下的钝化膜等的损伤。此外，由于也能够使凸起电极的强度均匀化，所以，能够防止在安装半导体芯片时等剥离凸起电极。
此外，采用本发明的一实施方式的半导体装置，其特征在于：还具有布线基板，其搭载上述半导体芯片具有并布线图形，上述第1凸起电极和上述第2凸起电极与布线图形接合。
由此，即使在使布线基板的布线图形细间距化时，也能够缓和搭载半导体芯片时的位置精度，同时在布线基板上安装半导体芯片。
此外，采用本发明的一实施方式的半导体装置，其特征在于：在上述半导体芯片和上述布线基板的之间，设置树脂层。
由此，在使布线基板的布线部细间距化时，能够抑制凸起电极接合时的温度升高，同时也能够稳定地将半导体芯片安装在电路基板上。
此外，采用本发明的一实施方式的半导体装置，提供一种电子器件，其特征在于，具有：电子零件；第1凸起电极列，从上述电子零件的表面突出设置，各自含有多个具有第1重心的第1凸起电极，设置在连结上述第1重心的第1线段上；第2凸起电极列，从上述电子零件的表面突出设置，各自含有多个具有第2重心的第2凸起电极，设置在连结上述第2重心的第2线段上；上述第1线段和上述第2线段间隔地位于上述第1线段和上述第2线段的短方向上；上述第1凸起电极的宽度小于上述第2凸起电极的宽度；上述第1凸起电极的长度大于上述第2凸起电极的长度。
由此，能够稳定地将第1凸起电极接合在布线图形上，同时，能够扩大与第2凸起电极接合的布线间的间隔，能够使布线图形所含的布线细间距化，同时能够缓和搭载电子零件时的位置精度。
此外，采用本发明的一实施方式的电子机器，其特征在于，具有：半导体芯片；布线基板，含有与上述半导体芯片电连接的布线图形；电子零件，经由上述布线基板，与上述半导体芯片电连接；第1凸起电极列，设在上述半导体芯片和上述布线基板之间，各自含有多个具有第1重心的第1凸起电极，设置在连结上述第1重心的第1线段上；第2凸起电极列，设在上述半导体芯片和上述布线基板之间，各自含有多个具有第2重心的第2凸起电极，设置在连结上述第2重心的第2线段上；上述第1线段和上述第2线段间隔地位于上述第1线段和上述第2线段的短方向上；上述第1凸起电极的宽度小于上述第2凸起电极的宽度；上述第1凸起电极的长度大于上述第2凸起电极的长度。
由此，能够使布线细间距化，同时也能够缓和搭载电子零件时的位置精度，能够谋求电子机器的小型化·轻量化。
此外，采用本发明的一实施方式的半导体装置的制造方法，其特征在于，包括：设置工序，以上述第1凸起电极的宽度小于上述第2凸起电极的宽度，上述第1凸起电极的长度大于上述第2凸起电极的长度的方式，设置上述第1凸起电极列和上述第2凸起电极列，上述第1凸起电极列和上述第2凸起电极列从上述半导体芯片的表面突出设置在半导体芯片上，上述第1凸起电极列各自含有多个具有第1重心的第1凸起电极，设置在连结上述第1重心的第1线段上，上述第2凸起电极列各自含有多个具有第2重心的第2凸起电极列，设置在连结上述第2重心的第2线段上；连接工序，经由上述第1凸起电极列和上述第2凸起电极列，将上述半导体芯片搭接在含有布线图形的布线基板上，电连接上述第1凸起电极列及上述第2凸起电极列和上述布线图形。
由此，即使在使布线基板的布线细间距化时，由于也能够缓和半导体芯片的搭载位置的精度，所以能够抑制增加安装工序的负担，同时也能够在电路基板上安装半导体芯片。
附图说明
图1是表示第1实施方式的半导体装置的构成的图。
图2是表示图1的半导体装置的制造方法的剖面图。
图3是表示第2实施方式的液晶组件的构成的图。
图4是表示以往的半导体装置的构成的图。
图中：1、11：布线基板、2：连接端子、2′、12a、12b：布线部、3、13：半导体芯片、4、4′、14：凸起电极、5、15：各向异性导电片、21：印刷基板、22、36：连接端子、31、34：玻璃基板、32：透明电极、33：液晶层、35：密封材
具体实施方式
以下，参照附图，说明本发明的实施方式的半导体装置、电子器件及其制造方法。
图1(a)是表示第1实施方式的半导体装置的构成的剖面图，图1(b)是表示第1实施方式的连接端子及凸起电极的构成的俯视图。
在图1中，在布线基板1上，形成布线部2′及连接在布线部2′的连接端子2，在半导体芯片3上设置凸起电极4。另外，连接端子2及凸起电极4，例如，如图1(b)所示，能够交错状排列。此外，通过经由各向异性导电片5，在连接端子2上ACF(Anisotropic Conductive Film)接合凸起电极4，在布线基板1上安装半导体芯片3。也可以代替ACF，设置ACP(AnisotropicConductive Paste)、绝缘性粘合剂、绝缘性树脂等。
此时，交错排列第1凸起电极4和第2凸起电极4′。其构成可以为第2凸起电极4′的底面的宽度W2小于第1列凸起电极4的底面的宽度W1，同时，第2列的凸起电极4′的底面的长度L2大于第1列的凸起电极4′的底面的长度L1。此外，能够以在各凸起电极4、4′的排列方向不重复的方式，至少沿半导体芯片3的长边或短边任何一方排列第1列凸起电极4和第2列凸起电极4′。此处，所谓的交错排列，含有具有第1重心的第1凸起电极的第1凸起电极列，设在连结第1重心的第1线段上；含有具有第2重心的多个第2凸起电极的第2凸起电极列，设在连结第2重心的第2线段上。此时，第1线段和第2线段在各线段的短方向上间隔设置。
由此，能够增大第1列凸起电极4的宽度W1，能够使第1列的凸起电极4稳定地接合在连接端子2′上，同时能够减小第2列凸起电极的宽度4′，能够扩大第2列凸起电极4′和与第2列凸起电极4′邻接的布线部2′的间隔D1。因此，即使在减小布线部2′相互间的间隔D2时，也能够确保第2列凸起电极4′和与第2列凸起电极4′邻接的布线部2′的间隔D1，能够使布线部2′细间距化，同时也能够缓和半导体芯片3的安装位置的精度。
另外，对于第1列凸起电极4和第2列凸起电极4′，优选底面的面积实质上相等。由此，即使其构成为第2列凸起电极4′的底面的宽度W2小于第1列凸起电极4的底面的宽度W1，同时第2列凸起电极4′的底面的长度L2大于第1列凸起电极4的底面的长度L1，也能够使各向异性导电片5所含的导电性粒子的补充面积一致，能够促进布线部2′的细间距化，同时能够稳定进行ACF接合。
另外，作为凸起电极4，例如，可以采用Au凸起、用软焊料材被覆的Cu凸起或Ni凸起，或者采用软焊料球。此外，作为布线部2′及连接端子2，例如，能够采用铜箔图形；作为布线基板1，例如可以采用薄膜基板、玻璃基板等。此外，在上述实施方式中，说明了利用ACF接合，在布线基板1上安装半导体芯片3，但是，例如，也可以采用NCF(Nonconductive Film)接合等其他粘合剂接合，也可以采用软焊料接合或合金接合等金属接合。
此外，本发明中采用半导体芯片3进行了说明，但也不局限于本实施方式，也可以将半导体芯片3置换成电子元件。作为电子元件，可举例电容器、电阻等。
图2是表示图1的半导体装置的制造方法的剖面图。
在图2(a)中，通过对形成在布线基板1上的铜箔的图形进行刻蚀，可以在布线基板1上形成连接端子2及布线部2′。
然后，如图2(b)所示，在设置连接端子2的布线基板1上粘贴各向异性导电片5。之后，将凸起电极4配置在连接端子2上，进行半导体芯片3的定位。
然后，如图2(c)所示，在将凸起电极4配置在连接端子2上的状态下，通过从上面对半导体芯片3施加负荷，经由各向异性导电片5，将凸起电极4ACF接合在连接端子2上。
由此，即使在使电路基板的布线2′细间距化时，也能够缓和半导体芯片3的安装位置精度，能够抑制增加安装工序的负担，同时能够在电路基板上安装半导体芯片3。
图3(a)是图3(b)的沿A-A线切断的剖面图，图3(b)是表示本发明的第2实施方式的液晶组件的概略构成的俯视图。
在图3中，在液晶组件上设置液晶面板PN及驱动液晶面板PN的液晶驱动器DR。此时，在液晶驱动器DR上，设置形成驱动用电路等的半导体芯片13。此外，经由各向异性导电片15，将半导体芯片13安装在布线基板11上。
此外，在液晶面板PN上设置玻璃基板31、34，在玻璃基板31上形成ITO等透明电极32。在形成透明电极32的玻璃基板31和玻璃基板34的之间，设置液晶层33，用密封材35密封液晶层33。
此时，在布线基板11上，设置布线部12a、12b。另外，经由ACF等连接端子22，将布线部12a的外引线连接在印刷基板21，同时经由ACF等连接端子36，将布线部12b的外引线连接在透明电极32上。
另外，布线部12a、12b的内引线，经由各向异性导电片15，ACF接合在半导体芯片13的凸起电极14上。此时，布线部12a、12b的内引线及凸起电极14，例如，如图1(b)所示，能够排列成交错状。此外，能够以比交错排列在半导体芯片13上的第1列凸起电极14减小宽度、延长长度，在与第1列凸起电极14的排列方向不重复的方式，在半导体芯片13上排列第2列凸起电极14。此外，能够使第1列及第2列的凸起电极14的底面的面积实质上相等。
由此，能够将交错排列的第1列凸起电极14稳定接合在布线部12a、12b的内引线上，同时，能够扩大与第2列凸起电极14邻接的布线部12a、12b的间隔，能够使布线部12a、12b细间距化，同时，也能够缓和半导体芯片13的安装位置的精度。此外，即使在与交错排列的第1列凸起电极14相比，减小第2列凸起电极14的宽度、延长长度时，也能够使各向异性导电片15所含的导电性粒子的补充面积一致，能够促进布线部12a、12b的细间距化，同时也能够稳定进行ACF接合。

Claims (7)

1.一种半导体装置，其特征在于，具有：
半导体芯片；
第1凸起电极列，从上述半导体芯片的表面突出设置，各自含有多个具有第1重心的第1凸起电极，设置在连结上述第1重心的第1线段上；
第2凸起电极列，从上述半导体芯片的表面突出设置，各自含有多个具有第2重心的第2凸起电极，设置在连结上述第2重心的第2线段上；
上述第1线段和上述第2线段间隔地位于上述第1线段和上述第2线段的短方向上；
上述第1凸起电极的宽度小于上述第2凸起电极的宽度；
上述第1凸起电极的长度大于上述第2凸起电极的长度。
2.如权利要求1所述的半导体装置，其特征在于，对于上述第1凸起电极和上述第2凸起电极，上述基板侧的表面的面积实质上相等。
3.如权利要求1或2所述的半导体装置，其特征在于，还具有布线基板，其搭载有上述半导体芯片并具有布线图形，上述第1凸起电极和上述第2凸起电极被接合在布线图形上。
4.如权利要求3所述的半导体装置，其特征在于，在上述半导体芯片和上述布线基板之间，设置树脂层。
5.一种电子器件，其特征在于，具有：
电子零件；
第1凸起电极列，从上述电子零件的表面突出设置，各自含有多个具有第1重心的第1凸起电极，设置在连结上述第1重心的第1线段上；
第2凸起电极列，从上述电子零件的表面突出设置，各自含有多个具有第2重心的第2凸起电极，设置在连结上述第2重心的第2线段上；
上述第1线段和上述第2线段间隔地位于上述第1线段和上述第2线段的短方向上；
上述第1凸起电极的宽度小于上述第2凸起电极的宽度；
上述第1凸起电极的长度大于上述第2凸起电极的长度。
6.一种电子机器，其特征在于，具有：
半导体芯片；
布线基板，含有与上述半导体芯片电连接的布线图形；
电子零件，经由上述布线基板，与上述半导体芯片电连接；
第1凸起电极列，设在上述半导体芯片和上述布线基板之间，各自含有多个具有第1重心的第1凸起电极，设置在连结上述第1重心的第1线段上；
第2凸起电极列，设在上述半导体芯片和上述布线基板之间，各自含有多个具有第2重心的第2凸起电极，设置在连结上述第2重心的第2线段上；
上述第1线段和上述第2线段间隔地位于上述第1线段和上述第2线段的短方向上；
上述第1凸起电极的宽度小于上述第2凸起电极的宽度；
上述第1凸起电极的长度大于上述第2凸起电极的长度。
7.一种半导体装置的制造方法，其特征在于，包括：
设置工序，以上述第1凸起电极的宽度小于上述第2凸起电极的宽度，上述第1凸起电极的长度大于上述第2凸起电极的长度的方式，设置上述第1凸起电极列和上述第2凸起电极列，上述第1凸起电极列和上述第2凸起电极列从上述半导体芯片的表面突出地设置在半导体芯片上，上述第1凸起电极列各自含有多个具有第1重心的第1凸起电极，设置在连结上述第1重心的第1线段上，上述第2凸起电极列各自含有多个具有第2重心的第2凸起电极，设置在连结上述第2重心的第2线段上；
连接工序，经由上述第1凸起电极列和上述第2凸起电极列，将上述半导体芯片搭接在含有布线图形的布线基板上，对上述第1凸起电极列、上述第2凸起电极列以及上述布线图形进行电连接。
CNA200410038693XA 2003-05-19 2004-05-12 半导体装置、电子器件、电子机器及半导体装置的制造方法 Pending CN1551341A (zh)

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JP5395407B2 (ja) * 2008-11-12 2014-01-22 ルネサスエレクトロニクス株式会社 表示装置駆動用半導体集積回路装置および表示装置駆動用半導体集積回路装置の製造方法
JP6006528B2 (ja) * 2012-05-16 2016-10-12 シャープ株式会社 半導体装置
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JPH07235564A (ja) * 1993-12-27 1995-09-05 Toshiba Corp 半導体装置
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JP3986199B2 (ja) * 1999-03-16 2007-10-03 カシオ計算機株式会社 フレキシブル配線基板
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