CN1503374A - 具有独立制作的垂直掺杂分布的栅极结构 - Google Patents

具有独立制作的垂直掺杂分布的栅极结构 Download PDF

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CN1503374A
CN1503374A CNA2003101164316A CN200310116431A CN1503374A CN 1503374 A CN1503374 A CN 1503374A CN A2003101164316 A CNA2003101164316 A CN A2003101164316A CN 200310116431 A CN200310116431 A CN 200310116431A CN 1503374 A CN1503374 A CN 1503374A
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polysilicon region
crystal silicon
upper polysilicon
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奥默・H・多库马西
奥默·H·多库马西
・格鲁申科夫
奥利格·格鲁申科夫
A・曼德尔曼
杰克·A·曼德尔曼
拉登斯
卡尔·拉登斯
・B・多丽丝
布鲁斯·B·多丽丝
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GlobalFoundries Inc
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Abstract

本发明公开了一种用于半导体晶体管的栅极结构。在一示例性实施例中，栅极结构包括以第一掺杂剂浓度掺杂的下部多晶硅区、以及以第二浓度掺杂的上部多晶硅区，该第二浓度不同于第一浓度。导电阻挡层设置在下部和上部多晶硅区之间，其中，导电阻挡层防止了下部和上部多晶硅区之间的杂质扩散。

Description

具有独立制作的垂直掺杂分布的栅极结构
技术领域
本发明总体上涉及半导体器件加工，更具体地，涉及具有独立制作的垂直掺杂分布(vertical doping profile)的半导体晶体管栅极结构(semiconductor transistor gate structure)。
背景技术
多晶硅(polysilicon)已经成为了MOSFET(金属氧化物半导体场效应晶体管)结构中栅极电极(gate electrode)的优选材料。具体地，多晶硅比金属栅极电极优异之处在于其在达到共晶(eutectic)温度前能抵御更高的后续加工温度。此外，多晶硅易于利用低压化学气相沉积(LPCVD)沉积在块体硅(bulk silicon)或二氧化硅(SiO2)上。
现有技术的MOSFET晶体管通过在栅极氧化物(gate oxide)和衬底上沉积栅极叠层材料(gate stack material)来制成。光刻(lithography)和蚀刻(etch)工艺用于定义多晶硅栅极结构，然后栅极结构和硅衬底两者得以热氧化。接着，注入源极/漏极(S/D)延伸区(extension)和环形区(halo)。这样的注入通常利用间隔壁(spacers)来进行，以在栅极和注入的结(junction)之间形成特定的距离。在某些情况中，注入NFET器件的S/D延伸区将无需间隔壁，但PFET器件的S/D延伸区的注入在间隔壁存在的情况下进行。在注入S/D延伸区之前通常形成厚间隔壁。之后，利用已有的厚间隔壁来进行深S/D的注入。然后进行高温退火(anneal)以将结活化。
由于在单一集成电路上集成更多有源器件(active devices)的趋势需要制造越来越小的MOSFET结构，所以MOSFET栅极的电阻成为了器件速度的限制因素。于是，有利的是采用具有可能的最小片电阻率(sheet resistivity)的材料来与多晶硅栅极结构相接触。为此，公知的是，耐火金属硅化物可以利用传统溅射、沉积和退火工艺而容易地在多晶硅MOSFET栅极结构上形成。耐火金属硅化物在退火后具有较低的片电阻率，并且还与通常使用的互连金属形成低电阻欧姆接触。因此，一旦结通过高温退火活化，则S/D区域和栅极顶部均被硅化。
为了既充分提高多晶硅活化，又使多晶硅的耗尽效应(depletion effect)减到最小，栅极以较高的掺杂剂浓度掺杂。不幸地，当栅极被重度掺杂时，高的掺杂剂浓度还会对栅极上的硅化作用产生不利影响，尤其是栅极线宽降低到0.1μm阈值以下时。由于适当的硅化物的形成是获得低电阻栅极(因而降低信号传播延迟)所必须的，所以还需要具有一种栅极结构，其中，栅极底部被重度掺杂以使多晶硅的耗尽效应最小化，而同时栅极顶部得以更轻度的掺杂以形成适当的硅化物。然而，采用当前的器件加工方法，即使对栅极顶部进行单独的、轻度掺杂的注入，后续退火工艺也会导致栅极中掺杂剂的再分布，从而导致较一致的垂直掺杂剂浓度。
发明内容
前述讨论的现有技术的缺点和不足通过半导体晶体管的一种栅极结构来克服或减小。在一示例性实施例中，该栅极结构包括以第一掺杂剂浓度掺杂的下部多晶硅区(lower polysilicon region)和以第二浓度掺杂的上部多晶硅区(upper polysilicon region)，第二浓度不同于第一浓度。导电阻挡层(conductive barrier layer)设置在下部和上部多晶硅区之间，其中，导电阻挡层防止了下部和上部多晶硅区之间的杂质扩散。
另一方面，MOS晶体管器件包括源极扩散区(source diffusion region)和漏极扩散区(drain diffusion region)。栅极叠层结构设置在栅极介电层(gatedielectric)上，栅极叠层结构还包括以第一掺杂剂浓度掺杂的下部多晶硅区、设置在下部多晶硅区上的导电阻挡层、以及设置在导电阻挡层上的上部多晶硅区。该上部多晶硅区以与第一浓度不同的第二浓度掺杂，且其中该导电阻挡层防止了下部和上部多晶硅区之间的杂质扩散。
再一方面，形成半导体晶体管的栅极结构的方法包括在栅极介电层上形成下部多晶硅区。该下部多晶硅区中注入第一掺杂剂浓度的掺杂剂。然后，在下部多晶硅区上形成导电阻挡层，且在该导电阻挡层上形成上部多晶硅区。该上部多晶硅区以第二掺杂剂浓度进行注入，所述第二浓度小于所述第一浓度。
附图说明
参见示例性附图，其中在该多个图中相同的元件标以相同的标记，其中：
图1-12示出了根据本发明一实施例的可用于形成MOS晶体管器件的栅极结构的示例性加工步骤的顺序，该栅极结构具有独立制作的垂直掺杂分布。
具体实施方式
此处公开的是一种用于MOS晶体管器件的栅极结构，其具有改善的栅极活化特性(gate activation characteristics)，且没有栅极线电阻的下降，其中防止了所不需要的杂质不利地影响高性能MOS晶体管的栅极特性。简而言之，该栅极结构包括通过导电扩散阻挡层彼此隔开的下部多晶硅区和上部多晶硅区。下部多晶硅区掺以第一浓度，该浓度非常地不同于(例如高于)掺杂上部多晶硅区所用的第二浓度。
于是，该扩散阻挡层允许独立调节栅极的下部和上部多晶硅区之间的掺杂分布(doping profile)，且还防止了退火过程中上部和下部区域之间杂质的扩散。从而，由高掺杂剂浓度导致的硅化问题在上部区域得以减轻，且不会危及栅极的通过下部区域的高掺杂剂浓度的活化。因此，延伸区、源极/漏极、和/或环形区(halo)注入可得以优化，而没有任何相应的有害的多晶硅耗尽和掺杂剂渗透问题。
现在参见附图，其示出可用于形成MOS晶体管的垂直制作的栅极结构的示例性工艺步骤的顺序。图1中，多晶硅(poly-Si)块体(block)102首先形成在栅极介电层104上(例如诸如栅极氧化层)，该栅极介电层又形成在衬底106上。衬底106可以是本领域技术人员所知的任何合适的半导体衬底，诸如硅衬底或多层绝缘体上硅(silicon-on-insulator)(SOI)衬底，栅极介电层104形成在其上。栅极介电层104可以例如通过氧化衬底106或通过在衬底106上沉积氧化物层来形成。然后，第一层多晶硅得以沉积、构图和蚀刻以形成多晶硅块体102，该块体将成为以上所概括描述的新栅极叠层结构的一部分。
一旦形成了多晶硅块体102，则牺牲层(sacrificial layer)(例如氧化物层)108沉积在栅极介电层104和多晶硅块体102上，然后被平坦化而下降至多晶硅块体的顶部，如图2所示。然后，在图3中，通过选择性蚀刻使多晶硅块体102凹陷，以形成栅极结构的第一层，以下称为下部多晶硅区110。此时，进行下部多晶硅区110的第一离子注入工艺，如图4所示，以提供足以用于栅极活化和防止耗尽效应的高掺杂剂浓度。如果下部多晶硅区110的所需厚度较薄，则注入的尾部(tail of the implant)会延伸到沟道区(channel)中。在此情形下，第一离子注入可以在使多晶硅块体102下陷之前完成。
适当的掺杂剂包括但不限于硼(B)、磷(P)、砷(As)和BF2。根据具体的掺杂剂或掺杂剂的组合，其浓度将会不同。然而，下部多晶硅区的示例性掺杂剂浓度为约1×1021原子/立方厘米(atoms/cm3)。
图5示出导电阻挡层112在氧化物层108和下部多晶硅区110上的形成。如下文讨论的那样，导电阻挡层112将用于防止上部和下部多晶硅区之间掺杂剂的扩散(多晶硅掺杂剂以及环形区/延伸区注入掺杂剂)。诸如氮化钨(WN)的金属因其电导性能和其作为阻挡层的功能性而为阻挡层112的优选材料，且可以通过化学气相沉积(CVD)沉积在氧化物层108和下部多晶硅区110的上面。其它适用于阻挡层的材料包括氮化钽(TaN)、氮化钛(TiN)、硅氮化钨(WSiN)、硅氮化钽(TaSiN)、氮化钛铝(AlTiN)、硅化钛(TiSi)、以及由超薄电介质(例如SiN或SiON)形成的量子导电半绝缘(quantumconductive semi-insulating)阻挡层、及其组合物。阻挡层112在下部多晶硅区110上的形成以基本上一致的厚度来进行，以留下其中将形成栅极的上部多晶硅区的凹陷(recess)114。
接着，如图6所示，在第一阻挡层112上沉积第二层多晶硅116，然后对其平坦化向下至氧化物层108，如图7所示，以形成上部多晶硅区118。第二层多晶硅116可以是与用于形成图1和2的多晶硅块体102的第一多晶硅层具有相同的导电类型。作为选择地，第二层116可以是第一多晶硅层的相反导电类型。图8中，示出了第二离子注入工艺，其中，其掺杂剂浓度优选小于第一注入工艺的掺杂剂浓度，以不危及对后续硅化物形成的完整性。再者，具体的注入浓度取决于所用的具体掺杂剂，但是第二层116的示例性浓度为约3×1020原子/cm3左右。
现在参见图9，氧化物层108通过蚀刻去除，以用于形成扩散区(即源极和漏极区)，并用于作为MOS器件的特征的延伸区和环形区注入。具体地，图10示出了延伸注入区120、以及环形注入区122的成角度注入。然后，如图11所示，在注入源极/漏极扩散区126之前，以传统方式形成源极/漏极间隔壁124。然后，该器件在高温(例如自约700℃至约1300℃，优选地自约900℃至约1100℃)下退火，以活化扩散区126。
由于导电阻挡层112的存在，在退火过程中，在高剂量下部多晶硅区108和低剂量上部多晶硅区118之间没有明显的掺杂剂浓度变化。也就是说，没有阻挡层112的存在，退火过程将导致下部和上部多晶硅区中掺杂的均等化。此外，在退火过程中，源极/漏极或延伸区/环形区形成过程中注入的任何氟或碳原子将保留在上部多晶硅区118中。因此，获得了栅极顶部和栅极底部之间掺杂剂和杂质的完全分隔。
最后，图12示出了硅化步骤之后形成栅极结构(总体上用128来表示)和MOS晶体管130的完成，在该硅化步骤中，硅化物层132形成在源极/漏极扩散区120上、以及在栅极结构形成的上部多晶硅区118上。适用于硅化物层132的材料包括但不必限于：硅化钴(CoSi)、硅化钛(TiSi)和硅化镍(NiSi)。作为上部多晶硅区118中较轻度掺杂剂浓度的结果，避免了硅化的困难。
如将进一步理解的那样，上述栅极结构还可用于Si/SiGeC(上部/下部)多晶硅叠层，其中，由于SiGeC多晶中掺杂剂的溶解度较高，多晶硅耗尽效应进一步减小。因此，如果SiGeC用于上部或下部多晶区，则优选地在较高浓度下掺杂，以利用其溶解度的增加，同时上部多晶区中的硅应当更轻度地掺杂，以防止硅化问题。
所公开的栅极结构的另一好处源自以下事实：也注入到栅极中的延伸区、源极/漏极、和/或环形区注入会导致MOS器件的某些问题。例如在PFET器件中，延伸区和源极/漏极注入会包含BF2，因为随之会获得更浅的结，这与相同热负担(thermal budget)的硼相反。另一方面，栅极中氟的出现还增强了掺杂剂自栅极起通过栅极电介质向下面沟道区中的扩散。沟道区中过多的掺杂剂对高性能MOS器件是有害的，尤其是当前半导体产业中正在开发的具有超薄氧化物(例如＜15)和高k电介质的MOS器件。
然而，采用以上栅极结构的导电阻挡层，栅极的底部将得以保护而免于氟穿过栅极电介质的渗透。这还适用于诸如碳的扩散阻挡物质的存在。在某些情形中，需要用扩散阻挡物质来注入源极/漏极和/或延伸区，以获得超浅结和超锐利环形区。但是，如果碳存在于下部区域栅极中，则阻碍了掺杂剂扩散到栅极底部，于是所得的多晶耗尽(poly depletion)将对MOS器件的性能有害。再者，导电阻挡层用于保护栅极的下部多晶硅区域而使之没有任何扩散阻挡物质。
虽然已经参照优选实施例描述了本发明，但是本领域技术人员将理解，在不脱离本发明的范围的情况下，对其各元件可以作各种改变和作各种等价替换。此外，在不脱离本发明的实质内容的情形下，可以作诸多改变，以使具体的情形或材料与发明的教导相适应。因此，本发明并不限于为实施本发明而设计的作为最好方式公开的具体实施例，相反，本发明包括所附权利要求的范围所涵盖的所有实施方案。

Claims (20)

1.一种用于半导体晶体管的栅极结构，包括：
以第一浓度掺杂的下部多晶硅区；
以第二浓度掺杂的上部多晶硅区，所述第二浓度不同于所述第一浓度；以及
导电阻挡层，其设置在所述下部和所述上部多晶硅区之间；
其中，所述导电阻挡层防止了所述下部和所述上部多晶硅区之间的杂质扩散。
2.如权利要求1的栅极结构，其中，所述第二浓度小于所述第一浓度。
3.如权利要求1的栅极结构，还包括设置在所述上部多晶硅区上的硅化物层。
4.如权利要求3的栅极结构，其中，所述硅化物层选自以下的组：硅化钴CoSi、硅化钛TiSi、硅化镍NiSi、以及包括前述物质中的至少一种的组合。
5.如权利要求1的栅极结构，其中，所述下部多晶硅区和所述上部多晶硅区中的至少一个包括硅锗碳SiGeC。
6.如权利要求1的栅极结构，其中，所述下部多晶硅区以约1×1021原子/立方厘米的浓度掺杂，所述上部多晶硅区以约3×1020原子/立方厘米的浓度掺杂。
7.如权利要求1的栅极结构，其中，所述导电阻挡层选自以下组：氮化钨WN、氮化钽TaN、氮化钛TiN、硅氮化钨WSiN、硅氮化钽TaSiN、氮化钛铝AlTiN、硅化钛TiSi、量子导电半绝缘阻挡层、以及包括前述物质中的至少一种的组合。
8.一种金属氧化物半导体(MOS)晶体管器件，包括：
源极扩散区和漏极扩散区；以及
设置在栅极介电层上的栅极叠层结构，所述栅极叠层结构还包括：
下部多晶硅区，其以第一掺杂剂浓度掺杂；
导电阻挡层，其设置在所述下部多晶硅区上；以及
上部多晶硅区，其设置在所述导电阻挡层上，所述上部多晶硅区以第二浓度掺杂，所述第二浓度与所述第一浓度不同，
其中，所述导电阻挡层防止了所述下部和所述上部多晶硅区之间杂质的扩散。
9.如权利要求8的晶体管器件，其中，所述第二浓度小于所述第一浓度。
10.如权利要求8的晶体管器件，还包括设置在所述上部多晶硅区上的硅化物层。
11.如权利要求10的晶体管器件，其中，所述硅化物层选自以下的组：硅化钴CoSi、硅化钛TiSi、硅化镍NiSi、以及包括前述物质中的至少一种的组合。
12.如权利要求8的晶体管器件，其中，所述下部多晶硅区和所述上部多晶硅区中的至少一个包括硅锗碳SiGeC。
13.如权利要求8的晶体管器件，其中，所述下部多晶硅区以约1×1021原子/立方厘米的浓度掺杂，所述上部多晶硅区以约3×1020原子/立方厘米的浓度掺杂。
14.如权利要求8的晶体管器件，其中，所述导电阻挡层选自以下组：氮化钨WN、氮化钽TaN、氮化钛TiN、硅氮化钨WSiN、硅氮化钽TaSiN、氮化钛铝AlTiN、硅化钛TiSi、量子导电半绝缘阻挡层、以及包括前述物质中的至少一种的组合。
15.一种形成半导体晶体管的栅极结构的方法，包括：
在栅极介电层上形成下部多晶硅区；
以第一掺杂剂浓度向所述下部多晶硅区中注入掺杂剂；
在所述下部多晶硅区上形成导电阻挡层；
在所述导电阻挡层上形成上部多晶硅区；以及
以第二掺杂剂浓度向所述上部多晶硅区中注入掺杂剂，所述第二浓度小于所述第一浓度。
16.如权利要求15的方法，还包括在所述上部多晶硅区上形成硅化物层。
17.如权利要求15的方法，其中，所述导电阻挡层选自以下组：氮化钨WN、氮化钽TaN、氮化钛TiN、硅氮化钨WSiN、硅氮化钽TaSiN、氮化钛铝AlTiN、硅化钛TiSi、量子导电半绝缘阻挡层、以及包括前述物质中的至少一种的组合。
18.如权利要求15的方法，其中，所述下部多晶硅区包括硅锗碳SiGeC。
19.如权利要求1 5的方法，其中，所述下部多晶硅区以约1×1021原子/立方厘米的浓度掺杂，所述上部多晶硅区以约3×1020原子/立方厘米的浓度掺杂。
20.如权利要求15的方法，其中，所述下部多晶硅区由以下步骤形成：
在所述栅极介电层上形成多晶硅块体；
在所述栅极介电层和所述多晶硅块体上形成牺牲层；
平坦化所述牺牲层向下至所述多晶硅块体的顶部；以及
使所述多晶硅块体下陷至比平坦化的牺牲层的顶部低。
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