CN1487598A - 具有高架源/漏结构的半导体器件及其制造方法 - Google Patents
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Abstract
一个栅极形成在半导体基片的部分表面上，一个栅绝缘膜被插入在它们之间。第一半导体膜形成在栅极的两侧上的半导体基片的表面上，该第一半导体膜与栅极相隔离。杂质扩散区形成在每个第一半导体膜中。外延区形成在栅极的两侧上的半导体基片的表面层中。该外延区被掺杂有与杂质扩散区相同导电型的杂质，并且连接到相应一个杂质扩散区。侧壁衬垫由绝缘材料所制成并且形成在栅极的侧壁上，该侧壁衬垫延伸出在栅极侧面上的第一半导体膜的边界并且覆盖第一半导体膜的部分表面。
Description
对相关申请的交叉引用
本申请基于并要求在2002年8月29日递交的日本专利申请2002-251268的优先权，并且其全部内容被包含于此以供参考。
技术领域
本发明涉及半导体器件及其制造方法，特别涉及一种具有高架源/漏结构的MOS半导体器件及其制造方法。
背景技术
半导体器件的高速操作和高集成度需要短栅极长度以及减小的寄生电容。为了抑制短沟道效应，需要使得源区和漏区变浅。为了抑制由于浅源和漏区所造成的薄膜电阻的增加，采用在源和漏区上形成耐火金属硅化物层的技术。
如果耐火金属硅化物层形成在浅源和漏区之上，则结泄漏电流增加。MOS半导体器件已经被提出具有高架源/漏结构，该结构在即使形成耐火金属硅化物层的情况下也不会增加结泄漏电流。
形成高架结构的方法是众所周知的。根据该方法，在把杂质注入到源和漏区之后，半导体的膜被有选择地外延生长在源和漏区之上。通过该方法，外延生长温度最好被设置在600℃或更低，以抑制在源和漏区中掺杂的杂质的横向扩散。由于生长温度不高，因此半导体膜的生长速度较慢。该方法不适用于大规模生产。
并且，在外延生长之前在氢气环境中进行热处理，以除去形成在源和漏区的表面上的自然氧化膜。热处理温度最好被设置在从700至900℃的范围内，以增强除去自然氧化膜的效果。但是另一方面，最好不把热处理温度设置在600℃或更高，以抑制在源和漏区中的杂质的横向扩散。如果热处理温度被设置在600℃或更低，则不能够获得所希望的除去自然氧化膜的充分效果。
如果在形成高架源/漏结构之后形成源和漏杂质扩散区，则可以防止在源和漏区中的杂质的横向扩散。但是，如果在形成高架源/漏结构之前已经形成轻微掺杂的漏(LDD)结构的延伸区，则在延伸区中的杂质在横向方向上扩散。因此不能够期望获得充分的短沟道效应抑制效果。
在日本专利公告JP-A-2000-150886的图12中以及其相关描述中，公开可以解决上述问题的用于具有高架源/漏结构的MOS晶体管的制造方法。根据该方法，首先，通过使用覆盖栅极的侧壁的侧壁衬垫以及在栅极的上表面上的绝缘膜作为掩膜，一个外延层被有选择的生长在源和漏区上。在此之后，杂质离子被注入到源和漏区，硅化钛层被形成在外延生长层之上。
在除去侧壁衬垫之后，杂质被注入以形成LDD结构的外延区。在950℃的温度下执行30分钟的热处理，以扩散该杂质，并且使得该外延区与源和漏区相连续。
通过在日本专利公告JP-2000-150886中所公开的方法在用于使该外延区与源和漏区相连续的热处理过程中，该外延区中的杂质还向沟道扩散。短沟道效应变大。另外，由于用于扩散在外延区中的杂质的热处理在形成硅化钛层之后执行，因此容易出现的硅化钛的聚集。如果出现硅化钛的聚集，则源和漏区的薄膜电阻变高。另外，通过该方法，硅化钛层不形成在栅极上。因此不能够期望获得低电阻的栅极。
发明内容
本发明的一个目的是提供一种能够减轻短沟道效应的具有高架源/漏结构的半导体器件，及其制造方法。
根据本发明的一个方面，在此提供一种半导体器件，其中包括：形成在半导体基片的部分表面上的栅极，一个栅绝缘膜被插入在它们之间；由半导体材料所制成并且形成在栅极的两侧上的半导体基片的表面上的第一半导体膜，该第一半导体膜与栅极隔开一定的距离；形成在每个第一半导体膜中的杂质扩散区；形成在栅极的两侧上的半导体基片的表面层中的外延区，该外延区被掺杂有与杂质扩散区相同导电型的杂质，并且连接到相应一个杂质扩散区；以及由绝缘材料所制成并且形成在栅极的侧壁上的侧壁衬垫，该侧壁衬垫延伸出在栅极侧面上的第一半导体膜的边界并且覆盖第一半导体膜的部分表面。
通过使用覆盖第一半导体膜的部分表面的侧壁衬垫作为掩膜，杂质被注入以形成源和漏的杂质扩散区。则可以抑制由于杂质的横向扩散所造成的短沟道效应的增加。
根据本发明的另一方面，在此提供一种制造半导体器件的方法，其中包括如下步骤：(a)在半导体基片的部分表面上形成栅绝缘膜以及置于该栅绝缘膜上的栅极；(b)在栅极的侧壁上形成第一侧壁衬垫；(c)在半导体基片的表面上生长由半导体材料所制成的第一半导体膜，不覆盖栅极和第一侧壁衬垫；(d)除去第一侧壁衬垫；(e)通过使用栅极作为掩膜，把第一导电型的杂质注入到半导体基片的表面层以及第一半导体膜的表面层；(f)在栅极的侧壁上形成第二侧壁衬垫，该第二侧壁衬垫至少到达在栅极侧上的第一半导体膜的边缘；(g)把第一导电型的杂质注入到不被第二侧壁衬垫所覆盖的第一半导体膜的区域中；以及(h)执行热处理用于激活在步骤(e)和(g)中注入的杂质。
在生长第一半导体膜之后，杂质被注入以形成源和漏区。在生长第一半导体膜的过程中所述的杂质没有受到热处理，从而可以抑制杂质的横向扩散。
如上文所述，在此执行有选择地外延生长以形成高架源/漏结构之后，形成源和漏的延伸区以及源和漏区。因此可以抑制在延伸区和源/漏区中的杂质的横向扩散。由于可以在高温下执行外延生长，因此可以增加生长速度。在形成源和漏区之后，形成金属硅化物膜。由于该金属硅化物膜没有受到对杂质的活化热处理，因此可以避免金属硅化物的聚集。
附图说明
图1A至1E为示出根据第一实施例的半导体器件制造方法的基片的截面视图。
图2为示出根据第一实施例的一种变型的半导体器件的截面视图。
具体实施方式
参见图1A至1E，将说明根据本发明一个实施例的半导体器件制造方法。
如图1A中所示，在由硅所制成的半导体基片1的表面层中，元件分离绝缘膜2通过硅的局部氧化(LOCOS)或浅沟槽隔离(STI)而形成。元件分离区2确定有源区。半导体基片1的表面被氧化，以在每个有源区的表面上形成氧化硅膜，该氧化硅膜具有大约2nm厚度并且被作为一个栅绝缘膜。
在半导体基片1上，通过化学汽相淀积(CVD)形成具有70至120nm的厚度的多晶硅膜，可以形成一个无定形硅膜。通过CVD方法，把具有20至40m的厚度的氮化硅膜形成在该多晶硅膜上。通过覆盖要被形成栅极的区域，从氮化硅膜到栅绝缘膜的三个层面被干法蚀刻，以保留由氮化硅膜所制成的掩膜5、多晶硅的栅极4以及氧化硅的栅绝缘膜3。
如图1B中所示，通过CVD方法把具有20至40nm的厚度的氮化硅膜淀积在基片的整个表面上，并且被各向异性干法蚀刻，以保留在栅极4的侧壁上的侧壁衬垫8。在淀积氮化硅膜之前，通过使用四乙基原硅酸盐(TEOS)作为原材料通过低压CVD形成大约5nm厚的氧化硅膜。
通过使用稀释的氢氟酸在把通过热氧化所形成的氮化硅膜腐蚀大约5nm的条件下对半导体基片执行表面处理。在氢气环境中，在大约1×104Pa(大约80乇)的压力、750℃的温度以及20slm的氢气流速的条件下执行120秒的热处理。通过这些处理，除去在半导体基片上形成的自然氧化物膜。
通过使用元件分离绝缘膜2、侧壁衬垫8和掩膜5作为掩膜，有选择地在半导体基片1的表面上外延生长硅，以形成具有20至70纳米的厚度的外延层10。例如，在20slm的氢气流速、100sccm的二氯硅烷(SiH2Cl2)流速、30sccm的氯化氢(HCl)流速、5.3×103Pa(40乇)和800℃的温度的条件下，通过CVD方法生长外延层10。在这些条件下进行300秒的生长，形成大约60nm厚的外延层。
该外延层可以通过超高真空CVD(UHV-CVD)在较低的生长气压下形成。可以使用(SiH4)、乙硅烷(Si2H6)和氯气(Cl2)作为源气体。
如图1C中所示，通过热磷酸除去图1B中所示的掩膜5和侧壁衬垫8。因此，半导体基片1的表面被暴露在栅极4的两侧。如果在淀积用于侧壁衬垫8的氮化硅膜之前形成具有大约5nm厚度的氧化硅膜，在使用热磷酸进行蚀刻处理的过程中该氧化硅膜作为半导体基片1的表面保护膜。该氧化硅膜被氢氟酸所除去。
如果要形成n沟道MOS晶体管，砷(As)离子被在4keV的加速能量和1.2×1015cm-2的剂量的条件下注入。如果要形成p沟道MOS晶体管，硼(B)离子被在3keV的加速能量和1×1015cm-2的剂量的条件下注入。通过该离子注入，源和漏区的延伸区15被形成在栅极4两侧的半导体基片的表面层中。该杂质还被注入到外延层10的表面层中。
如图1D中所示，侧壁衬垫18被再次形成在栅极4的侧壁上。该侧壁衬垫18覆盖栅极4两侧上的半导体基片的表面，并且延伸超过在栅极侧上的外延层10的边界，以覆盖外延层10的部分表面。例如，如果图1B中所示的侧壁衬垫8的厚度为30nm，则要被第二次形成的侧壁衬垫18被设置为50nm。侧壁衬垫18可以由氧化硅或氮化硅树脂层。它还可以由氮化硅膜和氮化硅膜的双层结构所制成。
如果要形成n沟道MOS晶体管，则通过使用侧壁衬垫18作为掩膜，磷(P)离子在6keV的加速能量和8×1015cm-2的剂量的条件下注入到外延层10。在此时，磷也被注入到栅极中。如果要形成p沟道MOS晶体管，则硼(B)离子在4keV的加速能量和4×1015cm-2的剂量的条件下注入。通过该离子注入，源和漏区19形成在外延层10中以及半导体基片1的表面层中。在离子注入之后，通过在950至1050℃的温度下执行激活热处理。退火时间大约为0至10秒。
下面将描述进行到图1E的处理。钛膜形成在基片的整个表面上并且执行热处理。因此，硅化钛的金属硅化物膜20形成在栅极4的上表面和外延层10的表面上。在热处理之后，除去未反应的钛膜。该金属硅化物膜20可以由的硅酸钴或硅酸镍所制成。
在本实施例中，在形成外延层10中，执行离子注入以形成延伸区15和源和漏区19。由于在外延生长过程中所注入的杂质没有受到热处理，因此可以抑制杂质的横向扩散。可以在700℃或更高的温度下执行外延生长。因此，可以增加生长速度。在外延生长之前，可以在700℃或更高的高温下执行在氢气环境中的热处理，用于除去自然氧化物。因此可以良好地除去自然晶体氧化物。
在本实施例中，在对所注入杂质执行激活热处理之后形成金属硅化物膜20。由于金属硅化物膜20不暴露在激活热处理的高温环境中，因此可以防止金属硅化物的聚集。
并且在本实施例中，被用作为注入离子的掩膜并且形成源和漏区19的侧壁衬垫18延伸超过在栅极侧上的外延层10的边界。因此，即使在源和漏区中的杂质在横向方向上扩散，它们也难以到达沟道区的附近。因此，可以增加源和漏区19的杂质浓度，而不产生穿孔。通过使得杂质浓度较高，可以表现出由于金属硅化物膜20所造成的结泄漏电流的增加。
图2为根据本实施例的一个变型的半导体器件的截面视图。在本实施例中，源和漏区19延伸到图1E中所示的半导体基片1的表面层。在图2中所示的变型中，在栅极侧上的外延层10的部分区域中，源和漏区19保留着外延层中并且不延伸到半导体基片1的表面层。其他结构类似于图1E中所示的实施例的半导体器件的结构。
在图2中所示的变型中，即使在源和漏区19中的杂质在横向方向上扩散，它们大部分进入被侧壁衬垫18所覆盖的外延层10的区域，并且不进入半导体基片1的表面层。可以增强防止穿孔的效果。
本发明已经结合优选实施例而描述。本发明不仅限于上述实施例。显然本领域的普通技术人员可以作出各种变型、改进、组合等等。
Claims (9)
1.一种半导体器件，其中包括：
形成在半导体基片的部分表面上的栅极，一个栅绝缘膜被插入在它们之间；
由半导体材料所制成并且形成在栅极的两侧上的半导体基片的表面上的第一半导体膜，每个第一半导体膜与栅极隔开一定的距离；
形成在每个第一半导体膜中的杂质扩散区；
形成在栅极的两侧上的半导体基片的表面层中的外延区，每个外延区被掺杂有与杂质扩散区相同导电型的杂质，并且连接到相应一个杂质扩散区；以及
由绝缘材料所制成并且形成在栅极的侧壁上的侧壁衬垫，该侧壁衬垫延伸出在栅极侧面上的第一半导体膜的边界并且覆盖第一半导体膜的部分表面。
2.根据权利要求1所述的半导体器件，其中进一步包括：
不被侧壁衬垫所覆盖的第一半导体膜的表面上的第一金属硅化物膜；以及
形成在栅极上的第二金属硅化物膜。
3.一种制造半导体器件的方法，其中包括如下步骤：
(a)在半导体基片的部分表面上形成栅绝缘膜以及置于该栅绝缘膜上的栅极；
(b)在栅极的侧壁上形成第一侧壁衬垫；
(c)在半导体基片的表面上生长由半导体材料所制成的第一半导体膜，不覆盖栅极和第一侧壁衬垫；
(d)除去第一侧壁衬垫；
(e)通过使用栅极作为掩膜，把第一导电型的杂质注入到半导体基片的表面层以及第一半导体膜的表面层；
(f)在栅极的侧壁上形成第二侧壁衬垫，该第二侧壁衬垫至少到达在栅极侧上的第一半导体膜的边缘；
(g)把第一导电型的杂质注入到不被第二侧壁衬垫所覆盖的第一半导体膜的区域中；以及
(h)执行热处理用于激活在步骤(e)和(g)中注入的杂质。
4.根据权利要求3所述的用于制造半导体器件的方法，其中进一步包括执行硅化反应以及在不被第二侧壁衬垫所覆盖的第一半导体膜的表面上和栅极的上表面上形成金属硅化物的步骤，该步骤在步骤(h)之后执行。
5.根据权利要求3所述的用于制造半导体器件的方法，其中在步骤(f)中，形成第二侧壁衬垫，第二侧壁衬垫延长在栅极侧上的第一半导体膜的边缘，并且覆盖第一半导体膜的部分表面。
6.根据权利要求4所述的用于制造半导体器件的方法，其中在步骤(f)中，形成第二侧壁衬垫，该第二侧壁衬垫延长在栅极侧上的第一半导体膜的边缘，并且覆盖第一半导体膜的部分表面。
7.根据权利要求3所述的用于制造半导体器件的方法，其中在步骤(g)中，在步骤(h)中的热处理之后的条件下注入杂质，该杂质保留在栅极侧上的第一半导体膜的至少部分区域中，而不扩散到半导体基片。
8.根据权利要求4所述的用于制造半导体器件的方法，其中在步骤(g)中，在步骤(h)中的热处理之后的条件下注入杂质，该杂质保留在栅极侧上的第一半导体膜的至少部分区域中，而不扩散到半导体基片。
9.根据权利要求5所述的用于制造半导体器件的方法，其中在步骤(g)中，在步骤(h)中的热处理之后的条件下注入杂质，该杂质保留在栅极侧上的第一半导体膜的至少部分区域中，而不扩散到半导体基片。
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| US7132338B2 (en) * | 2003-10-10 | 2006-11-07 | Applied Materials, Inc. | Methods to fabricate MOSFET devices using selective deposition process |
| KR100567752B1 (ko) * | 2003-12-31 | 2006-04-05 | 동부아남반도체 주식회사 | 반도체 소자 형성 방법 |
| US7402207B1 (en) | 2004-05-05 | 2008-07-22 | Advanced Micro Devices, Inc. | Method and apparatus for controlling the thickness of a selective epitaxial growth layer |
| US7125805B2 (en) * | 2004-05-05 | 2006-10-24 | Freescale Semiconductor, Inc. | Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing |
| US7129548B2 (en) * | 2004-08-11 | 2006-10-31 | International Business Machines Corporation | MOSFET structure with multiple self-aligned silicide contacts |
| US7135724B2 (en) * | 2004-09-29 | 2006-11-14 | International Business Machines Corporation | Structure and method for making strained channel field effect transistor using sacrificial spacer |
| US7241700B1 (en) | 2004-10-20 | 2007-07-10 | Advanced Micro Devices, Inc. | Methods for post offset spacer clean for improved selective epitaxy silicon growth |
| US7456062B1 (en) | 2004-10-20 | 2008-11-25 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device |
| US7687383B2 (en) * | 2005-02-04 | 2010-03-30 | Asm America, Inc. | Methods of depositing electrically active doped crystalline Si-containing films |
| US20060252191A1 (en) * | 2005-05-03 | 2006-11-09 | Advanced Micro Devices, Inc. | Methodology for deposition of doped SEG for raised source/drain regions |
| US20060281271A1 (en) * | 2005-06-13 | 2006-12-14 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device having an epitaxial layer and device thereof |
| US7553732B1 (en) * | 2005-06-13 | 2009-06-30 | Advanced Micro Devices, Inc. | Integration scheme for constrained SEG growth on poly during raised S/D processing |
| US20060286730A1 (en) * | 2005-06-15 | 2006-12-21 | Liu Alex Liu Yi-Cheng | Semiconductor structure and method for forming thereof |
| US7572705B1 (en) | 2005-09-21 | 2009-08-11 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing a semiconductor device |
| US8217423B2 (en) * | 2007-01-04 | 2012-07-10 | International Business Machines Corporation | Structure and method for mobility enhanced MOSFETs with unalloyed silicide |
| JP2010003812A (ja) * | 2008-06-19 | 2010-01-07 | Fujitsu Microelectronics Ltd | 半導体装置およびその製造方法 |
| US8486191B2 (en) * | 2009-04-07 | 2013-07-16 | Asm America, Inc. | Substrate reactor with adjustable injectors for mixing gases within reaction chamber |
| JP5446558B2 (ja) * | 2009-08-04 | 2014-03-19 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| US8367528B2 (en) | 2009-11-17 | 2013-02-05 | Asm America, Inc. | Cyclical epitaxial deposition and etch |
| KR101714003B1 (ko) | 2010-03-19 | 2017-03-09 | 삼성전자 주식회사 | 패시티드 반도체패턴을 갖는 반도체소자 형성방법 및 관련된 소자 |
| US9129823B2 (en) | 2013-03-15 | 2015-09-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon recess ETCH and epitaxial deposit for shallow trench isolation (STI) |
| JP6279291B2 (ja) | 2013-11-18 | 2018-02-14 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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| US6121100A (en) * | 1997-12-31 | 2000-09-19 | Intel Corporation | Method of fabricating a MOS transistor with a raised source/drain extension |
| JP3209731B2 (ja) | 1998-09-10 | 2001-09-17 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
| JP2002124665A (ja) * | 2000-10-12 | 2002-04-26 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
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| CN101194350B (zh) * | 2005-06-08 | 2010-12-01 | 格罗方德半导体公司 | 用可弃式间隔物提高的源极与漏极工艺 |
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