CN1428845A - 晶体管形成方法 - Google Patents
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Abstract
本发明提供一种能减少短沟道效应和逆短沟道效应晶体管形成方法。该形成方法步骤有：在半导体基片顺次形成使基片一部分露出焊垫氧化膜和氮化硅膜；把焊垫氧化膜和氮化硅膜作为掩膜蚀刻基片形成绝缘沟槽；顺次在沟槽内部在第一氧化膜和所述第一氧化膜侧面形成柱状绝缘间隔；形成使第一氧化膜和绝缘间隔沟槽内部添平的绝缘图形；通过蚀刻碳化硅膜、绝缘图形和绝缘间隔使焊垫氧化膜露出；除去焊垫氧化膜；除去绝缘间隔和第一氧化膜；顺次在剩余的绝缘图形两侧下部基片形成源极/漏极和LDD；在源极/漏极和LDD基片上形成第二氧化膜；顺次在LDD之间形成沟道阻挡层和在其下部形成穿透阻挡层，顺次在第二氧化膜沟槽内部形成栅极绝缘膜和栅极。
Description
技术领域
本发明涉及半导体装置的形成方法，特别涉及能使短沟道效应(shortchannel effect)和逆短沟道效应(reverse short channel effect)减少的晶体管形成方法。
背景技术
在硅片上形成的半导体装置包含用于使各个图形电路分离的元件分离区域，所述元件分离区域的形成是在所有步骤中的初始步骤，由于能左右活性区域的大小和后面工艺步骤的工艺余量而随着半导体装置的高集成化微细化，不仅对使各个不同元件的大小缩小而且使元件分离区的缩小的研究的活动正在积极地进行。
在半导体装置制造中通常广泛使用的硅的局部氧化元件分离法虽然具有工序简单的优点，但对256M DRAM量级以化的高集成化的半导体元件而言，随着元件分离区域的宽度减少而使由鸟喙状物(Bird’s Beak)引起的穿透(Purch-through)和元件分离膜的厚度减少，从而使分离区域的宽度减少已达到极限点。
伴随这种情况，作为适合于集成化半导体装置元件分离的技术有人推荐利用沟槽的元件分离方法例如浅沟槽隔离(Shallow Trench Isolation以下称为STI)。
然而随着半导体元件的集成度的增加栅极沟道长也照样减少，从而引发不仅使短沟道效应严重而还使逆短沟道效应严重的问题。
发明内容
鉴于所述情况，本发明的目的在于，提供不仅能防止短沟道效应也能防止逆短沟道效应的晶体管形成方法。
为了达到所述目的，本发明的晶体管形成方法包括：在半导体基片上顺次形成使所述基片的一部分露出的焊垫氧化膜和氮化硅膜的步骤；通过把所述焊垫氧化膜和氮化硅膜作为掩膜蚀刻所述基片形成沟槽的步骤；顺次在所述沟槽内部在第一氧化膜和所述第一氧化膜的侧面上形成柱状的绝缘间隔的步骤；形成使包含所述第一氧化膜和绝缘间隔的沟槽的内部添平的绝缘图形的步骤；通过蚀刻所述碳化硅膜、所述绝缘图形和所述绝缘间隔使所述焊垫氧化膜露出的步骤；除去所述焊垫氧化膜的步骤；除去所述绝缘间隔和第一氧化膜的步骤；顺次在所述剩余的绝缘图形的两侧的下部基片上形成源极/漏极和LDD的步骤；在包含所述源极/漏极和LDD的基片上形成第二氧化膜的步骤；顺次在所述LDD中间形成沟道阻挡层和在其下部形成穿透阻挡层的步骤，以及顺次在包含所述第二氧化膜的沟槽内部形成栅极绝缘膜和栅极的步骤。
附图说明
图1a至1f是表示本发明的晶体管形成的工序剖面图。
具体实施方式
从对下面参照的本发明的优选实施例的以下说明可以使所述的本发明的目的和其他的特征和优点等更加明确。
下面参照附图详细说明本发明的优选实施例。图1a至图1e是表示本发明的半导体元件的隔离过程的工序剖面图。
本发明的半导体元件的隔离方法如图1a所示，在半导体基片100上顺次蒸镀起缓冲(Buffer)作用的焊垫氧化膜104和抑制氧化的第一氮化硅膜106后，通过光刻工序使第一氮化硅膜106，氧化硅膜104和半导体基片100蚀刻到规定深度形成浅沟槽(ST)。这时所述半导体基片100通过阱(未图示)和浅沟槽隔离(STI，Shallow trench Isolation)方法形成区域氧膜102。
接着通过在所述结果物上进行热氧化工序在浅沟槽(ST)内部上形成第一氧化膜108。
然后如图1b所示那样，在包含所述第一氧化膜108的浅沟槽(ST)的结果物上进行LPCVD(Low Pressure Chemical Vapor Depositon)工序生成第二氧化膜后，通过对所述第二氧化膜进行各向异性干式蚀刻工序形成绝缘间隔110。这时所述绝缘间隔110具有包围形成有第一氧化膜的沟槽的内壁和剩余的电接点氧化膜和氮化硅膜的侧面的构造。
另外，作为所述第二氧化膜的材料相对第一氧化膜使用湿式蚀刻的选择比高的PSG。在利用PSG作为所述第二氧化膜时，在其后进行的湿式蚀刻工序中利用50∶1HF湿式溶液将第一氧化膜蚀刻10时，作为PSG的第二氧化膜被蚀刻200左右。
然后，在第一氮化硅膜106上蒸镀第二氮化硅膜后，对所述第二氮化硅膜进行层腐蚀(blanket-etch)或化学-机械抛光(Chemical MechanicalPolishing)工序，形成使包含绝缘间隔110的沟槽(ST)添平的绝缘图形112。
接着如图1c所示那样，在除去残留的第一氮化硅膜后，通过对所述绝缘图形112和绝缘间隔110进行化学-机械抛光工序或进行深腐蚀(etchback)工序，以使焊接区氧化膜在同一平面上地进行平坦化。
然后通过在所述结果物上进行离子注入工程形成源极/漏极120，122。这时所述源极/漏极120、122沟槽(ST)的底面向上侧方向形成300～1000的厚度。
以后如图1d所示那样，除去所述焊接区氧化膜。
接着利用H3PO4湿式溶液除去所述浅沟槽(ST)内部的绝缘间隔和第一氧化膜后，再通过进行离子注入工序在所述绝缘图形112的两侧下部形成LDD(Lightly Doped Drain)124。
然后在所述结果的基片上通过热氧化工序形成覆盖源极/漏极120、122和LDD 124的第三氧化膜126。
接着如图1e所示那样，利用热的H3PO4湿式溶液除去残留的绝缘图形后，再通过离子注入工序在所述LDD 124中间形成沟道阻挡层130，在其下部形成穿透阻挡层128。
接着如图1f所示那样，在形成有所述第三氧化膜126的沟槽(ST)的内部通过化学气相蒸镀(Chemical Vapor Deposition)工序顺次形成绝缘膜132和栅极134。
接着，在形成有所述栅极134的基片上进行化学气相蒸镀层间绝缘膜136后，通过光刻(Photolithography)工序蚀刻所述层间绝缘膜136，以形成使源极/漏极120、122和栅极134露出的各个连接孔138。
然后通过溅射(Sputter)工序在所述层间绝缘膜136上蒸镀钨等第一金属膜后，对所述第一金属膜进行化学-机械抛光或深腐蚀工序后，形成覆盖所述各个连接孔138的导电塞(Conductive Plug)140。这时使Ti/TiN膜(未示出)夹在所述各个连接孔138和导电塞140之间。所述Ti/TiN膜不仅使连接孔与导电塞间的粘着力强化还能充当后面的光工序中的减少光反射的反射防止膜。
接着通过溅射工序在包含所述导电塞140的层间绝缘膜136上蒸镀铝等第二金属膜后，通过所述光刻工序蚀刻所述第二金属膜形成与所述导电塞140连接的金属线142。
如上所述，按照本发明，在沟槽结构的栅极两侧形成源极/漏极并在其下部形成LDD，在所述LDD中间形成沟槽阻挡层，在其下部形成穿透阻挡层，借此不仅能防止短沟道效应还能防止逆短沟道效应。
另外，在不脱离本发明的权利要求的宗旨的范围内可以进行各种各样的变更。
Claims (5)
1.一种晶体管形成方法，其特征在于，包括：在半导体基片上顺次形成使所述基片的一部分露出的焊垫氧化膜和氮化硅膜的步骤；通过把所述焊垫氧化膜和氮化硅膜作为掩膜蚀刻所述基片形成沟槽的步骤；顺次在所述沟槽内部在第一氧化膜和所述第一氧化膜的侧面上形成柱状的绝缘间隔的步骤；形成使包含所述第一氧化膜和绝缘间隔的沟槽的内部添平的绝缘图形的步骤；通过蚀刻所述碳化硅膜、所述绝缘图形和所述绝缘间隔使所述焊垫氧化膜露出的步骤；除去所述焊垫氧化膜的步骤；除去所述绝缘间隔和第一氧化膜的步骤；顺次在所述剩余的绝缘图形的两侧的下部基片上形成源极/漏极和LDD的步骤；在包含所述源极/漏极和LDD的基片上形成第二氧化膜的步骤；顺次在所述LDD中间形成沟道阻挡层和在其下部形成穿透阻挡层的步骤；以及顺次在包含所述第二氧化膜的沟槽内部形成栅极绝缘膜和栅极的步骤。
2.如权利要求1所述的晶体管的形成方法，其特征在于，所述绝缘间隔的形成工序包括：在包含所述第一氧化膜的浅沟槽结果物上通过进行LPCVD工序使第二氧化膜生成的步骤；在所述第二氧化膜上进行各向异性干式蚀刻工序的步骤。
3.如权利要求2所述的晶体管的形成方法，其特征在于，所述第二氧化膜相对所述第一氧化膜使用湿式蚀刻选择比高的PSG。
4.如权利要求1所述的晶体管的形成方法，其特征在于，在形成所述栅极绝缘膜和栅极后，追加下述步骤：在所述结果物上形成层间绝缘膜的步骤，所述层间绝缘膜具有使所述源极/漏极和栅极露出的各自的接触孔；形成使所述接触孔添平的各个导电塞的步骤；以及在所述层间绝缘膜上形成与所述导电塞连接的金属配线的步骤。
5.如权利要求1所述的晶体管的形成方法，其特征在于，所述LDD从包含所述第一氧化膜的沟槽的底面向上侧方向形成为300-1000左右的厚度。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0085190A KR100433488B1 (ko) | 2001-12-26 | 2001-12-26 | 트랜지스터 형성 방법 |
| KR85190/2001 | 2001-12-26 | ||
| KR85190/01 | 2001-12-26 |
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| Publication Number | Publication Date |
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| CN1428845A true CN1428845A (zh) | 2003-07-09 |
| CN1266762C CN1266762C (zh) | 2006-07-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021584826A Expired - Fee Related CN1266762C (zh) | 2001-12-26 | 2002-12-25 | 晶体管形成方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6689664B2 (zh) |
| JP (1) | JP2003224263A (zh) |
| KR (1) | KR100433488B1 (zh) |
| CN (1) | CN1266762C (zh) |
| TW (1) | TWI226667B (zh) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444354C (zh) * | 2004-12-17 | 2008-12-17 | 尔必达存储器股份有限公司 | 制造半导体器件的方法 |
| CN101652833B (zh) * | 2007-04-05 | 2011-11-23 | 住友电气工业株式会社 | 半导体器件及其制造方法 |
| CN101030602B (zh) * | 2007-04-06 | 2012-03-21 | 上海集成电路研发中心有限公司 | 一种可减小短沟道效应的mos晶体管及其制作方法 |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100442780B1 (ko) * | 2001-12-24 | 2004-08-04 | 동부전자 주식회사 | 반도체 소자의 트랜지스터 제조 방법 |
| US6756619B2 (en) * | 2002-08-26 | 2004-06-29 | Micron Technology, Inc. | Semiconductor constructions |
| KR100507856B1 (ko) * | 2002-12-30 | 2005-08-17 | 주식회사 하이닉스반도체 | Ｍｏｓ트랜지스터 제조방법 |
| US20050263801A1 (en) * | 2004-05-27 | 2005-12-01 | Jae-Hyun Park | Phase-change memory device having a barrier layer and manufacturing method |
| US7482616B2 (en) * | 2004-05-27 | 2009-01-27 | Samsung Electronics Co., Ltd. | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same |
| KR100648205B1 (ko) * | 2005-06-13 | 2006-11-23 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| KR100631960B1 (ko) * | 2005-09-16 | 2006-10-04 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
| JP5280716B2 (ja) * | 2007-06-11 | 2013-09-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US8072035B2 (en) | 2007-06-11 | 2011-12-06 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| JP2009054946A (ja) * | 2007-08-29 | 2009-03-12 | Seiko Instruments Inc | 半導体装置とその製造方法 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3254868B2 (ja) * | 1993-12-24 | 2002-02-12 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
| JPH07321212A (ja) | 1994-05-24 | 1995-12-08 | Sony Corp | チャネルストップ拡散層の形成方法 |
| US5545579A (en) * | 1995-04-04 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains |
| KR100265227B1 (ko) | 1998-06-05 | 2000-09-15 | 김영환 | 씨모스 트랜지스터의 제조 방법 |
| JP2000156499A (ja) * | 1998-11-20 | 2000-06-06 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
| KR100280520B1 (ko) * | 1998-11-30 | 2001-02-01 | 김영환 | 모스 트랜지스터 제조방법 |
| US5981346A (en) * | 1999-03-17 | 1999-11-09 | National Semiconductor Corporation | Process for forming physical gate length dependent implanted regions using dual polysilicon spacers |
| KR100351447B1 (ko) * | 1999-12-29 | 2002-09-09 | 주식회사 하이닉스반도체 | 트렌치형 게이트전극 구조의 트랜지스터 및 그 제조방법 |
| US6309933B1 (en) * | 2000-06-05 | 2001-10-30 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating T-shaped recessed polysilicon gate transistors |
-
2001
- 2001-12-26 KR KR10-2001-0085190A patent/KR100433488B1/ko not_active IP Right Cessation
-
2002
- 2002-12-18 US US10/323,330 patent/US6689664B2/en not_active Expired - Lifetime
- 2002-12-19 TW TW091136745A patent/TWI226667B/zh not_active IP Right Cessation
- 2002-12-25 CN CNB021584826A patent/CN1266762C/zh not_active Expired - Fee Related
- 2002-12-26 JP JP2002378269A patent/JP2003224263A/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444354C (zh) * | 2004-12-17 | 2008-12-17 | 尔必达存储器股份有限公司 | 制造半导体器件的方法 |
| CN101652833B (zh) * | 2007-04-05 | 2011-11-23 | 住友电气工业株式会社 | 半导体器件及其制造方法 |
| CN101030602B (zh) * | 2007-04-06 | 2012-03-21 | 上海集成电路研发中心有限公司 | 一种可减小短沟道效应的mos晶体管及其制作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20030054780A (ko) | 2003-07-02 |
| KR100433488B1 (ko) | 2004-05-31 |
| TWI226667B (en) | 2005-01-11 |
| JP2003224263A (ja) | 2003-08-08 |
| TW200411779A (en) | 2004-07-01 |
| US6689664B2 (en) | 2004-02-10 |
| US20030119290A1 (en) | 2003-06-26 |
| CN1266762C (zh) | 2006-07-26 |
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