CN1312753C - 半导体元件的元件隔离膜的形成方法 - Google Patents

半导体元件的元件隔离膜的形成方法 Download PDF

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CN1312753C
CN1312753C CNB021542392A CN02154239A CN1312753C CN 1312753 C CN1312753 C CN 1312753C CN B021542392 A CNB021542392 A CN B021542392A CN 02154239 A CN02154239 A CN 02154239A CN 1312753 C CN1312753 C CN 1312753C
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朴哲秀
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    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

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Abstract

本发明提供一种半导体元件的元件隔离膜的形成方法。本发明在利用隔离掩膜图形依次腐蚀掩蔽绝缘膜和隔离氧化膜时通过腐蚀隔离氧化膜使之残存自硅衬底算起数百埃以内的厚度，使硅衬底不受因等离子体带来的损伤，使元件可靠性提高。为此本发明的半导体元件元件隔离膜的形成方法的特征在于：在依次在硅衬底上形成隔离氧化膜和掩蔽绝缘膜后，形成掩膜图形的步骤，利用所述掩膜图形，通过干式腐蚀依次腐蚀所述掩蔽绝缘膜和所述隔离氧化膜的规定部位步骤，在除去所述隔离掩膜图形后，将所述硅衬底上残存的规定部分的隔离氧化膜完全除去，从而形成沟槽的步骤，和在所获得的结构上生长硅外延膜，完成硅外延有源区的步骤。

Description

半导体元件的元件隔离膜的形成方法
技术领域
本发明涉及半导体元件的元件隔离膜的形成方法，特别是涉及利用硅外延生长(Epitaxial Silicon Growth)的元件隔离膜的形成方法。
背景技术
一般，一面增加半导体元件的集成度，一面正在进行在隔离工艺中利用沟槽(trench)腐蚀和化学机械剖光(Chemical Machanical Polishing：CMP)代替现有LOCOS(Locoal Oxidation of Silicon硅局部氧化)的隔离方法的新研究。
如下所述通过图1和图2说明以往的元件隔离膜的形成方法。
首先，如图1所示，在硅衬底1上形成衬垫氧化膜2和氮化膜3，按一定大小对所述氮化膜3和衬垫氧化膜2进行构图后，腐蚀露出的硅衬底1，形成沟槽。
接着，如图2所示，在硅衬底1上完成沟槽腐蚀后，在对沟槽内填充氧化膜4和进行CMP(Chemical Mechanical Polishing化学机械剖光)之后，完成洗净(Cleaning)工艺和牺牲氧化膜(SacrificialOxide)形成工艺。
但是，如上述那样进行的已往沟槽隔离膜的形成方法会发生各向异性的氧化膜损失，削减氧化膜的腐蚀边缘(A)。即，沟槽向下凹陷很多，这在进行字线腐蚀时使残留物残留在该部分，妨害元件稳定地执行动作，而且由于在该区域发生的边缘电场(Fringing Electric Field)，引起晶体管曲线顶点(Hump)出现，使亚阈值电流(Sub-threshold current)变大，并发生反向窄宽度效应(Inverse Narrow Width Effect)，使元件特性恶化。
图3至图5示出了用于解决上述问题的其它现有技术。
首先，参照图3，在硅衬底1上形成衬垫氧化膜12和氮化膜13，按一定大小对所述氮化膜13和衬垫氧化膜12进行构图后，腐蚀露出的硅衬底11而形成沟槽。但是，在以往的其它方法中，利用在硅衬底11的沟槽形成时产生的残留物在衬底11上腐蚀，从而变成钳口(B)。
接着，如图4所示，执行氧化工艺，形成沟槽角部(Corner)区域进一步变圆(round)的氧化膜14。
接着，如图5所示，在沟槽内填充氧化膜15，经CMP等工艺在沟槽边缘区域形成具有圆形轮廓的隔离绝缘膜。
但是，所述以往的其它方法受图形尺寸的影响。即，在图形尺寸大的部位容易产生这样的钳口，而在高集成的D随机存取存储器(DRAM)这样的构图狭窄的区域不产生这样的钳口，使所获得的氧化膜产生腐蚀边缘(A)，使元件的电气特性恶化。此外，由于在沟槽腐蚀时使产生的钳口因图形尺寸造成其程度不同，由此在以后使电气特性受到互不相同的影响。而且，在沟槽腐蚀后，为除去受损伤的硅膜而使角部变圆，如果在热氧化膜形成后进行除去该热氧化膜的牺牲氧化工艺，则存在角部变得更脆弱的问题。
发明内容
因此，本发明为解决上述问题而作出，本发明目的在于提供一种利用沟槽腐蚀的半导体元件的元件隔离膜的形成方法，所述沟槽腐蚀通过在填充沟槽的元件隔离绝缘膜的角部不发生损失，使在以后的工艺中不产生残留物，可获得稳定的元件电气特性。
此外，本发明的另一目的在于提供一种使元件可靠性提高的半导体元件的元件隔离膜的形成方法，该方法在利用隔离掩膜图形依次腐蚀掩蔽绝缘膜和隔离氧化膜时，通过腐蚀隔离氧化膜，使之残存从硅衬底算起数百埃以内的厚度，从而使硅衬底不被等离子体(Plasma)损伤(damage)。
为实现上述目的，本发明提供一种半导体元件的元件隔离膜的形成方法，其特征在于：依次在硅衬底上形成隔离氧化膜和掩蔽绝缘膜的步骤；通过腐蚀所述掩蔽绝缘膜和所述隔离氧化膜形成沟槽的步骤，其中所述隔离氧化膜残存在所述硅衬底上；去除所述残存的隔离氧化膜的步骤；以及在所述沟槽内生长硅外延膜，以形成硅外延有源区的步骤。
为实现上述目的，本发明半导体元件的元件隔离膜的形成方法的特征在于，包括：
在依次在硅衬底上形成隔离氧化膜和掩蔽绝缘膜后，形成掩膜图形的步骤，
利用所述掩膜图形，通过干式腐蚀依次腐蚀所述掩蔽绝缘膜和所述隔离氧化膜的规定部位的步骤，
在除去所述隔离掩膜图形后，将所述硅衬底上残存的规定部位的隔离氧化膜完全除去，从而形成沟槽的步骤，和
在所获得的结构上生长硅外延膜，完成硅外延有源区的步骤。
下面参照对本发明的优选实施例进行的以下说明，上述本发明的目的、其它特征和优点等会变得更明确。
附图说明
图1是用于说明现有技术的元件隔离膜形成方法的工艺剖面图。
图2同样是用于说明现有技术的元件隔离膜形成方法的工艺剖面图。
图3同样是用于说明现有技术的元件隔离膜形成方法的工艺剖面图。
图4是用于说明现有的其它技术的元件隔离膜形成方法的工艺剖面图。
图5同样是用于说明现有的其它技术的元件隔离膜形成方法的工艺剖面图。
图6是用于说明本发明的元件隔离膜形成方法的工艺剖面图。
图7同样是用于说明本发明的元件隔离膜形成方法的工艺剖面图。
图8同样是用于说明本发明的元件隔离膜形成方法的工艺剖面图。
图9是用于说明本发明的其它元件隔离膜形成方法的工艺剖面图。
图10同样是用于说明本发明其它元件隔离膜形成方法的工艺剖面图。
图11同样是用于说明本发明其它元件隔离膜形成方法的工艺剖面图。
具体实施方式
以下参照附图详细说明本发明实施例。
另外，在用于说明实施例的全部图面中具有相同功能的部件使用相同符号，省略重复说明。
图6至图8是用于说明本发明元件隔离膜形成方法的工艺剖面图。
首先参照图6，在硅衬底1的上部使隔离氧化膜2热生长成必要的厚度，在其上层叠掩蔽(Masking)绝缘膜3。之后，在所述掩蔽绝缘膜3上形成隔离掩膜图形4。
接着，利用所述隔离掩膜图形4通过干式腐蚀对所述掩蔽绝缘膜3和所述隔离氧化膜2进行腐蚀，使所述硅衬底1露出。
之后，除去所述隔离掩膜图形4(图7)。
接着，参照图8，通过硅外延生长(Epitaxial Silicon Growth)生成有源(active)硅区5，完成有源区和场(field)区。
图9至图11是用于说明本发明半导体元件的其它元件隔离膜的形成方法的工艺剖面图。
首先，参照图9，在硅衬底1的上部使隔离氧化膜2热生长成必要的厚度程度，在其上层叠掩蔽(Masking)绝缘膜3。之后，在所述掩蔽绝缘膜3上形成隔离掩膜图形4。
接着，尽管利用所述隔离掩膜图形4通过干式腐蚀对依次所述掩蔽绝缘膜3和所述隔离氧化膜2进行腐蚀，但腐蚀所述隔离氧化膜2使之残存从所述硅衬底1算起数百埃以内的厚度。此时，使所述隔离氧化膜2残存数百埃以内厚度的理由是为了所述硅衬底1不受等离子体(Plasma)的损伤(damage)，而这是为了以后进行在有源区形成的硅外延生长时减少外延层和所述硅衬底1之间发生的缺陷(defect)。
接着，参照图10，在除去所述隔离掩膜图形4后，在按照图6在所述硅衬底1上进行腐蚀后，将残存的氧化膜2完全除去。
接着，参照图11，通过硅外延生长(Epitaxial Silicon Growth)生成有源(active)区，完成有源区和场(field)区。
如上所述，如果按照本发明的半导体元件元件隔离膜的形成方法，在利用隔离掩膜图形4依次腐蚀掩蔽绝缘膜3和隔离氧化膜2时，通过腐蚀隔离氧化膜2使之残存从硅衬底1算起数百埃以内的厚度，则硅衬底1不受因等离子体(Plasma)带来的损伤(damage)，可使元件可靠性提高。
此外，在以后形成的硅外延生长时，可减少外延层和所述硅衬底1之间发生的缺陷(defect)。
以上通过实施例详细说明了本发明，但本发明不受实施例的限定，如果具有本发明所属技术领域中常识，则不脱离本发明思想和精神就可对本发明进行修改或变更。

Claims (2)

1.一种半导体元件的元件隔离膜的形成方法，其特征在于，
依次在硅衬底上形成隔离氧化膜和掩蔽绝缘膜的步骤，
通过腐蚀所述掩蔽绝缘膜和所述隔离氧化膜形成沟槽的步骤，其中所述隔离氧化膜残存在所述硅衬底上，
去除所述残存的隔离氧化膜的步骤，以及
在所述沟槽内生长硅外延膜，以形成硅外延有源区的步骤。
2.如权利要求1所述的半导体元件的元件隔离膜形成方法，其特征在于，在形成该沟槽的该步骤中，部分所述隔离氧化膜残存在该硅衬底上该沟槽内。
CNB021542392A 2001-12-20 2002-12-20 半导体元件的元件隔离膜的形成方法 Expired - Fee Related CN1312753C (zh)

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KR100620707B1 (ko) * 2004-12-31 2006-09-13 동부일렉트로닉스 주식회사 반도체 소자의 ｓｔｉ 형성 방법
CN100358155C (zh) * 2005-10-14 2007-12-26 西安电子科技大学 等离子体平板显示器寻址驱动芯片制备方法
KR100775963B1 (ko) 2006-07-12 2007-11-15 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR100814417B1 (ko) 2006-10-02 2008-03-18 삼성전자주식회사 단결정 실리콘 패턴 형성 방법 및 이를 이용한 불 휘발성 메모리 소자의 형성 방법
KR101416318B1 (ko) 2008-01-15 2014-07-09 삼성전자주식회사 소자 분리 공정을 포함하는 반도체 장치의 제조방법
JP2009272596A (ja) * 2008-04-09 2009-11-19 Sony Corp 固体撮像装置とその製造方法、及び電子機器
US8536674B2 (en) 2010-12-20 2013-09-17 General Electric Company Integrated circuit and method of fabricating same
CN102427051A (zh) * 2011-08-29 2012-04-25 上海华力微电子有限公司 一种浅沟槽隔离填充的方法
CN103811403B (zh) * 2012-11-13 2016-05-25 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构的形成方法
CN114242651A (zh) * 2022-02-24 2022-03-25 北京芯可鉴科技有限公司 浅槽隔离结构制作方法及浅槽隔离结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US6228691B1 (en) * 1999-06-30 2001-05-08 Intel Corp. Silicon-on-insulator devices and method for producing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100365741B1 (ko) * 1998-06-30 2003-02-19 주식회사 하이닉스반도체 반도체장치제조방법
JP2000100931A (ja) * 1998-09-25 2000-04-07 Seiko Epson Corp 半導体装置及びその製造方法
KR20000043906A (ko) * 1998-12-29 2000-07-15 김영환 반도체 소자의 제조 방법
KR20010003257A (ko) * 1999-06-22 2001-01-15 김영환 반도체소자의 제조방법
US6277723B1 (en) 1999-10-14 2001-08-21 Taiwan Semiconductor Manufacturing Company Plasma damage protection cell using floating N/P/N and P/N/P structure
US6303467B1 (en) 2000-07-28 2001-10-16 United Microelectronics Corp. Method for manufacturing trench isolation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US6228691B1 (en) * 1999-06-30 2001-05-08 Intel Corp. Silicon-on-insulator devices and method for producing the same

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TW200411810A (en) 2004-07-01
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KR20030051018A (ko) 2003-06-25
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