CN1309419A - 具有最小覆盖电容的金属氧化物半导体场效应晶体管 - Google Patents

具有最小覆盖电容的金属氧化物半导体场效应晶体管 Download PDF

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CN1309419A
CN1309419A CN01102992A CN01102992A CN1309419A CN 1309419 A CN1309419 A CN 1309419A CN 01102992 A CN01102992 A CN 01102992A CN 01102992 A CN01102992 A CN 01102992A CN 1309419 A CN1309419 A CN 1309419A
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CN1177357C (zh
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黛安娜·C·博伊德
霍塞因·I·哈纳费
梅克·伊昂格
韦斯利·C·纳茨尔
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Elpis technologies
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Abstract

提供了制造具有高介电常数(k大于7)栅绝缘体、低覆盖电容(0.35fF/μm或更低)、以及短于光刻确定的栅长度的沟道长度(亚光刻,例如0.1μm或更短)的MOSFET的方法。这些方法包括镶嵌工艺步骤和化学氧化物清除(COR)步骤。COR步骤在衬垫氧化物层上产生一个大的斜坡,当与高k栅绝缘体组合时,导致比用常规互补金属氧化物半导体(CMOS)技术制作的MOSFET器件更低的覆盖电容、短的沟道长度和更好的器件性能。

Description

具有最小覆盖电容的金属 氧化物半导体场效应晶体管
本发明涉及到半导体器件，确切地说是涉及到具有高介电常数(k大于7)栅绝缘体、低覆盖电容(0.35fF/μm或更低)、以及短于光刻确定的栅长度的沟道长度(亚光刻，例如0.1μm或更小)的金属氧化物半导体场效应晶体管(MOSFET)的制造方法。
随着MOSFET的沟道长度被缩小到亚0.1μm尺度和栅氧化物厚度被缩小到1.5nm以下，大于1A/cm2的隧道电流将使得不能够用SiO2作为栅介电层。因此，必需开发利用高k栅绝缘体的互补金属氧化物半导体(CMOS)技术，以便继续将CMOS缩小到亚0.1μm范围。
在采用高k栅绝缘体的常规栅CMOS技术中，通常在制作栅绝缘体之后，对源/漏掺杂剂执行激活退火。为了防止高k绝缘体性质的退化，将退火温度限制在低于800℃。这样低温度的退火导致源/漏结的局部激活以及多晶硅栅的耗尽。上述的二个特性由于常常导致器件性质退化而是不可取的。
而且，在常规栅CMOS技术中，源/漏延伸部分必需覆盖器件的栅区。这一覆盖引起器件中的电容。源/漏延伸部分与栅区的覆盖越大，覆盖电容就越大。同样，若源/漏延伸部分与栅的覆盖太小，则可能制造出不可靠的MOSFET器件。
与常规栅CMOS技术有关的另一个问题是利用光刻和腐蚀来制造栅。在制作CMOS器件的栅区的过程中使用光刻和腐蚀，提供了沟道长度与光刻工具同等数量级的MOSFET器件。亦即，光刻确定的栅长度使得无法制作亚光刻器件。
考虑到现有技术栅CMOS技术的缺点，对开发能够制造具有高k栅绝缘体、低覆盖电容、和亚光刻沟道长度MOSFET的新的和改进了的方法，就有了不断的需求。
本发明的一个目的是提供一种制造包含高k介电材料作为器件的栅绝缘体的高度可靠的MOSFET器件的方法。
本发明的进一步目的是提供一种制造包含高k介电栅绝缘体和低覆盖电容的高度可靠的MOSFET器件的方法。
本发明的另一个目的是提供一种制造具有高k栅绝缘体、低覆盖电容和短沟道长度的高度可靠的MOSFET器件的方法。
本发明的再一个目的是提供一种制造具有低覆盖电容和短沟道长度的高度可靠的MOSFET器件的方法，其中高k低温金属氧化物或高k高温金属氧化物被用作器件的栅绝缘体。
术语“高k”在本发明中被用来表示介电常数大于Si3N4亦即大于7.0的介电材料。术语“高k”表示介电常数为15或更大的介电材料则更好。
术语“低覆盖电容”在本发明中被用来表示0.35fF/μm或更低的电容。
术语“短沟道长度”在本发明中被用来表示位于栅区下面的长度为0.1μm或更短，亦即亚光刻的栅沟道。
术语“高温金属氧化物”表示在大约950-1050℃，最好是1000℃的温度下，承受10秒钟的退火时不退化的金属氧化物。这种金属氧化物的示例性例子包括但不局限于Al2O3和TiO2。
术语“低温金属氧化物”表示在950-1050℃，最好是1000℃下，退火10秒钟时被转换成金属或变得漏电的金属氧化物。这种金属氧化物的示例性例子包括但不局限于ZrO2、钛酸钡、钛酸锶、和钛酸锶钡。
利用包括用来形成栅电极的镶嵌工艺步骤以及用来产生衬垫氧化物层中的大斜坡的化学氧化物清除(COR)工艺步骤的方法，在本发明中达到了这些和其它的目的和优点。当这二个工艺步骤与高k介电材料组合使用时，能够制造具有低覆盖电容和短沟道长度的MOSFET器件。
在本发明的一个实施例中，其中高k高温金属氧化物被用作栅绝缘体，本发明的工艺步骤包含：
(a)提供具有制作在衬底表面上的叠层膜的半导体结构，所述叠层膜包含至少一个制作在所述衬底的所述表面上的衬垫氧化物层和一个制作在所述衬垫氧化物层上的氮化物层；
(b)在所述氮化物层中制作停止在所述衬垫氧化物层上的栅孔；
(c)在所述栅孔中的氮化物层上制作氧化物膜；
(d)对所述氧化物膜和部分所述衬垫氧化物层进行腐蚀，以便在所述栅孔中提供暴露部分所述衬底的窗口，其中的衬垫氧化物层被所述腐蚀削尖；
(e)在所述栅孔周围和所述暴露的衬底上制作高k高温金属氧化物层；
(f)用栅导体填充所述栅孔；
(g)清除暴露部分所述高k高温金属氧化物的所述氮化物层；以及
(h)完成所述MOSFET器件的制造。
步骤(h)包括在所述栅导体下面的所述衬底中形成激活的源/漏延伸部分；在所述高k高温金属氧化物的暴露的侧壁上制作隔板；在所述衬底中形成激活的源/漏区；以及在部分所述衬垫氧化物层中和在所述栅导体中形成硅化物区。
在本发明的另一个实施例中，其中高k低温金属氧化物被用作栅绝缘体，本发明的工艺步骤包含：
(ⅰ)提供具有制作在衬底表面上的虚拟叠层膜的半导体结构，所述虚拟叠层膜包含至少一个制作在所述衬底的所述表面上的衬垫氧化物层、一个制作在所述衬垫氧化物层上的多晶硅层、以及制作在所述多晶硅层上的SiO2层；
(ⅱ)清除所述虚拟叠层膜的选定部分，停止在所述衬垫氧化物层上，以便提供图形化的虚拟栅区；
(ⅲ)从所述图形化的虚拟栅区清除所述SiO2层；
(ⅳ)在所述虚拟栅区下面的所述衬底中形成激活的源/漏延伸部分；
(ⅴ)在所述虚拟栅区的侧壁上形成隔板；
(ⅵ)在所述衬底中形成激活的源/漏区；
(ⅶ)在部分所述衬垫氧化物层中和在所述虚拟栅区的所述多晶硅层中形成硅化物区；
(ⅷ)制作围绕所述虚拟栅区的绝缘层；
(ⅸ)整平所述绝缘层，停止在所述虚拟栅区中的所述多晶硅层；
(ⅹ)制作窗口，以便暴露部分所述衬底，借助于清除所述虚拟栅的所述多晶硅层以及借助于削尖所述虚拟栅区的部分所述衬垫氧化物层，而制作所述窗口；
(ⅹⅰ)在所述窗口中制作高k低温金属氧化物；以及
(ⅹⅱ)用栅导体填充所述窗口，所述栅导体在低温下制作。
在步骤(ⅹⅱ)之后，可以随之以可选的整平工艺。
本发明的另一情况涉及到利用上述某一种方法制造的MOSFET器件。本发明的MOSFET器件的特征是具有低的覆盖电容和短的沟道长度。具体地说，本发明的MOSFET器件包含至少一个具有制作在至少部分削尖的衬垫氧化物层上的高k栅绝缘体的栅区，其中所述栅区还包括长度为亚光刻，最好是0.1μm或更短的沟道。
图1A-G示出了通过用于本发明第一实施例中的各个工艺步骤，亦即在采用高k高温金属氧化物的情况下的本发明的MOSFET器件。
图2A-F示出了通过用于本发明第二实施例中的各个工艺步骤，亦即在采用高k低温金属氧化物的情况下的本发明的MOSFET器件。
现参照本发明的附图来更详细地描述提供具有高k、低覆盖电容和短沟道长度的MOSFET器件的制造方法的本发明。应该指出的是，在附图中相同的参考号被用来描述相同和/或相当的元件。
参照图1A-1G，示出了本发明第一实施例中使用的各个基本工艺步骤。具体地说，图1A-1G是利用本发明第一方法能够制作的一种可能的MOSFET器件的剖面图。如上所述，当高k高温金属氧化物被用作栅绝缘体时，使用第一方法。
图1A示出了由本发明的步骤(a)制作的初始结构。此初始结构包含衬底10和叠层膜12。此叠层膜包括诸如制作在衬底10表面上的SiO2之类的衬垫氧化物层14和诸如制作在衬垫氧化物层上的Si3N4之类的氮化物层16。虽然本发明的附图描述了包含二个材料层的叠层膜，但叠层膜也可以包含额外的材料层。在本发明附图中的实施例中，氮化物层16不同于用来确定隔离沟槽的氮化物层，因此，将用稍后的腐蚀步骤清除这一层，以便暴露结构的栅区，在清除氮化物层之后，衬垫氧化物层保留在部分衬底上。
用常规的热生长工艺，将衬垫氧化物层14制作在衬底10的表面上，或作为变通，可以用诸如但不局限于此的化学汽相淀积(CVD)、等离子体辅助CVD、溅射、蒸发之类的淀积工艺或其它相似的淀积工艺，来制作衬垫氧化物层。衬垫氧化物层的厚度可以变化，但应该比后续工艺步骤中将要制作的相应的栅绝缘体更厚。通常，衬垫氧化物层的厚度为大约8-20nm。
就氮化物层16而论，利用包括与以上在制作衬垫氧化物层过程中所指出的相同的本技术领域众所周知的常规淀积工艺，将此层制作在衬垫氧化物层14的表面上。氮化物层的厚度可以变化，但应该比其上制作的衬垫氧化物更厚。通常，在本发明中，叠层膜12的氮化物层16的厚度约为50-200nm。
本发明所用的衬底可以是其中存在硅之类的半导体材料的任何一种常规的半导体衬底。可以用在本发明中的一些衬底的例子包括但不局限于Si、Ge、SiGe、GaP、InAs、InP和所有其它的Ⅲ/Ⅴ族化合物半导体。衬底也可以由诸如Si/SiGe之类的层状半导体组成。依赖于要制造的所需器件，衬底可以是n型或p型。衬底可以包含用本技术众所周知的工艺技术制作在衬底上或制作在衬底中的各种各样的有源和/或隔离区。用于本发明的最佳衬底是Si晶片即芯片。
在衬底10上制作叠层膜12之前，在衬底中制作隔离沟槽。此隔离沟槽被制作成通过先前淀积的氮化物层(不同于氮化物层16)、衬垫氧化物层14和部分衬底10。用常规的光刻和腐蚀(反应离子刻蚀(RIE)、等离子体腐蚀、离子束腐蚀和其它相似的干法腐蚀工艺)来制作隔离沟槽。虽然在附图中未示出，但光刻步骤使用了常规的光刻胶以及可选地使用了抗反射涂层，在衬底中制作隔离沟槽之后，二者都被清除。
在隔离沟槽中制作例如SiO2的氧化物衬里，以便衬垫各个沟槽的侧壁和底部，然后用沟槽介电材料填充沟槽(在附图中，隔离区18意味着包括氧化物衬里以及沟槽介电材料)。在沟槽填充之后，可以随之以可选的致密化步骤和/或整平步骤。图1A示出了隔离沟槽填充、整平和叠层膜12制作之后形成的结构。应该指出的是，氧化物衬里构成具有衬垫氧化物顶部表面的一个连续的层；因此，隔离沟槽的整个底部被隔离于衬底10。
可以用包括与以上制作衬垫氧化物层14过程中指出的相同的常规淀积或热生长工艺，来制作氧化物衬里。依赖于其制作中所用的工艺技术，氧化物衬里的厚度可以变化，但氧化物衬里的典型厚度范围是大约5-20nm。
在用氧化物衬里衬垫隔离沟槽的底部之后，在先前制作的氮化物层的表面上和在隔离沟槽中，制作沟槽介电材料。用于本发明的填充工艺包含任何常规的淀积工艺，包括但不局限于CVD和等离子体辅助CVD。可以用于本发明这一步骤中的适当的沟槽介电材料包括任何常规的介电材料。能够用于本发明的一些适当的沟槽介电材料的例子，包括但不局限于原硅酸四乙酯(TEOS)、SiO2、可流动的氧化物、以及其它相似的介电材料。当TEOS被用作沟槽介电材料时，在整平之前可以使用可选的致密化步骤。
整平工艺包含本技术领域熟练人员所知的任何常规的整平技术，包括但不局限于化学机械抛光(CMP)和研磨。在制作隔离区之后，可以清除氮化物层，并制作新的氮化物层16，或作为变通，淀积额外的氮化物材料，以形成新的氮化物层16。
本发明的第一方法的下一步骤包括在氮化物层16中制作停止于衬垫氧化物14上的栅孔20，见图1B。具体地说，利用常规的光刻和腐蚀(反应离子刻蚀(RIE)、等离子体腐蚀、离子束腐蚀和其它相似的干法腐蚀工艺)来制作栅孔，提供图1B所示的结构。在确定栅孔过程中使用常规的光刻胶，并在其制造之后被清除。虽然附图描述了结构中仅仅一个栅孔的制作，但此处也考虑了多个栅孔。
在制作栅孔之后，可以利用常规的离子注入和激活退火方法，来执行可选的阈值调整注入步骤；本技术领域熟练人员对这二个工艺都是众所周知的。
在栅孔制作和可选的阈值调整注入制作之后，在栅孔20中的氮化物层上制作氧化膜22，提供图1C所示的结构。用诸如能够制作栅孔中的氮化物层上的氧化物层的CVD之类的淀积工艺，来制作氧化物层。此氧化物由诸如TEOS之类的常规材料组成。
接着，如图1D所示，在栅孔20底部的衬垫氧化物层14中制作窗口24，以便在栅孔中提供斜坡衬垫氧化物层。“斜坡”意味着衬垫氧化物的侧壁不是垂直的。相反，衬垫氧化物的侧壁明显地偏离90度。斜坡衬垫氧化物的侧壁最好是大约45度或更小。在本发明中，利用在清除氧化物过程中有高度选择性的化学氧化物清除(COR)步骤来提供斜坡。本发明的这一步骤借助于在完全清除先前制作在栅孔中的氮化物层上的氧化物层的情况下削尖衬垫氧化物层，而在栅孔中暴露部分衬底10。COR步骤是一种汽相化学氧化物清除工艺，其中用汽相HF和NH3作为腐蚀剂，并使用低压(6毫乇或更低)。
在削尖栅孔中的衬垫氧化物层之后，环绕栅孔(包括被削尖的衬垫氧化物层和衬底的暴露表面)制作高k高温金属氧化物层26(见图1E)。利用包括但不局限于CVD、等离子体辅助CVD、原子层淀积、溅射的常规淀积工艺以及其它相似的淀积工艺，来制作高k高温金属氧化物。如上所述，高k高温材料包括在950-1050℃下，最好是在1000℃下退火10秒钟时不退化的金属氧化物。能够用于本发明的一些高k高温金属氧化物的例子包括Al2O3和TiO2。
对于本发明，高k高温介电材料的厚度是不严格的，但通常，高k高温介质的厚度约为5-30埃。
在制作高k高温金属氧化物之后，利用诸如CVD、等离子体辅助CVD、蒸发和溅射之类的本技术领域熟练人员众所周知的常规淀积工艺，用栅导体28来填充栅孔。能够用于本发明的适当的栅导体包括但不局限于多晶硅、W、Ta、TiN和其它相似的导电材料。在图1E中也示出了包括栅导体的结构。若有需要，则在用栅导体填充栅孔之后，使用常规的整平工艺。
接着，如图1F所示，利用常规的镶嵌回腐蚀工艺，从结构中清除氮化物层16。具体地说，在镶嵌回腐蚀工艺中，采用了在清除氮化物比之其它周围材料层具有高度选择性的诸如热磷酸之类的化学腐蚀剂；本发明中使用的镶嵌回腐蚀工艺停止于上述的衬垫氧化物层上。
在清除氮化物层16之后，利用本技术领域熟练人员众所周知的技术，来制造通常出现在MOSFET器件中的其它的各个区域。图1G示出了本发明的一个完成的MOSFET器件，这是MOSFET器件区周围的剖面图。具体地说，图1G包括：源/漏延伸部分30、隔板32、源/漏区34和硅化物区36。利用常规的离子注入和退火方法来形成源/漏延伸部分。在激活源/漏延伸部分过程中使用的退火温度通常约为950℃或更高，而退火时间通常约为5秒钟或更短。
隔板32由任何常规氮化物(例如Si3N4)或氧化物(例如SiO2)组成，并利用本技术众所周知的常规淀积工艺来制作，然后用RIE或其它相似的腐蚀工艺对其进行腐蚀。隔板32的厚度可以变化，但通常其厚度约为100-150nm。
用常规的离子注入和退火方法来制作源/漏区34。对于约为5秒钟或更短的时间长度，用来激活源/漏区的退火温度通常约为1000℃或更高。
利用本技术领域熟练人员众所周知的自对准形成硅化物的常规工艺步骤，在结构中制作硅化物区。由于这一工艺步骤是众所周知的，故此处不提供其详细描述。
然后可以对图1G所示的结构进行本技术众所周知的并在例如著作R.Colclaser,″Micro Electronics processing and Device Design″,Chapter 10,pages 266-269,John Wiley and Sons publisher,1980中所述的其它常规CMOS工艺步骤。
上述描述和图1A-1G示出了本发明的方法，其中使用高k高温金属氧化物作为栅导体。下面的描述和图2A-2F示出了当高k低温金属氧化物被用作栅导体时的本发明的方法。要指出的是，图2A-2F所示的第二实施例代表了本发明的最佳实施例。
图2A示出了本发明的这一实施例中使用的初始结构。具体地说，图2A包含衬底10、隔离沟槽18以及包含衬垫氧化物层14、多晶硅层52和SiO2层54的虚拟叠层膜50。利用结合本发明第一实施例的上述的工艺步骤来制作沟槽和衬垫氧化物层。利用诸如CVD、等离子体辅助CVD和溅射之类的常规淀积工艺，来制作虚拟叠层膜50的多晶硅层，以低压CVD工艺最佳。多晶硅层52的厚度对本发明来说是不严格的，但通常多晶硅层的厚度约为1000-2000埃。
利用原硅酸四乙酯(TEOS)的臭氧淀积，或能够形成SiO2层的任何其它的淀积工艺，来制作虚拟叠层膜50的SiO2层。SiO2层54的的厚度对本发明来说是不严格的，但通常SiO2层的厚度约为300-500埃。
图2A还示出了存在用来制造虚拟叠层膜50中的虚拟栅区的图形化光刻胶56。用于本发明的光刻胶是光刻中使用的任何常规的光刻胶，并用常规的淀积工艺、曝光和显影方法被制作在SiO2层上。
在本发明中，用图形化的光刻胶来保护部分虚拟叠层膜50。用诸如RIE或等离子体腐蚀之类的常规干法腐蚀工艺，来清除虚拟叠层膜50的未被保护的区域，停止于衬垫氧化物层14上。在清除未被保护的层，亦即虚拟叠层膜的多晶硅层52和SiO2层54之后，用本技术领域熟练人员众所周知的常规剥离方法来剥离图形化的光刻胶，并用常规的湿法腐蚀工艺来清除虚拟栅区的先前被保护的SiO2层。
在从虚拟栅区清除图形化的光刻胶和SiO2层54之后，制作源/漏延伸部分30、隔板32、源/漏区34、和硅化物区36(在源/漏区上和在虚拟栅的多晶硅的顶部上)，提供图2B所示的结构。用与以上指出的相同的工艺技术，制作区域30、32、34和36。要指出的是，图2B示出了包括含有多晶硅层52的虚拟栅区58的结构。虚拟栅区的使用以及区域30、32、34和36的稍后的制作，使人们能够用高k低温金属氧化物作为栅绝缘体。
接着，如图2C所示，用诸如CVD、低压CVD、等离子体辅助CVD之类的常规淀积工艺和其它相似的能够在结构上形成共形层的淀积工艺，在结构上制作绝缘层60。诸如SiO2之类的任何绝缘材料能够被用作层60。绝缘层的厚度可以根据所使用的材料的类型而变化，但通常绝缘层的厚度约为2000-3000埃。
在结构上制作绝缘层之后，可以使用诸如化学机械抛光或研磨之类的任何常规整平工艺。要指出的是，本发明这一步骤中使用的整平工艺，在清除制作在多晶硅层52上的硅化物区36之后被停止。于是，这一整平就暴露出虚拟栅区的多晶硅层52。图2D示出了在进行上述整平之后形成的结构。
接着，利用RIE或化学下游腐蚀工艺清除多晶硅层52，将衬垫氧化物层14暴露出来。然后用上述的COR工艺腐蚀被暴露的衬垫氧化物，以便在衬垫氧化物层中形成斜坡，见图2E。组合的腐蚀步骤在结构中形成窗口24，其中所述的窗口包含削尖的衬垫氧化物层。
在衬垫氧化物层中形成斜坡之后，利用先前结合高k高温金属氧化物所述的常规淀积工艺，在窗口中制作诸如ZrO2、钛酸钡、钛酸锶、钛酸锶钡之类的高k低温金属氧化物层62。高k低温金属氧化物的厚度约为5-30埃。
在淀积高k低温金属氧化物之前，可以在窗口中制作例如氮化物的可选势垒层。当可选势垒层被制作在结构中时，可以使用诸如CVD的任何常规淀积工艺，且依赖于制作势垒层过程中所使用的材料的类型，其厚度可以变化。
在结构中制作高k低温金属氧化物之后，在大约950℃或更低的温度下，于N2中进行大约30秒钟或更短的快速热退火。可以利用单个升温和恒温周期或多个升温和恒温周期来进行快速热退火。
然后，用以上指出过的工艺步骤，在窗口中制作如上所述的导电材料28。于是可以用例如CMP的常规整平工艺来整平此结构，以便提供图2F所示的结构。
在图1G和2F中，都示出了采用高k金属氧化物作为栅绝缘体的MOSFET器件。而且，图1G和2F所示的MOSFET器件具有低的覆盖电容和短的沟道长度。短的沟道长度是对衬垫氧化物层提供斜坡的一个直接的结果。借助于以上述的方式使衬垫氧化物层成斜坡，沟道38比光刻工艺能够得到的短得多。
虽然对于其最佳实施例已经详细地描述了本发明，但本技术领域的熟练人员能够理解，可以作出形式和内容方面的上述和其它的改变而不偏离本发明的构思与范围。因此认为本发明不局限于所述的准确形式和细节，而是在所附权利要求的范围内。

Claims (32)

1．一种制作具有低的覆盖电容和短的沟道长度的MOSFET器件的方法，它包含下列步骤：
(a)提供具有制作在衬底表面上的叠层膜的半导体结构，所述叠层膜包含至少一个制作在所述衬底的所述表面上的衬垫氧化物层和一个制作在所述衬垫氧化物层上的氮化物层；
(b)在所述氮化物层中制作停止在所述衬垫氧化物层上的栅孔；
(c)在所述栅孔中的所述氮化物层上制作氧化物层；
(d)对所述氧化物层和部分所述衬垫氧化物层进行腐蚀，以便在所述栅孔中提供暴露所述衬底的窗口，其中的衬垫氧化物层被所述腐蚀削尖；
(e)在所述栅孔周围和所述暴露的衬底上制作高k高温金属氧化物层；
(f)用栅导体填充所述栅孔；
(g)清除暴露部分所述高k高温金属氧化物的所述氮化物层；以及
(h)完成所述MOSFET器件的制造。
2．权利要求1的方法，其中的步骤(h)包括在所述栅导体下面的所述衬底中形成激活的源/漏延伸部分；在所述暴露的高k高温金属氧化物上制作隔板；在所述衬底中形成激活的源/漏区；以及在部分所述衬垫氧化物中和在所述栅导体中形成硅化物区。
3．权利要求1的方法，其中所述衬底包括其中制作的隔离区。
4．权利要求3的方法，其中所述隔离区包括氧化物衬里和沟槽介电材料。
5．权利要求1的方法，其中所述衬底是选自Si、Ge、SiGe、GaAs、InAs、InP和层状半导体的半导体材料。
6．权利要求1的方法，其中所述栅孔用光刻和腐蚀方法制作。
7．权利要求1的方法，其中所述氧化物层用淀积氧化物材料的方法制作。
8．权利要求1的方法，其中利用化学氧化物清除工艺来进行步骤(d)。
9．权利要求8的方法，其中在汽相HF和NH3中进行所述化学氧化物清除工艺。
10．权利要求8的方法，其中在大约8毫乇或更低的压力下进行所述化学氧化物清除工艺。
11．权利要求1的方法，其中所述高k高温金属氧化物是Al2O3或TiO2或能够经受住950-1050℃下10秒钟退火的任何其它氧化物。
12．权利要求1的方法，其中用选自化学汽相淀积(CVD)、等离子体辅助CVD、溅射、原子层淀积的淀积工艺和其它相似的淀积工艺，来制作所述高k高温金属氧化物。
13．权利要求1的方法，其中所述高k高温金属氧化物的厚度约为5-30埃。
14．权利要求1的方法，其中所述栅导体是多晶硅、W、Ta、TiN和其它相似的导体。
15．权利要求1的方法，其中的步骤(g)包含镶嵌工艺步骤，其中使用了化学腐蚀剂。
16．一种制作具有低的覆盖电容和短的沟道长度的MOSFET器件的方法，它包含下列步骤：
(ⅰ)提供具有制作在衬底表面上的虚拟叠层膜的半导体结构，所述虚拟叠层膜包含至少一个制作在所述衬底的所述表面上的衬垫氧化物层、一个所述衬垫氧化物层上的多晶硅层、以及一个制作在所述多晶硅层上的SiO2层；
(ⅱ)清除所述虚拟叠层膜的选定部分，停止在所述衬垫氧化物层上，以便提供图形化的虚拟栅区；
(ⅲ)从所述图形化的虚拟栅区清除所述SiO2层；
(ⅳ)在所述虚拟栅区下面的所述衬底中形成激活的源/漏延伸部分；
(ⅴ)在所述虚拟栅区的侧壁上形成隔板；
(ⅵ)在所述衬底中形成激活的源/漏区；
(ⅶ)在部分所述衬垫氧化物层中和在所述虚拟栅区的所述多晶硅层中形成硅化物区；
(ⅷ)制作围绕所述虚拟栅区的绝缘层；
(ⅸ)整平所述绝缘层，停止在所述虚拟栅区中的所述多晶硅层处；
(ⅹ)制作窗口，以便暴露部分所述衬底，借助于清除所述虚拟栅的所述多晶硅层以及借助于削尖所述虚拟栅的部分所述衬垫氧化物层，而制作所述窗口；
(ⅹⅰ)在所述窗口中制作高k低温金属氧化物；以及
(ⅹⅱ)用低温下淀积的栅导体填充所述窗口。
17．权利要求16的方法，其中所述衬底包括其中制作的隔离区。
18．权利要求17的方法，其中所述隔离区包括氧化物衬里和沟槽介电材料。
19．权利要求16的方法，其中所述衬底是选自Si、Ge、SiGe、GaAs、InAs、InP和层状半导体的半导体材料。
20．权利要求16的方法，其中步骤(ⅱ)包含提供光刻胶、图形化所述光刻胶、以及腐蚀不包括图形化光刻胶的区域。
21．权利要求16的方法，其中用化学腐蚀剂清除所述SiO2层。
22．权利要求16的方法，其中用选自CVD、低压CVD、等离子体辅助CVD的淀积工艺以及能够形成共形层的其它相似的淀积工艺，来制作所述绝缘层。
23．权利要求16的方法，其中用化学机械抛光或研磨方法来进行所述整平。
24．权利要求16的方法，其中用化学氧化物清除工艺来进行步骤(ⅹ)。
25．权利要求24的方法，其中在汽相HF和NH3中进行所述化学氧化物清除工艺。
26．权利要求24的方法，其中在大约8毫乇或更低的压力下进行所述化学氧化物清除工艺。
27．权利要求1的方法，其中所述高k低温金属氧化物是ZrO2、钛酸钡、钛酸锶和钛酸锶钡、或当使用950-1050℃下10秒钟退火时不退化的任何其它氧化物。
28．权利要求16的方法，其中用选自化学汽相淀积(CVD)、等离子体辅助CVD、溅射、原子层淀积的淀积工艺以及其它相似的淀积工艺，来制作所述高k低温金属氧化物。
29．权利要求16的方法，其中所述高k低温金属氧化物的厚度约为5-30埃。
30．权利要求16的方法，其中所述高k低温金属氧化物在大约950℃或更低的温度下，在N2中被退火大约30秒钟或更短的时间。
31．权利要求16的方法，其中所述栅导体是多晶硅、W、Ta、TiN和其它相似的导体。
32．MOSFET器件，它包含至少一个制作在半导体衬底上的栅区，所述栅区包含栅导体、栅绝缘体和隔板，所述栅绝缘体是介电常数大于7.0的高k金属氧化物，所述栅区还包含制作在所述栅绝缘体下面的亚光刻沟道，其中所述沟道长度借助于在削尖的衬垫氧化物层上制作部分所述栅绝缘体而被确定。
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