CN1242888A - 用于通信设备减少备用电流的方法和装置 - Google Patents

用于通信设备减少备用电流的方法和装置 Download PDF

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CN1242888A
CN1242888A CN97181226A CN97181226A CN1242888A CN 1242888 A CN1242888 A CN 1242888A CN 97181226 A CN97181226 A CN 97181226A CN 97181226 A CN97181226 A CN 97181226A CN 1242888 A CN1242888 A CN 1242888A
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system clock
synchronizer
clock
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circuit
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CN1104098C (zh
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J·H·温德尔鲁普
B·M·G·林德奎斯特
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Telefonaktiebolaget LM Ericsson AB
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W52/00Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02Power saving arrangements
    • H04W52/0209Power saving arrangements in terminal devices
    • H04W52/0261Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0287Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
    • H04W52/029Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment reducing the clock frequency of the controller
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0802Details of the phase-locked loop the loop being adapted for reducing power consumption
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/14Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/08Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W52/00Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02Power saving arrangements
    • H04W52/0209Power saving arrangements in terminal devices
    • H04W52/0261Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0287Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
    • H04W52/0293Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
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  • Circuits Of Receivers In General (AREA)
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Abstract

方法和装置用于通信设备减少备用电流。在备用模式,具有相对较高精度和相对较高功率的时钟减电而一个较低功率,较低频率的时钟被用来保持系统同步。提供了同步装置来提高备用模式下较低频率时钟的精确度。

Description

用于通信设备减少备用电流的方法和装置
发明领域
本发明一般地涉及通信系统。更特别地,本发明涉及移动通信设备在备用运行模式期间减少电流。
发明背景
为了减少移动通信设备的电能消耗,常常需要提供一种备用或空闲运行模式。在备用模式期间,设备仅在侦听到一页的较短间隙有效,而在剩余间隙减电(Power down)。重要的是保持正确的系统时序以保证在精确的确切间隙内设备有效。在备用或空闲模式时尽可能大地减少电能消耗也是非常必要。
为了在典型的GSM通信设备内保持系统时序,要提供一个相对较高精确度(例如,1ppm)的时钟并在所有时间里,包括在备用期间保持有效。这种时钟消耗相对大量的电能。用于移动电话的一个实施例时钟是一运行在,例如,13MHz下的压控晶体振荡器(VCXO)。另外,移动电话还可以有一简单的低功率实时时钟(RTC)用于在通信设备显示器上显示时间。该时钟运行在相对很低频率(32.768Hz)和一般不很准确(例如,10-20ppm,这取决于时钟晶体的质量)。
因此为了减少电能消耗,有必要在通信设备备用运行模式期间关掉高频率高电流的时钟,而保持准确的系统时序。
美国授予Hietala等人的专利5,493,700(Hietala’700)揭示了用于无线电话的自动频率控制(AFC)装置。该无线电话包括发射器,接收器,用户接口,控制逻辑和合成器,该合成器以适当的频率给发射器和接收器提供信号同时给用户接口和控制逻辑提供时钟信号。该控制逻辑控制合成器的频率。该合成器包括两个N-分频合成器和一个锁相环。专利Hietala’700没有揭示在备用模式能够减少电流而又保持准确的系统时间的方法。
美国授予Hietala等人的专利5,505,802(Hietala’802)揭示了多累加器sigma-delta N-分频合成器,该合成器控制压控晶体振荡器输出信号的频率。合成器会带来相对较小的频率偏移增量。Hietala’802没有揭示在备用模式能够减少电流而又保持准确的系统时序的方法。
美国授予Hietala等人的专利5,070,310(Hietala’310)揭示了用于数字无线收发器的多锁存累加器N-分频合成器,该合成器可以避免通过多个累加器时的数据“波纹”并能减少伪信号。Hietala’310没有揭示在备用模式能够减少电流而又保持准确的系统时序的方法。
美国授予Shepherd等人的专利5,331,293(Shepherd)揭示了一个数字频率合成器,该合成器能够对伪信号进行补偿,办法是通过检波,转换和放大合成器的输出以产生用于调节参考晶体振荡器的补偿信号。Shepherd没有提及减少备用模式时需要的电能而又保持准确的系统时序。
在Pacific Digital Cellular移动电话中,在空闲模式期间,减少高频率晶体振荡器减电而使用第二晶体振荡器,该晶体振荡器运行在较低的频率并消耗较少的电能,这一点已广为人知。然而,在PDC系统中,符号速率是21ks/s,该速率显著低于GSM系统的270.833ks/s。结果是,PDC系统需要的时序精度远远低于GSM和其它系统所需要的,因此PDC系统不需要一准确的低频晶体振荡器。因此,PDC系统减少电能消耗的方法不适合GSM或其它相对高位速率并需要相对严格的时序的系统。
发明概述
根据本发明的实施例,通信设备内用于减少电能消耗的电路包括一个低功率,低频率实时时钟(RTC)晶体振荡器和同步装置,该装置用于使RTC晶体振荡器和相对较高功率和较高频率的主时钟保持同步。在备用或空闲模式期间,高频率主时钟减电(即,降低功耗),系统时序由较低频率时钟保持。根据多个实施例,同步装置可通过如下方法实现,开环实时修正电路,数字闭环实时修正电路,锁相环(PLL)修正电路,N-分频PLL电路,或其它等效装置。
本发明的方法和装置允许通信设备运行在低功率和备用模式下而仍然保持准确的系统时序。本发明在GSM系统或其它需要相对高精度时序的移动通信系统中尤其有用。
附图简要说明
对本发明更加完整的理解可以参照附图阅读下述优选实施例的详细描述而获得,在附图中类似的参考标识标识类似的元件,其中:
图1是减少电能消耗电路的一个框图,该电路根据本发明的一个实施例采用开环和闭环数字时序修正电路;
图2是减少电能消耗电路的一个框图,该电路根据本发明的另一个实施例采用锁相环数字时序修正电路;
图3是减少电能消耗电路的一个框图,该电路根据本发明的一个可选实施例采用sigma-delta调制器;
图4是减少电能消耗电路的一个框图,该电路根据本发明的又另一个实施例采用N-分频锁相环数字时序修正电路;
优选实施例的详细说明
根据本发明,运行在具有相对较高数据速率或具有相对严格时间要求的系统(例如,根据GSM标准的移动电信系统)的通信设备包括能够使设备运行在两种模式的电路:正常运行模式和备用运行模式。在备用运行模式,设备至少有部分元件只有在特定的时间间隙才处于加电状态。一个区别于参考时钟的备用时钟提供用来保持准确的时序和保证在准确的时间间隙使得合适的元件加电。备用时钟工作在相对参考时钟较低的频率,并比参考时钟消耗较小的电流。本发明包括用于将备用时钟和参考时钟同步的同步装置,以便从一个具有相对较低精度(例如,10-20ppm)的时钟获得相对较高的时钟精度(例如,1ppm)。
现在参看图1所示本发明的第一实施例,其中一个开环时序修正电路用来将备用(RTC)时钟10和参考时钟12同步。根据此实施例,RTC晶体振荡器10的频率被准确量测然后系统时序相应地被修正或调整。在知道RTC时钟10的确切频率下,能够在备用空闲时间里使用RTC信号作为系统时钟,以便准确的VCXO 12关闭时仍能保持系统同步。如图1所示,第一和第二计数器14和16分别连接来接收RTC 10和VCXO 12的输出。逻辑电路18接收计数器输出并在预定的间隙内基于计数器输出产生一个精确的RTC信号。基于VCXO 12的频率来选择预定的间隙,该预定间隙优选足够长以能获得想要的精确度。
做为选择,可以调整RTC频率使得RTC与参考时钟12同步。该调整可以通过将RTC 10和更精确的VCXO 12作数字闭环频率锁定来实现,如图1虚线所示。
闭环电路包括RTC 10,VCXO 12,计数器14和16,逻辑电路18和控制RTC 10频率的装置,该装置可以由连接在逻辑电路18的输出和RTC时钟10的输入之间的反馈环形式的D/A转换器20来实现。
闭环方法需要相对较长的修正时间来达到想要的精确度。在通信设备第一次启动时补偿值优选需要频繁地更新,是因为加电时设备需要自加热。在持续运行一段时间之后,不需要频繁地更新补偿值。
闭环方法有利于获得一个很高精度的RTC时钟(理想时与VCXO有相同的精确度)。相对较低费用的晶体振荡器(例如,在32.768kHz时有20ppm的精确度)可以用作振荡器。RTC晶体振荡器的运行温度特性仅仅需要限定在RTC频率控制范围之内。
一个可选实施例,用于减少RTC频率修正时间,包括使用一个锁相环(PLL)。在移动电话内用PLL将相对较高频率(1GHz)振荡器锁定到精确的较低频率(13MHz)VCXO的技术已为人所熟知,本发明用PLL将相对较低频率振荡器10锁定到精确的较高频率VCXO 12。应当理解的是PLL锁定时间是滤波环截止频率(假定比较频率足够高)的函数,如下所讨论的。虽然较高截止频率带来较大的噪声,在本实施例中较大的噪声不会显著影响RTC 10。
PLL锁定RTC 10,使其精度达到当VCXO 12加电时VCXO的精度,而当VCXO 12减电时在RTC 10内保持此精度值。
本实施例的优选实现示于图2。图2的电路包括相位检测器22用于给充电泵24提供数字输出。充电泵24提供一个到滤波环26的高阻充电脉冲输出。在本实施例中充电脉冲的精度是不重要的,因为对噪声或锁定时间没有严格的要求。充电泵24的输出通过低通滤波器26滤波并反馈回到RTC 10来控制低功率时钟的频率。
如上推及,有一个因素限制了PLL的锁定时间,这就要求比较频率必须足够大。比较频率f比较定义为:
其中N和M是整数。
RTC频率一般是32.768kHz和GSM中VCXO频率典型地是13MHz。结果是最大比较频率为64Hz。典型地PLL的环带宽低十倍,这意味着6Hz的环带宽和几乎半秒的锁定时间。这是不够的,因为如果在GSM中,需要锁定时间<20ms和2秒的VCXO减电时间来减少电能消耗。
为了获得较高的比较频率(在kHz级),需要改变RTC频率,特别是VCXO频率预先确定时,如在GSM系统中。例如,一个40625Hz的RTC频率使得RTC易于实现。这种实现的不利之处在于这一频率的晶体不是“标准”晶体因而比标准32768Hz晶体较贵些。
根据又另一实施例,较高的比较频率可通过使用N-分频PLL来实现。N-分频PLL工作时针对N和N+1之间的一个频率将计数器值改变,因此产生一个为另一个原有频率的分数频的新频率。
作为一个例子,假设RTC是32768Hz和VCXO是13MHz。比较频率优选为大于2kHz。2048Hz选作比较频率,因为这就是32768/16且易于实现。此时VCXO的分频比是: N = 13 MH z 2048 = 6347,65625 = 6347 + 21 32
这意味着为了锁定PLL,除数N(6347)使用11周期和除数N+1(6348)使用21周期。因此有另一个较长的周期来完全锁定N-分频PLL。这一周期是2048Hz/32=64Hz,这和前述的周期相同。在可替代的实施例中避免RTC的64Hz调制将是合适的。
最简单的方案是提供相对较低环带宽(例如,6Hz),以使得RTC不必跟随64Hz调制。然而,这会降低在N-分频PLL中较高比较频率带来的速度好处。
另一方案是给环提供补偿电流以补偿相位检测器引起的误差。该方案可通过添加附加的模拟充电泵电路到相位检测器充电泵加以实现。
另一方案示于图3,包括一个数字sigma delta调制器28去数字式控制计数器的除法比率以产生21/32的比率。这不需要附加的模拟电路并提高调制噪声频率。
一个附加的方案示于图4,包括一个模e调制器30,并产生一个接近于,但不等于,确切RTC频率的频率。举例为: N = 13 MH z 2048 = 6347 + 21 32 = 6347 + 2 3 f RTC = 13 MH z 6347 + 2 3 × 16 = 32767,946 H z
因此,RTC频率并不精确地为32768Hz而是稍低些(低1.6ppm)。这个小的差别对实时时钟10而言是不足道的且是如此的小而使系统保持同步没有困难。这种实现取得一个显著的好处,因为N-分频周期是2048/3=683Hz,而在环带宽之外。图4的实施例提供了具有快锁定时间(<20ms)的很简单的PLL。所有N-分频周期调制均可在环外实现,而在环内不需要一般的N-分频补偿。
本发明通过使用能提高低功率时钟的精确度的同步装置,使得在不需要时将相对准确但消耗较大功率的VCXO减电而代之以使用较低功率,较低频率的时钟来仍然保持系统同步成为可能。
虽然前述说明已经包括许多细节和特征,应当指出这些只是说明性的而无意限制本发明。本领域稍有常识的人易于明白,对所揭示的事例的许多修改将会不背离本发明的精神和范围,正如下述权利要求及其等价所定义的。

Claims (18)

1.用于减少电信设备电能消耗的方法,包含步骤:
在预定的时间周期内将电信设备内包含的第一系统时钟减电(Power down);以及
在所述预定的时间周期内将电信设备内包含的第二系统时钟加电(Power up),该第二系统时钟比第一系统时钟消耗较少电流,和该第二系统时钟包括在预定的时间周期内充分地将第二系统时钟与第一系统时钟同步的同步装置。
2.权利要求1所述的方法,其中同步装置包括分别用于第一和第二系统时钟计数的第一和第二计数器,和用于充分地将第二系统时钟与第一系统时钟同步的逻辑电路。
3.权利要求2所述的方法,其中同步装置更包括连接在逻辑电路的输出和第二系统时钟输入之间的反馈环。
4.权利要求3所述的方法,其中反馈环包括一个数字到模拟的转换器。
5.权利要求1所述的方法,其中同步装置包括分别用于第一和第二系统时钟计数的第一和第二计数器,一个相位检测器用于检测在第一和第二计数器之间的相位差,一个充电泵用于将相位差转换成充电脉冲和将充电脉冲供给第二系统时钟。
6.权利要求5所述的方法,其中同步装置更包括一个低通滤波器,用于在将充电脉冲供给第二系统时钟之前对其滤波。
7.权利要求5所述的方法,其中同步装置更包括一个连接在第一计数器的输出和第一计数器的输入之间的调制器,该调制器数字式地控制第一计数器的分频比。
8.权利要求7所述的方法,其中所述调制器是一个从外部源接收控制信息的sigma delta调制器。
9.权利要求7所述的方法,其中所述调制器不接收外部控制信息。
10.电信设备内的同步电路,包含:
第一系统时钟,该时钟工作在第一功率水平;以及
第二系统时钟,该时钟工作在比所说第一功率水平低的第二功率水平,该第二系统时钟包括在第一系统时钟减电的预定时间周期内基本上将第二系统时钟与第一系统时钟同步的同步装置。
11.权利要求10所述的电路,其中同步装置包括分别用于第一和第二系统时钟计数的第一和第二计数器,和用于充分地将第二系统时钟与第一系统时钟同步的逻辑电路。
12.权利要求11所述的电路,其中同步装置更包括连接在逻辑电路的输出和第二系统时钟输入之间的反馈环。
13.权利要求12所述的电路,其中反馈环包括一个数字到模拟的转换器。
14.权利要求10所述的电路,其中同步装置包括分别用于第一和第二系统时钟计数的第一和第二计数器,一个相位检测器用于检测在第一和第二计数器之间的相位差,一个充电泵用于将相位差转换成充电脉冲和将充电脉冲供给第二系统时钟。
15.权利要求14所述的电路,其中同步装置更包括一个低通滤波器,用于在充电脉冲供给第二系统时钟之前对其滤波。
16.权利要求14所述的电路,其中同步装置更包括一个连接在第一计数器的输出和第一计数器的输入之间的调制器,该调制器数字式地控制第一计数器的分频比。
17.权利要求16所述的电路,其中所述调制器是一个从外部源接收控制信息的sigma delta调制器。
18.权利要求16所述的电路,其中所述调制器不接收外部控制信息。
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