CN1237614C - 一种金属电互连结构 - Google Patents

一种金属电互连结构 Download PDF

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CN1237614C
CN1237614C CNB011179368A CN01117936A CN1237614C CN 1237614 C CN1237614 C CN 1237614C CN B011179368 A CNB011179368 A CN B011179368A CN 01117936 A CN01117936 A CN 01117936A CN 1237614 C CN1237614 C CN 1237614C
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solder
substrate
conductive pole
interconnection structure
copper
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CN1321784A (zh
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M·J·恩特兰特
B·彼得森
S·K·雷
W·E·萨林斯基
A·K·萨克赫尔
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Ultratech Corp
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Abstract

本发明一般涉及到一种新的半导体芯片载体连接，其中利用表面安装技术制作芯片载体和第二层组装件。更确切地说，本发明包含表面安装技术，作为几个例子，例如球栅阵列(BGA)、柱栅阵列(CGA)，其中表面安装技术主要包含一种非焊料金属连接，例如铜连接。本发明还涉及到柱栅阵列结构及其工艺。

Description

一种金属电互连结构
技术领域
本发明一般涉及到一种新颖的半导体芯片载体连接，其中利用表面安装技术制作半导体芯片载体和第二层组装件。更确切地说，本发明包含表面安装技术，举几个例子，例如球栅阵列(BGA)，柱栅阵列(CGA)，其中表面安装技术主要包含一种非焊料金属连接，例如铜连接。本发明还涉及到柱栅阵列结构及其工艺。
背景技术
随着新技术的不断发展，半导体器件变得更小和更密集。然而，电路密度的增加在芯片连接方面总体上相应地增大了困难。因此，面对这种挑战，驱使芯片制造商依靠不断的发明创新来改进其产品。尽管在芯片互连技术方面已取得了明显的改进，但仅靠这些还不足以克服所有的问题。
已出现目前主要发明的现有技术领域是采用各种无铅焊料合金作为芯片和衬底之间，以及衬底和下一层互连之间的连接。
例如，美国专利No.5,328,660(Gonya)公开了一种无铅、高温、锡基多成份焊料，其中的焊料合金含有78.4％重量比的锡，其余成份为银、铋和铟。
同样，美国专利No.5,411,703(Gonya)提出了一种基于多成份的无铅焊料，其中高固线温度的焊料合金含有93～94％重量比的锡，其余成份为锑、铋和铜。
而美国专利No.5,733,501(Takao)公开了一种无铅焊料合金的疲劳测试，其中铜线通过玻璃环氧树脂和铜层叠板/衬底中的孔，并被焊料合金焊接。
美国专利No.5,874,043(Sarkhel)公开了另一种基于多种成份的无铅富锡焊料，其中焊料合金含有70.5～73.5％重量比的锡，其余成份为银和铟。
另一发明领域是柱栅阵列(CGA)芯片载体，在芯片载体技术中正得到越来越多的应用，特别是当芯片载体由陶瓷材料制成时，更是如此。芯片载体通常由陶瓷材料或有机叠层材料制成。多个焊料柱被固定到芯片载体和下一层封装件的I/O(输入/输出)焊点，以便在二者之间提供电连接。例如见已转让给美国纽约州阿莫克的国际商业机器公司的美国专利No.5,324,892(Granier)，此处将其内容列为参考，它提出了一种利用焊料柱制造电互连的方法。该焊料柱由熔点高于约250℃的焊料制成。利用熔点低于约240℃的焊料，将预制的焊料柱固定到芯片载体。这些焊料柱被单独制造，并被送入炉子装置，然后使其对准载体。借助于低温焊料合金回流来固定高温焊料柱。然而，正如本领域的技术人员所知，直径通常很小的焊料柱是非常软的，其结果是在制造芯片载体模块时，该焊料柱很容易被损坏或弯曲。特别是若位于I/O焊点阵列上的多个位置，这一问题就更复杂。通常的解决途径是代价高昂的返工。另外，在电路板组装期间，这些柱栅阵列模块容易遭受处置时的损坏。再者，随着互连密度的增加，焊料柱的直径必须减小。当然，焊料柱直径的减小将会降低这些焊料柱的抗弯强度，并增加了对这些焊料柱的处置损坏。
发明内容
如所知，现有技术使用一种无铅焊料系统，但没有提到用非焊料金属互连部分来将芯片连接到衬底或将衬底连接到电路板。同样，也没有提到结合使用铜芯柱阵列与高熔点和低熔点焊料合金来将这种铜柱栅阵列连接到芯片载体和有机电路板。这些高和低熔点焊料合金可以从含铅或无铅焊料合金中选取。而且，本发明的目的是一种柱栅阵列型结构，它缓解了现有技术的问题，并使得能够大批量制造具有柱栅阵列连接的芯片载体。
本发明是一种高密度柱栅阵列连接的新颖方法和结构。
因此，本发明的目的是提供一种可提供高密度柱栅阵列连接的结构和方法。
本发明的另一个目的是提供一种非焊料金属互连。
本发明的再一个目的是提供一种芯片载体与电子元件之间的非焊料金属互连。
本发明还有一个目的是提供一种芯片载体和电子元件之间的铜互连。
本发明再一个目的是提供一种使用铅基固定焊料的芯片载体和电子元件之间的铜互连，例如衬底一侧为90/10的铅/锡，而电路板一侧为37/63的铅/锡低共熔体。
本发明再一个目的是提供一种无铅焊料，例如用于衬底一侧的锡/锑和电路板一侧的锡/银/铜合金，以便提供电路板与衬底之间铜互连的牢固连接。
本发明提供了芯片载体衬底上的第一焊点与第二衬底上的第二焊点之间的一种金属电互连结构，包括：具有第一端和第二端的导电柱，所述导电柱由非焊料金属材料构成，所述第一端连接到所述芯片载体衬底上的第一焊点，所述第二端连接到所述第二衬底上的第二焊点；其中，所述导电柱的第一端通过第一焊料连接到所述芯片载体衬底上的第一焊点，所述导电柱的第二端通过第二焊料连接到所述第二衬底上的第二焊点；其中，所述第一焊料具有第一熔点，所述第二焊料的熔点比第一焊料的熔点低。
根椐本发明的互连结构，其中至少50％以上的所述导电柱由非焊料金属材料构成。
根椐本发明的互连结构，其中所述导电柱由铜、纯铜、或完全退火的铜制成。
根椐本发明的互连结构，其中所述导电柱的材料选自铜、镍及其合金、以及锡为20％重量比的铜-锡合金。
根椐本发明的互连结构，其中所述导电柱的直径为0.2～0.5mm。
根椐本发明的互连结构，其中所述第一衬底是陶瓷衬底。
根椐本发明的互连结构，其中所述第二衬底是有机板。
根椐本发明的互连结构，其中至少部分所述导电柱具有至少一个由至少一种材料组成的涂层。
根椐本发明的互连结构，其中至少部分所述导电柱具有至少一个由至少一种材料组成的涂层，且其中所述至少一种材料选自铜、镍、银、锡及其合金。
根椐本发明的互连结构，其中所述涂层的厚度为0.5～4.0μm。
根椐本发明的互连结构，其中所述导电柱是利用软焊或硬焊的方法被紧固于所述芯片载体衬底的。
根椐本发明的互连结构，其中所述第二衬底是印刷电路板，所述导电柱是利用软焊或硬焊的方法被紧固于所述印刷电路板的。
因此，在一种情况下，本发明包含第一衬底上的第一个焊点和第二衬底上的第二个焊点之间的金属电互连，其中所述电互连是非焊料金属材料。
在另一种情况下，本发明包含一种将互连紧固到衬底的方法，其中至少50％以上的所述互连是非焊料金属材料，此方法包括下列步骤：
(a)对所述互连的末端进行助熔处理，
(b)将所述互连的经助熔处理过的所述末端置于所述衬底上至少具有一种焊料的焊点上，
(c)在靠近所述经助熔处理过的末端和所述焊点处，使温度由室温升高到约100～300℃，并在所述焊料回流后，将所述互连降低到室温，从而使所述互连紧固于所述衬底。
在另一种情况下，本发明包含一种使互连紧固于印刷电路板的方法，其中至少50％以上的所述互连是非焊料金属材料，此方法包含下列步骤：
(a)对所述互连的末端进行助熔处理，
(b)将所述互连的经助熔处理过的所述末端置于所述印刷电路板上至少具有一种焊料的焊点上，
(c)在靠近所述经助熔处理过的末端和所述焊点处，使温度由室温升高到约100～300℃，并在所述焊料回流后，将所述互连降低到室温，从而使所述互连紧固于所述印刷电路板。
在再一种情况下，本发明包含一种使互连紧固于第一衬底和第二衬底的方法，其中所述互连是非焊料金属材料，此方法包含下列步骤：
(a)对所述互连的第一末端进行助熔处理，
(b)将所述互连的经助熔处理过的所述第一末端置于所述第一衬底上至少具有一种第一焊料的第一焊点上，
(c)在靠近所述经助熔处理过的末端和所述第一焊点处，使温度由室温升高到约100～300℃，并在所述第一焊料回流后，将所述互连降低到室温，
(d)对所述互连的第二末端进行助熔处理，
(e)将所述互连的经助熔处理过的所述第二末端置于所述第二衬底上至少具有一种第二焊料的第二焊点上，
(f)在靠近所述经助熔处理过的末端和所述第二焊点处，使温度由室温升高到约100～300℃，并在所述第二焊料回流后，将所述互连降低到室温，从而使所述互连紧固于所述第一衬底和所述第二衬底。
附图说明
所附权利要求叙述了被认为新颖的本发明的特点和本发明特有的要素。附图只是为了说明的目的，并未按比例绘出。而且，附图中相似的参考号表示相似的零件。然而，参照结合附图的详细描述，可以最好地理解本发明本身的组织和操作方法。其中：
图1示出了本发明的优选实施方案。
图2示出了本发明的另一优选实施方案。
具体实施方式
图1示出了本发明的优选实施方案，其中用至少一种高熔点焊料材料14，把诸如铜柱的非焊料金属柱23，焊接到芯片载体或衬底10上的I/O(输入/输出)焊点12，得到高密度的柱结构。
图2示出了本发明的另一优选实施方案，其中用至少一种低温焊料材料24，把图1的高密度柱结构焊接到诸如印刷电路板(PCB)20的第二层封装件或衬底20上的I/O(输入/输出)焊点22。此非焊料金属柱23，例如铜柱，也能够具有至少一个金属薄镀层21。通常，金属镀层21是一非常薄的镀层，且优选的金属材料是锡。然而，仅仅作为几个例子，也能够使用另外的金属镀层21，例如镍、具有额外的一层或更多层锡的镍、锡-银、锡-金及其合金。
如前所述，本发明基本上利用一种包括非焊料金属柱23的结构，例如柔性铜芯柱组成的阵列，以便用高熔点焊料材料14(如高熔点焊料合金)和低熔点焊料合金24，将芯片载体10连接到有机板或电路板20。此铜柱最好被充分退火，使其具有高延伸率，从而在产品寿命内能够吸收连接到有机板的芯片载体通常经历的多次热疲劳周期。所使用的低和高熔点焊料合金最好与铜芯柱兼容。用来紧固铜柱的焊料合金可以由含铅的焊料合金或无铅的焊料合金制成。
包括高密度非焊料金属柱23的连接，最好是包括完全退火的铜柱部分，其延伸率大于约30％。可选择的涂层21，例如锡、锡/银、镍或镍/锡镀层21，其厚度最好在大约0.5～4.0μm之间。然而，非焊料金属柱23的直径和长度，及其相关的焊料连接带的几何尺寸都能够根据模型功能环境中的具体应力条件而预先定制。对于大多数应用，非焊料金属柱23的直径最好为大约0.2～0.5mm。这是间距约为0.5～1.27mm的非焊料柱阵列的典型直径。
为了把非焊料金属柱23连接到印刷电路板或衬底20或芯片载体10，可以使用一种高熔点焊料，例如铅/锡(铅浓度约为70～90％重量比)或掺有钯的低共熔铅锡。
对于无铅系统，作为几个例子，高熔点焊料材料14的焊料可以选自：锡/锑(锡约为55～95％重量比)，锡/银，锡/银/铜(银和铜约为0.5～3.0％重量比)，锡/银/铋(银约为2.0～4.5％重量比，而铋约为3.5～7.5％重量比)，锡/银/铜(银约为2.0～4.5％重量比，而铜约为0.5～3.0％重量比)。
对于印刷电路板或卡板20，通常习惯于使用低共熔铅/锡焊料24。然而，对于无铅系统，作为几个例子，焊料24可以选自：锡/锑(锡约为55～95％重量比)，锡/银，锡/银/铜(银和铜约为0.5～3.0％重量比)，锡/银/铋(银约为2.0～4.5％重量比，而铋约为3.5～7.5％重量比)，锡/银/铜(银约为2.0～4.5％重量比，而铜约为0.5～3.0％重量比)，锡/锌(锡约为91％重量比)，锡/铋(锡约为42％重量比)。
为了优化其应力特性，可以对非焊料金属柱23的纯铜芯进行退火，并可选地涂覆镍(比如说约为0.5～4.0μm)，随之以薄镀锡(比如说约为0.2～0.5μm)。
为了将非焊料金属柱23固定到I/O焊点12，可以使用95/5比例的锡/锑或锡/银(银约为3～5％重量比)，其熔点约为220～240℃。这应该是高温无铅焊料连接。
为了将非焊料金属柱23固定到印刷电路板的I/O焊点22，可以使用48/52比例的锡/铟或者43/57比例的锡/铋，其熔点约为120～140℃。这应该是低温无铅焊料连接。
在卡板组装过程中，这种形式的焊料连接分层明显地将I/O高熔点焊料材料14的连接的回流风险减到了最小。
虽然结合具体的优选实施方案对本发明作了确切的描述，但显然，对于本领域的技术人员，参照上述的描述，许多变通、修正和改变是显而易见的。因此，所期望的是所附权利要求包括了本发明构思与范围内的任何这种变通、修正和改变。

Claims (12)

1.芯片载体衬底上的第一焊点与第二衬底上的第二焊点之间的一种金属电互连结构，包括：
具有第一端和第二端的导电柱，所述导电柱由非焊料金属材料构成，所述第一端连接到所述芯片载体衬底上的第一焊点，所述第二端连接到所述第二衬底上的第二焊点；
其中，所述导电柱的第一端通过第一焊料连接到所述芯片载体衬底上的第一焊点，所述导电柱的第二端通过第二焊料连接到所述第二衬底上的第二焊点；
其中，所述第一焊料具有第一熔点，所述第二焊料的熔点比第一焊料的熔点低。
2.权利要求1的互连结构，其特征是，其中至少50％以上的所述导电柱由非焊料金属材料构成。
3.权利要求1的互连结构，其特征是，其中所述导电柱由铜、纯铜、或完全退火的铜制成。
4.权利要求1的互连结构，其特征是，其中所述导电柱的材料选自铜、镍及其合金、以及锡为20％重量比的铜-锡合金。
5.权利要求1的互连结构，其特征是，其中所述导电柱的直径为0.2～0.5mm。
6.权利要求1的互连结构，其特征是，其中所述芯片载体衬底是陶瓷衬底。
7.权利要求1的互连结构，其特征是，其中所述第二衬底是有机板。
8.权利要求1的互连结构，其特征是，其中至少部分所述导电柱具有至少一个由至少一种材料组成的涂层。
9.权利要求1的互连结构，其特征是，其中至少部分所述导电柱具有至少一个由至少一种材料组成的涂层，且其中所述至少一种材料选自铜、镍、银、锡及其合金。
10.权利要求8的互连结构，其特征是，其中所述涂层的厚度为0.5～4.0μm。
11.权利要求1的互连结构，其特征是，其中所述导电柱是利用软焊或硬焊的方法被紧固于所述芯片载体衬底的。
12.权利要求1的互连结构，其特征是，其中所述第二衬底是印刷电路板，所述导电柱是利用软焊或硬焊的方法被紧固于所述印刷电路板的。
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Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6503088B2 (en) * 2000-12-15 2003-01-07 Di/Dt, Inc. I-channel surface-mount connector with extended flanges
US6750396B2 (en) * 2000-12-15 2004-06-15 Di/Dt, Inc. I-channel surface-mount connector
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6892925B2 (en) 2002-09-18 2005-05-17 International Business Machines Corporation Solder hierarchy for lead free solder joint
US7223633B2 (en) 2002-11-27 2007-05-29 Intel Corporation Method for solder crack deflection
US6854636B2 (en) * 2002-12-06 2005-02-15 International Business Machines Corporation Structure and method for lead free solder electronic package interconnections
US6917113B2 (en) * 2003-04-24 2005-07-12 International Business Machines Corporatiion Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly
US7390735B2 (en) 2005-01-07 2008-06-24 Teledyne Licensing, Llc High temperature, stable SiC device interconnects and packages having low thermal resistance
US20060186175A1 (en) * 2005-02-18 2006-08-24 Kay Lawrence C Metal containers for solder paste
JP5696173B2 (ja) * 2005-08-12 2015-04-08 アンタヤ・テクノロジーズ・コープ はんだ組成物
US7754343B2 (en) * 2005-08-17 2010-07-13 Oracle America, Inc. Ternary alloy column grid array
US20070059548A1 (en) * 2005-08-17 2007-03-15 Sun Microsystems, Inc. Grid array package using tin/silver columns
WO2007023284A1 (en) * 2005-08-24 2007-03-01 Fry's Metals Inc. Reducing joint embrittlement in lead-free soldering processes
US7292450B2 (en) * 2006-01-31 2007-11-06 Microsoft Corporation High density surface mount part array layout and assembly technique
WO2007120418A2 (en) * 2006-03-13 2007-10-25 Nextwire Systems, Inc. Electronic multilingual numeric and language learning tool
TW200908824A (en) * 2007-08-13 2009-02-16 Delta Electronics Inc Surface mount connector and circuit board assembly having same
JP5763887B2 (ja) 2010-02-24 2015-08-12 千住金属工業株式会社 銅カラム及びその製造方法
CN102157481B (zh) * 2011-03-31 2012-07-04 无锡中微高科电子有限公司 用于集成电路封装的应力应变焊柱
TWI464031B (zh) * 2011-12-14 2014-12-11 Univ Yuan Ze 抑制柯肯達爾孔洞形成於銲料與銅銲墊之間的方法
JP5854137B2 (ja) * 2012-06-22 2016-02-09 株式会社村田製作所 電子部品モジュール
US9786634B2 (en) * 2015-07-17 2017-10-10 National Taiwan University Interconnection structures and methods for making the same
WO2017020295A1 (en) * 2015-08-06 2017-02-09 Telefonaktiebolaget Lm Ericsson (Publ) Surface mount contact, electronic device assembly, and test probe pin tool
US9806052B2 (en) 2015-09-15 2017-10-31 Qualcomm Incorporated Semiconductor package interconnect
US9648729B1 (en) * 2015-11-20 2017-05-09 Raytheon Company Stress reduction interposer for ceramic no-lead surface mount electronic device
US10586782B2 (en) 2017-07-01 2020-03-10 International Business Machines Corporation Lead-free solder joining of electronic structures
JP7259942B2 (ja) * 2019-03-29 2023-04-18 株式会社村田製作所 樹脂多層基板、および樹脂多層基板の製造方法
US10477698B1 (en) * 2019-04-17 2019-11-12 Topline Corporation Solder columns and methods for making same
CN110176437B (zh) * 2019-05-31 2020-11-03 合肥圣达电子科技实业有限公司 一种窄间距陶瓷接线柱及其制备方法
US10937752B1 (en) 2020-08-03 2021-03-02 Topline Corporation Lead free solder columns and methods for making same
CN113921406B (zh) * 2021-10-11 2024-10-08 山东凯能电子科技有限公司 一种提高cga器件无模具植柱连接质量的方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59155950A (ja) 1983-02-25 1984-09-05 Shinko Electric Ind Co Ltd 半導体装置用セラミックパッケージ
US4705205A (en) * 1983-06-30 1987-11-10 Raychem Corporation Chip carrier mounting device
US4778733A (en) 1986-07-03 1988-10-18 Engelhard Corporation Low toxicity corrosion resistant solder
US4806309A (en) 1988-01-05 1989-02-21 Willard Industries, Inc. Tin base lead-free solder composition containing bismuth, silver and antimony
US4930001A (en) * 1989-03-23 1990-05-29 Hughes Aircraft Company Alloy bonded indium bumps and methods of processing same
US4914814A (en) * 1989-05-04 1990-04-10 International Business Machines Corporation Process of fabricating a circuit package
US5324892A (en) 1992-08-07 1994-06-28 International Business Machines Corporation Method of fabricating an electronic interconnection
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
US5405577A (en) 1993-04-29 1995-04-11 Seelig; Karl F. Lead-free and bismuth-free tin alloy solder composition
US5328660A (en) 1993-06-16 1994-07-12 International Business Machines Corporation Lead-free, high temperature, tin based multi-component solder
US5411703A (en) 1993-06-16 1995-05-02 International Business Machines Corporation Lead-free, tin, antimony, bismtuh, copper solder alloy
US5527628A (en) 1993-07-20 1996-06-18 Iowa State University Research Foudation, Inc. Pb-free Sn-Ag-Cu ternary eutectic solder
US5435968A (en) 1994-01-21 1995-07-25 Touchstone, Inc. A lead-free solder composition
JP3232963B2 (ja) 1994-10-11 2001-11-26 株式会社日立製作所 有機基板接続用鉛レスはんだ及びそれを用いた実装品
JP2805595B2 (ja) 1994-11-02 1998-09-30 三井金属鉱業株式会社 鉛無含有半田合金
US5484964A (en) * 1995-02-06 1996-01-16 Dawson, Deceased; Peter F. Surface mounting pin grid arrays
JPH0970687A (ja) 1995-07-04 1997-03-18 Toyota Central Res & Dev Lab Inc 無鉛はんだ合金
WO1997047426A1 (en) 1996-06-12 1997-12-18 International Business Machines Corporation Lead-free, high tin ternary solder alloy of tin, silver, and indium
JPH1071488A (ja) 1996-08-29 1998-03-17 Mitsui Mining & Smelting Co Ltd 錫−銀系半田合金
US5863493A (en) 1996-12-16 1999-01-26 Ford Motor Company Lead-free solder compositions
US6016947A (en) * 1997-10-21 2000-01-25 International Business Machines Corporation Non-destructive low melt test for off-composition solder
US6053394A (en) * 1998-01-13 2000-04-25 International Business Machines Corporation Column grid array substrate attachment with heat sink stress relief
US5938862A (en) 1998-04-03 1999-08-17 Delco Electronics Corporation Fatigue-resistant lead-free alloy
JP3715438B2 (ja) * 1998-07-21 2005-11-09 富士通株式会社 電子装置およびその製造方法

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