CN1228697C - 同步跳跃模式及初始化时钟转送接口的系统及方法 - Google Patents
同步跳跃模式及初始化时钟转送接口的系统及方法 Download PDFInfo
- Publication number
- CN1228697C CN1228697C CNB018164536A CN01816453A CN1228697C CN 1228697 C CN1228697 C CN 1228697C CN B018164536 A CNB018164536 A CN B018164536A CN 01816453 A CN01816453 A CN 01816453A CN 1228697 C CN1228697 C CN 1228697C
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- CN
- China
- Prior art keywords
- clock
- signal
- clock signal
- reset
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000001360 synchronised effect Effects 0.000 claims abstract description 43
- 230000005540 biological transmission Effects 0.000 claims description 10
- 230000004044 response Effects 0.000 claims description 6
- 238000012546 transfer Methods 0.000 abstract description 20
- 238000001514 detection method Methods 0.000 abstract 1
- 238000013519 translation Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 230000000712 assembly Effects 0.000 description 4
- 238000000429 assembly Methods 0.000 description 4
- 230000004087 circulation Effects 0.000 description 4
- 230000009191 jumping Effects 0.000 description 4
- 238000012937 correction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000003708 edge detection Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 206010011968 Decreased immune responsiveness Diseases 0.000 description 1
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000001839 systemic circulation Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/005—Correction by an elastic buffer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/637,710 | 2000-08-11 | ||
US09/637,710 US6748039B1 (en) | 2000-08-11 | 2000-08-11 | System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1466711A CN1466711A (zh) | 2004-01-07 |
CN1228697C true CN1228697C (zh) | 2005-11-23 |
Family
ID=24557059
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB018164536A Expired - Fee Related CN1228697C (zh) | 2000-08-11 | 2001-05-09 | 同步跳跃模式及初始化时钟转送接口的系统及方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6748039B1 (zh) |
EP (1) | EP1309908A1 (zh) |
JP (1) | JP2004506974A (zh) |
KR (1) | KR100804286B1 (zh) |
CN (1) | CN1228697C (zh) |
AU (1) | AU2001263015A1 (zh) |
TW (1) | TW587206B (zh) |
WO (1) | WO2002014992A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103988191A (zh) * | 2011-12-22 | 2014-08-13 | 英特尔公司 | 边带初始化 |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7161999B2 (en) * | 2002-01-02 | 2007-01-09 | Intel Corporation | Synchronizing data or signal transfer across clocked logic domains |
JP4176720B2 (ja) * | 2002-09-30 | 2008-11-05 | 富士通株式会社 | 同期制御装置および同期制御方法 |
US7047432B1 (en) * | 2003-01-17 | 2006-05-16 | Cisco Technology, Inc. | Method and system for synchronizing output from differently timed circuits |
WO2004066092A2 (en) * | 2003-01-23 | 2004-08-05 | University Of Rochester | Multiple clock domain microprocessor |
KR100522433B1 (ko) * | 2003-04-29 | 2005-10-20 | 주식회사 하이닉스반도체 | 도메인 크로싱 회로 |
DE10342255A1 (de) | 2003-09-11 | 2005-04-07 | Bts Media Solutions Gmbh | Schaltung zur Ansteuerung eines Speichers |
US7319729B2 (en) * | 2003-09-29 | 2008-01-15 | International Business Machines Corporation | Asynchronous interface methods and apparatus |
US7657689B1 (en) * | 2003-10-07 | 2010-02-02 | Altera Corporation | Methods and apparatus for handling reset events in a bus bridge |
US7231539B1 (en) * | 2004-06-03 | 2007-06-12 | Integrated Device Technology, Inc. | Reset circuit for resetting two clock domains |
EP1615106A1 (en) * | 2004-07-05 | 2006-01-11 | STMicroelectronics Limited | Reset in a system-on-chip circuit |
US20060146967A1 (en) * | 2004-12-31 | 2006-07-06 | Adarsh Panikkar | Keep-out asynchronous clock alignment scheme |
CN101297255B (zh) * | 2005-10-26 | 2011-11-02 | 英特尔公司 | 可检测变化的集群体系结构 |
US7664213B2 (en) * | 2005-11-22 | 2010-02-16 | Sun Microsystems, Inc. | Clock alignment detection from single reference |
US8132041B2 (en) * | 2007-12-20 | 2012-03-06 | Qualcomm Incorporated | Method and apparatus for generating or utilizing one or more cycle-swallowed clock signals |
WO2009105095A1 (en) * | 2008-02-20 | 2009-08-27 | Hewlett-Packard Development Company, L.P. | Redriver with two reference clocks and method of operation thereof |
US7733130B2 (en) * | 2008-03-06 | 2010-06-08 | Oracle America, Inc. | Skew tolerant communication between ratioed synchronous clocks |
WO2010132943A1 (en) | 2009-05-20 | 2010-11-25 | Chronologic Pty. Ltd. | Jitter reduction method and apparatus for distributed synchronised clock architecture |
GB2482303A (en) * | 2010-07-28 | 2012-02-01 | Gnodal Ltd | Modifying read patterns for a FIFO between clock domains |
KR101647002B1 (ko) * | 2011-12-22 | 2016-08-10 | 인텔 코포레이션 | 결정론적 클록 크로싱 |
US8972761B2 (en) * | 2012-02-01 | 2015-03-03 | Lsi Corporation | Systems and methods for idle clock insertion based power control |
US8786332B1 (en) | 2013-01-17 | 2014-07-22 | Apple Inc. | Reset extender for divided clock domains |
CN104076263B (zh) * | 2013-03-28 | 2017-03-15 | 致茂电子(苏州)有限公司 | 半导体自动测试设备的时间量测模块及方法 |
US9876709B1 (en) * | 2014-08-28 | 2018-01-23 | Xilinx, Inc. | Alignment detection in a multi-lane network interface |
US9727306B2 (en) | 2014-10-07 | 2017-08-08 | Stmicroelectronics S.R.L. | Bi-synchronous electronic device with burst indicator and related methods |
US10484165B2 (en) * | 2017-12-19 | 2019-11-19 | Stmicroelectronics International N.V. | Latency buffer circuit with adaptable time shift |
CN113472347B (zh) * | 2021-07-01 | 2024-04-05 | 北京兆芯电子科技有限公司 | 电子装置以及采样方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4007441A (en) * | 1975-05-29 | 1977-02-08 | Burroughs Corporation | Method of data communications in a heterogenous environment |
DE2853523C2 (de) | 1978-12-12 | 1981-10-01 | Ibm Deutschland Gmbh, 7000 Stuttgart | Dezentrale Erzeugung von Taktsteuersignalen |
JPS63110811A (ja) | 1986-10-28 | 1988-05-16 | Mitsubishi Electric Corp | クロツクジエネレ−タ |
JPH01251738A (ja) | 1988-03-31 | 1989-10-06 | Toshiba Corp | スタンダードセル |
JPH0642196B2 (ja) | 1988-06-09 | 1994-06-01 | 株式会社東芝 | 倍密度走査用ラインメモリ |
US5224129A (en) | 1990-10-31 | 1993-06-29 | Tektronix, Inc. | Method of synchronizing signals of a pulse generator |
US5448715A (en) | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
US5689689A (en) | 1992-12-17 | 1997-11-18 | Tandem Computers Incorporated | Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal |
US5434996A (en) * | 1993-12-28 | 1995-07-18 | Intel Corporation | Synchronous/asynchronous clock net with autosense |
US5768529A (en) | 1995-05-05 | 1998-06-16 | Silicon Graphics, Inc. | System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers |
US5909563A (en) * | 1996-09-25 | 1999-06-01 | Philips Electronics North America Corporation | Computer system including an interface for transferring data between two clock domains |
JP3019814B2 (ja) * | 1997-09-18 | 2000-03-13 | 日本電気株式会社 | クロックリカバリ回路 |
US6049887A (en) * | 1997-12-04 | 2000-04-11 | Intel Corporation | Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio |
US5961649A (en) | 1997-12-04 | 1999-10-05 | Intel Corporation | Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio |
KR100255664B1 (ko) | 1997-12-29 | 2000-05-01 | 윤종용 | 반도체 집적회로의 클락 포워딩 회로 및 클락포워딩 방법 |
JP4130006B2 (ja) * | 1998-04-28 | 2008-08-06 | 富士通株式会社 | 半導体装置 |
US6081904A (en) | 1998-04-30 | 2000-06-27 | International Business Machines Corporation | Method for insuring data integrity during transfers |
DE19820572A1 (de) * | 1998-05-08 | 1999-11-11 | Alcatel Sa | Desynchronisiereinrichtung für ein synchrones digitales Nachrichtenübertragungssystem |
US6681272B1 (en) * | 1999-10-20 | 2004-01-20 | Applied Micro Circuits Corporation | Elastic store circuit with static phase offset |
US6424688B1 (en) * | 1999-10-27 | 2002-07-23 | Advanced Micro Devices, Inc. | Method to transfer data in a system with multiple clock domains using clock skipping techniques |
US6581164B1 (en) * | 2000-01-03 | 2003-06-17 | Conexant Systems, Inc. | System for adjusting clock frequency based upon amount of unread data stored in sequential memory when reading a new line of data within a field of data |
-
2000
- 2000-08-11 US US09/637,710 patent/US6748039B1/en not_active Expired - Fee Related
-
2001
- 2001-05-09 AU AU2001263015A patent/AU2001263015A1/en not_active Abandoned
- 2001-05-09 CN CNB018164536A patent/CN1228697C/zh not_active Expired - Fee Related
- 2001-05-09 KR KR1020037002015A patent/KR100804286B1/ko not_active IP Right Cessation
- 2001-05-09 WO PCT/US2001/014902 patent/WO2002014992A1/en active Application Filing
- 2001-05-09 EP EP01937262A patent/EP1309908A1/en not_active Withdrawn
- 2001-05-09 JP JP2002520056A patent/JP2004506974A/ja active Pending
- 2001-06-26 TW TW090115363A patent/TW587206B/zh not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103988191A (zh) * | 2011-12-22 | 2014-08-13 | 英特尔公司 | 边带初始化 |
CN103988191B (zh) * | 2011-12-22 | 2017-05-17 | 英特尔公司 | 边带初始化 |
Also Published As
Publication number | Publication date |
---|---|
TW587206B (en) | 2004-05-11 |
US6748039B1 (en) | 2004-06-08 |
JP2004506974A (ja) | 2004-03-04 |
EP1309908A1 (en) | 2003-05-14 |
WO2002014992A1 (en) | 2002-02-21 |
AU2001263015A1 (en) | 2002-02-25 |
CN1466711A (zh) | 2004-01-07 |
KR20030064379A (ko) | 2003-07-31 |
KR100804286B1 (ko) | 2008-02-18 |
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C06 | Publication | ||
PB01 | Publication | ||
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SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: GLOBALFOUNDRIES Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC. Effective date: 20100705 |
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C41 | Transfer of patent application or patent right or utility model | ||
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Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA, THE UNITED STATES TO: CAYMAN ISLANDS, BRITISH |
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TR01 | Transfer of patent right |
Effective date of registration: 20100705 Address after: Grand Cayman, Cayman Islands Patentee after: Globalfoundries Semiconductor Inc. Address before: American California Patentee before: Advanced Micro Devices Inc. |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20051123 Termination date: 20160509 |
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CF01 | Termination of patent right due to non-payment of annual fee |