AU2001263015A1 - System and method for synchronizing a skip pattern and initializing a clock forwarding interface in multiple-clock system - Google Patents

System and method for synchronizing a skip pattern and initializing a clock forwarding interface in multiple-clock system

Info

Publication number
AU2001263015A1
AU2001263015A1 AU2001263015A AU6301501A AU2001263015A1 AU 2001263015 A1 AU2001263015 A1 AU 2001263015A1 AU 2001263015 A AU2001263015 A AU 2001263015A AU 6301501 A AU6301501 A AU 6301501A AU 2001263015 A1 AU2001263015 A1 AU 2001263015A1
Authority
AU
Australia
Prior art keywords
clock
initializing
synchronizing
forwarding interface
skip pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001263015A
Other languages
English (en)
Inventor
Michael E. Bates
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001263015A1 publication Critical patent/AU2001263015A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
AU2001263015A 2000-08-11 2001-05-09 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in multiple-clock system Abandoned AU2001263015A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/637,710 US6748039B1 (en) 2000-08-11 2000-08-11 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system
US09637710 2000-08-11
PCT/US2001/014902 WO2002014992A1 (en) 2000-08-11 2001-05-09 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system

Publications (1)

Publication Number Publication Date
AU2001263015A1 true AU2001263015A1 (en) 2002-02-25

Family

ID=24557059

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001263015A Abandoned AU2001263015A1 (en) 2000-08-11 2001-05-09 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in multiple-clock system

Country Status (8)

Country Link
US (1) US6748039B1 (zh)
EP (1) EP1309908A1 (zh)
JP (1) JP2004506974A (zh)
KR (1) KR100804286B1 (zh)
CN (1) CN1228697C (zh)
AU (1) AU2001263015A1 (zh)
TW (1) TW587206B (zh)
WO (1) WO2002014992A1 (zh)

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US7319729B2 (en) * 2003-09-29 2008-01-15 International Business Machines Corporation Asynchronous interface methods and apparatus
US7657689B1 (en) * 2003-10-07 2010-02-02 Altera Corporation Methods and apparatus for handling reset events in a bus bridge
US7231539B1 (en) * 2004-06-03 2007-06-12 Integrated Device Technology, Inc. Reset circuit for resetting two clock domains
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US20060146967A1 (en) * 2004-12-31 2006-07-06 Adarsh Panikkar Keep-out asynchronous clock alignment scheme
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US7664213B2 (en) * 2005-11-22 2010-02-16 Sun Microsystems, Inc. Clock alignment detection from single reference
US8132041B2 (en) * 2007-12-20 2012-03-06 Qualcomm Incorporated Method and apparatus for generating or utilizing one or more cycle-swallowed clock signals
WO2009105095A1 (en) * 2008-02-20 2009-08-27 Hewlett-Packard Development Company, L.P. Redriver with two reference clocks and method of operation thereof
US7733130B2 (en) * 2008-03-06 2010-06-08 Oracle America, Inc. Skew tolerant communication between ratioed synchronous clocks
WO2010132943A1 (en) 2009-05-20 2010-11-25 Chronologic Pty. Ltd. Jitter reduction method and apparatus for distributed synchronised clock architecture
GB2482303A (en) * 2010-07-28 2012-02-01 Gnodal Ltd Modifying read patterns for a FIFO between clock domains
KR101647002B1 (ko) * 2011-12-22 2016-08-10 인텔 코포레이션 결정론적 클록 크로싱
DE112011106026B4 (de) 2011-12-22 2023-01-05 Intel Corporation Vorrichtung, Tablet-Computer und System
US8972761B2 (en) * 2012-02-01 2015-03-03 Lsi Corporation Systems and methods for idle clock insertion based power control
US8786332B1 (en) 2013-01-17 2014-07-22 Apple Inc. Reset extender for divided clock domains
CN104076263B (zh) * 2013-03-28 2017-03-15 致茂电子(苏州)有限公司 半导体自动测试设备的时间量测模块及方法
US9876709B1 (en) * 2014-08-28 2018-01-23 Xilinx, Inc. Alignment detection in a multi-lane network interface
US9727306B2 (en) 2014-10-07 2017-08-08 Stmicroelectronics S.R.L. Bi-synchronous electronic device with burst indicator and related methods
US10484165B2 (en) * 2017-12-19 2019-11-19 Stmicroelectronics International N.V. Latency buffer circuit with adaptable time shift
CN113472347B (zh) * 2021-07-01 2024-04-05 北京兆芯电子科技有限公司 电子装置以及采样方法

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Also Published As

Publication number Publication date
TW587206B (en) 2004-05-11
US6748039B1 (en) 2004-06-08
JP2004506974A (ja) 2004-03-04
EP1309908A1 (en) 2003-05-14
WO2002014992A1 (en) 2002-02-21
CN1228697C (zh) 2005-11-23
CN1466711A (zh) 2004-01-07
KR20030064379A (ko) 2003-07-31
KR100804286B1 (ko) 2008-02-18

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