AU2001263015A1 - System and method for synchronizing a skip pattern and initializing a clock forwarding interface in multiple-clock system - Google Patents

System and method for synchronizing a skip pattern and initializing a clock forwarding interface in multiple-clock system

Info

Publication number
AU2001263015A1
AU2001263015A1 AU2001263015A AU6301501A AU2001263015A1 AU 2001263015 A1 AU2001263015 A1 AU 2001263015A1 AU 2001263015 A AU2001263015 A AU 2001263015A AU 6301501 A AU6301501 A AU 6301501A AU 2001263015 A1 AU2001263015 A1 AU 2001263015A1
Authority
AU
Australia
Prior art keywords
clock
initializing
synchronizing
forwarding interface
skip pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001263015A
Other languages
English (en)
Inventor
Michael E. Bates
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001263015A1 publication Critical patent/AU2001263015A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
AU2001263015A 2000-08-11 2001-05-09 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in multiple-clock system Abandoned AU2001263015A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/637,710 US6748039B1 (en) 2000-08-11 2000-08-11 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system
US09637710 2000-08-11
PCT/US2001/014902 WO2002014992A1 (en) 2000-08-11 2001-05-09 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system

Publications (1)

Publication Number Publication Date
AU2001263015A1 true AU2001263015A1 (en) 2002-02-25

Family

ID=24557059

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001263015A Abandoned AU2001263015A1 (en) 2000-08-11 2001-05-09 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in multiple-clock system

Country Status (8)

Country Link
US (1) US6748039B1 (zh)
EP (1) EP1309908A1 (zh)
JP (1) JP2004506974A (zh)
KR (1) KR100804286B1 (zh)
CN (1) CN1228697C (zh)
AU (1) AU2001263015A1 (zh)
TW (1) TW587206B (zh)
WO (1) WO2002014992A1 (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7161999B2 (en) * 2002-01-02 2007-01-09 Intel Corporation Synchronizing data or signal transfer across clocked logic domains
WO2004031926A1 (ja) * 2002-09-30 2004-04-15 Fujitsu Limited 同期制御装置および同期制御方法
US7047432B1 (en) * 2003-01-17 2006-05-16 Cisco Technology, Inc. Method and system for synchronizing output from differently timed circuits
US7089443B2 (en) * 2003-01-23 2006-08-08 University Of Rochester Multiple clock domain microprocessor
KR100522433B1 (ko) * 2003-04-29 2005-10-20 주식회사 하이닉스반도체 도메인 크로싱 회로
DE10342255A1 (de) 2003-09-11 2005-04-07 Bts Media Solutions Gmbh Schaltung zur Ansteuerung eines Speichers
US7319729B2 (en) * 2003-09-29 2008-01-15 International Business Machines Corporation Asynchronous interface methods and apparatus
US7657689B1 (en) * 2003-10-07 2010-02-02 Altera Corporation Methods and apparatus for handling reset events in a bus bridge
US7231539B1 (en) * 2004-06-03 2007-06-12 Integrated Device Technology, Inc. Reset circuit for resetting two clock domains
EP1615106A1 (en) * 2004-07-05 2006-01-11 STMicroelectronics Limited Reset in a system-on-chip circuit
US20060146967A1 (en) * 2004-12-31 2006-07-06 Adarsh Panikkar Keep-out asynchronous clock alignment scheme
KR100971806B1 (ko) * 2005-10-26 2010-07-22 인텔 코오퍼레이션 변화를 탐지하는 클러스터 아키텍처
US7664213B2 (en) * 2005-11-22 2010-02-16 Sun Microsystems, Inc. Clock alignment detection from single reference
US8132041B2 (en) * 2007-12-20 2012-03-06 Qualcomm Incorporated Method and apparatus for generating or utilizing one or more cycle-swallowed clock signals
US8166334B2 (en) * 2008-02-20 2012-04-24 Hewlett-Packard Development Company, L.P. Redriver with two reference clocks and method of operation thereof
US7733130B2 (en) * 2008-03-06 2010-06-08 Oracle America, Inc. Skew tolerant communication between ratioed synchronous clocks
JP5575229B2 (ja) * 2009-05-20 2014-08-20 クロノロジック プロプライエタリー リミテッド 分散型の同期されたクロックアーキテクチャのためのジッタ低減方法およびジッタ低減装置
GB2482303A (en) * 2010-07-28 2012-02-01 Gnodal Ltd Modifying read patterns for a FIFO between clock domains
US9274544B2 (en) 2011-12-22 2016-03-01 Intel Corporation Sideband initialization
US9285826B2 (en) * 2011-12-22 2016-03-15 Intel Corporation Deterministic clock crossing
US8972761B2 (en) * 2012-02-01 2015-03-03 Lsi Corporation Systems and methods for idle clock insertion based power control
US8786332B1 (en) 2013-01-17 2014-07-22 Apple Inc. Reset extender for divided clock domains
CN104076263B (zh) * 2013-03-28 2017-03-15 致茂电子(苏州)有限公司 半导体自动测试设备的时间量测模块及方法
US9876709B1 (en) * 2014-08-28 2018-01-23 Xilinx, Inc. Alignment detection in a multi-lane network interface
US9727306B2 (en) 2014-10-07 2017-08-08 Stmicroelectronics S.R.L. Bi-synchronous electronic device with burst indicator and related methods
US10484165B2 (en) * 2017-12-19 2019-11-19 Stmicroelectronics International N.V. Latency buffer circuit with adaptable time shift
CN113472347B (zh) * 2021-07-01 2024-04-05 北京兆芯电子科技有限公司 电子装置以及采样方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4007441A (en) * 1975-05-29 1977-02-08 Burroughs Corporation Method of data communications in a heterogenous environment
DE2853523C2 (de) 1978-12-12 1981-10-01 Ibm Deutschland Gmbh, 7000 Stuttgart Dezentrale Erzeugung von Taktsteuersignalen
JPS63110811A (ja) 1986-10-28 1988-05-16 Mitsubishi Electric Corp クロツクジエネレ−タ
JPH01251738A (ja) 1988-03-31 1989-10-06 Toshiba Corp スタンダードセル
JPH0642196B2 (ja) 1988-06-09 1994-06-01 株式会社東芝 倍密度走査用ラインメモリ
US5224129A (en) 1990-10-31 1993-06-29 Tektronix, Inc. Method of synchronizing signals of a pulse generator
US5448715A (en) 1992-07-29 1995-09-05 Hewlett-Packard Company Dual clock domain interface between CPU and memory bus
US6233702B1 (en) 1992-12-17 2001-05-15 Compaq Computer Corporation Self-checked, lock step processor pairs
US5434996A (en) * 1993-12-28 1995-07-18 Intel Corporation Synchronous/asynchronous clock net with autosense
US5768529A (en) 1995-05-05 1998-06-16 Silicon Graphics, Inc. System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers
US5909563A (en) 1996-09-25 1999-06-01 Philips Electronics North America Corporation Computer system including an interface for transferring data between two clock domains
JP3019814B2 (ja) * 1997-09-18 2000-03-13 日本電気株式会社 クロックリカバリ回路
US5961649A (en) 1997-12-04 1999-10-05 Intel Corporation Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio
US6049887A (en) * 1997-12-04 2000-04-11 Intel Corporation Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio
KR100255664B1 (ko) 1997-12-29 2000-05-01 윤종용 반도체 집적회로의 클락 포워딩 회로 및 클락포워딩 방법
JP4130006B2 (ja) * 1998-04-28 2008-08-06 富士通株式会社 半導体装置
US6081904A (en) 1998-04-30 2000-06-27 International Business Machines Corporation Method for insuring data integrity during transfers
DE19820572A1 (de) * 1998-05-08 1999-11-11 Alcatel Sa Desynchronisiereinrichtung für ein synchrones digitales Nachrichtenübertragungssystem
US6681272B1 (en) * 1999-10-20 2004-01-20 Applied Micro Circuits Corporation Elastic store circuit with static phase offset
US6424688B1 (en) * 1999-10-27 2002-07-23 Advanced Micro Devices, Inc. Method to transfer data in a system with multiple clock domains using clock skipping techniques
US6581164B1 (en) * 2000-01-03 2003-06-17 Conexant Systems, Inc. System for adjusting clock frequency based upon amount of unread data stored in sequential memory when reading a new line of data within a field of data

Also Published As

Publication number Publication date
TW587206B (en) 2004-05-11
CN1228697C (zh) 2005-11-23
WO2002014992A1 (en) 2002-02-21
KR20030064379A (ko) 2003-07-31
US6748039B1 (en) 2004-06-08
JP2004506974A (ja) 2004-03-04
KR100804286B1 (ko) 2008-02-18
CN1466711A (zh) 2004-01-07
EP1309908A1 (en) 2003-05-14

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