CN1224876C - 时钟同步电路 - Google Patents

时钟同步电路 Download PDF

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Publication number
CN1224876C
CN1224876C CNB021303754A CN02130375A CN1224876C CN 1224876 C CN1224876 C CN 1224876C CN B021303754 A CNB021303754 A CN B021303754A CN 02130375 A CN02130375 A CN 02130375A CN 1224876 C CN1224876 C CN 1224876C
Authority
CN
China
Prior art keywords
pulse
delay
state
reset
reverse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB021303754A
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English (en)
Chinese (zh)
Other versions
CN1396502A (zh
Inventor
加藤光司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1396502A publication Critical patent/CN1396502A/zh
Application granted granted Critical
Publication of CN1224876C publication Critical patent/CN1224876C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
CNB021303754A 2001-07-03 2002-07-03 时钟同步电路 Expired - Fee Related CN1224876C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP202552/2001 2001-07-03
JP2001202552A JP4005779B2 (ja) 2001-07-03 2001-07-03 クロック同期回路

Publications (2)

Publication Number Publication Date
CN1396502A CN1396502A (zh) 2003-02-12
CN1224876C true CN1224876C (zh) 2005-10-26

Family

ID=19039344

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021303754A Expired - Fee Related CN1224876C (zh) 2001-07-03 2002-07-03 时钟同步电路

Country Status (3)

Country Link
US (1) US6822922B2 (enExample)
JP (1) JP4005779B2 (enExample)
CN (1) CN1224876C (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100956770B1 (ko) * 2007-12-10 2010-05-12 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 그 제어 방법
JP6399136B1 (ja) 2017-03-31 2018-10-03 オムロン株式会社 制御装置、制御プログラム、および制御システム
TWI685200B (zh) 2018-08-10 2020-02-11 華邦電子股份有限公司 同步鏡延遲電路和同步鏡延遲操作方法
US11456729B1 (en) * 2021-03-26 2022-09-27 Analog Devices, Inc. Deskew cell for delay and pulse width adjustment

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3410922B2 (ja) * 1996-04-23 2003-05-26 株式会社東芝 クロック制御回路
JP3435335B2 (ja) * 1998-03-18 2003-08-11 株式会社東芝 クロック同期遅延制御回路及び外部クロックに同期した内部クロックを用いるデバイスを含む装置
JP2000235791A (ja) * 1999-02-15 2000-08-29 Toshiba Corp クロック同期遅延制御回路
JP2001014847A (ja) * 1999-06-30 2001-01-19 Toshiba Corp クロック同期回路
JP2002109880A (ja) * 2000-09-28 2002-04-12 Toshiba Corp クロック同期回路

Also Published As

Publication number Publication date
CN1396502A (zh) 2003-02-12
JP4005779B2 (ja) 2007-11-14
US6822922B2 (en) 2004-11-23
US20030007414A1 (en) 2003-01-09
JP2003015764A (ja) 2003-01-17

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C06 Publication
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C10 Entry into substantive examination
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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20051026

Termination date: 20170703

CF01 Termination of patent right due to non-payment of annual fee