CN1195189A - 半导体器件的制造方法 - Google Patents
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Abstract
本发明的目的在于防止硅化钛层与P型杂质层的接触电阻增大、P型MOS晶体管的电流驱动能力降低,在用于形成P型源、漏区域7的第1P型杂质离子注入工序和用于激活的热处理工序之后,包括,第2P型杂质的离子注入工序;用于至少使源、漏区域部位的扩散层非晶化的第3杂质离子注入工序;形成硅化钛9的工序。由此,降低了硅化钛层与P型杂质层的接触电阻,提高了P型MOS晶体管的电流驱动能力。
Description
本发明涉及半导体器件的制造方法,特别是涉及含有金属硅化物的半导体器件的制造方法。
以下参考图6说明这种半导体器件的制造方法。
首先,如图6(A)所示,在硅(Si)半导体衬底1上选择地形成器件分隔区域2,然后通过磷(P)的离子注入形成N-阱区域3。形成栅氧化膜4,形成多晶硅的栅电极5,在栅电极5的侧壁上形成氧化膜构成的侧壁6。例如以20keV的加速能量、3E15(=3×1015)cm-2的剂量的条件,离子注入BF2离子,例如通过在氮气氛中、1000℃下的10秒热处理进行激活,形成P型源·漏区域7。
然后,如图6(B)所示,例如在30keV、3E14cm-2的条件下离子注入砷(As),由此使P型源·漏区域7和栅电极5的表面非晶态化。
然后,如图6(C)所示,通过溅射法形成钛(Ti),通过例如700℃、30秒的热处理,至少在P型源区7和栅电极5之上形成硅化钛层9,采用以1∶1∶5的比例混合的氨∶过氧化氢∶水溶液,除去未反应的钛,之后通过例如800℃、10秒的热处理进行硅化钛层9的低电阻化。
此时,在氧化膜的器件分隔区域2、侧壁6的表面不形成硅化钛。实际上,之后形成层间绝缘膜,开出接触孔,形成布线,但是这些工序与本发明的主题无直接关系,故而省略。
采用这种已有的制造方法在半导体衬底1上形成硅化钛层9时,由于P型杂质扩散层中所含的硼(B)被吸进浓度更低的硅化钛层9,所以P型杂质扩散层表面部分的硼浓度降低了。
因此,存在硅化钛层9和P型杂质扩散层的接触电阻增大,P型MOS晶体管的电流驱动能力降低这样的问题。
作为期望消除这种问题的已有方法,例如在特开平4-150019号公报中,为了即使形成硅化钛层,也可不降低P型杂质扩散层和硅化钛层界面处的硼浓度,由此抑制两层间的接触电阻,提出了以下制造方法。
图7中展示了这种已有的制造方法的工序。首先,参看图7(A),在以硅为主要成分的半导体衬底1上形成器件分隔区域2,在形成N阱区域3之后对半导体衬底1离子注入硼并进行激活,由此在半导体衬底1表面附近形成P型源·漏区域7。
然后,如图7(B)所示,使用TiCl4作为离子源,通过以30keV的注入能量、至少1E17cm-2的注入剂量注入钛离子,在P型源·漏区域7的表面附近注入钛离子。
这样,一旦注入钛离子,则成为钛离子混在含P型杂质的硅之间的状态。而且,在这种状态下,以20keV的注入能量离子注入1E15cm-2剂量的硼。
之后,一旦采用退火法进行400℃-900℃的热退火,则如图7(C)所示,在半导体衬底的部分中钛与硅反应,形成硅化钛9。
另一方面,在器件分隔区域等的氧化膜上不形成硅化钛。在钛与硅反应形成硅化钛的过程中,硅化钛中的硼向外扩散,而对于厚约50nm的硅化物层,由于硼浓度峰值深约60nm,所以即使硅化钛中的硼扩散,硅和硅化钛中的硼浓度也极高,在后续工序中,通过加热硼向硅化钛中扩散,但由于硅与硅化钛界面处的硼浓度不降低,所以可抑制硅化钛与P型杂质扩散层的接触电阻的增大。
但是,在上述特开平4-150019号公报提出的制造方法中,由于是通过离子注入形成钛,所以存在如下问题,即难以形成具有完全组成比的硅化钛、即TiSi2。TiSi2呈现C54的结构,初始薄层电阻下降为10Ω/sq以下的电阻。
能够形成这种低电阻的TiSi2仅限于通过溅射形成Ti、以最适合的条件退火的场合。
而且,如上所述,在如图6所示的通过溅射法形成钛、进行退火形成硅化钛的已有方法中,存在硅化钛层与P型杂质层的接触电阻增大、P型MOS晶体管的电流驱动能力降低这样的问题。
其理由如下,形成硅化钛时,由于P型杂质扩散层中所含的硼被吸进浓度更低的硅化钛层,所以P型杂质扩散层表面部分的硼浓度降低了。
因此,为了解决上述问题,本发明的目的在于提供一种能防止硅化钛层与P型杂质层的接触电阻增大、电流驱动能力降低,获得高速半导体器件的制造方法。
为了达到上述目的,根据本发明的半导体器件的制造方法,包括:用于形成源·漏的第1P型杂质的离子注入工序和用于激活的热处理工序,第2P型杂质的离子注入工序,用于至少使源·漏部位的扩散层非晶化的第3杂质注入工序,和形成TiSi2的工序。
根据本发明,在源·漏区域形成后、TiSi2形成前,离子注入硼。由此,TiSi2化时无扩散层中硼的吸入,与TiSi2接触部分的硅中保持高的硼浓度,可以降低接触电阻。因此,可以增加晶体管的导通电流、提高电路工作速度。
以下说明本发明的实施方式。本发明的半导体器件的制造方法,在优选的实施方式中,包括:(a)用于形成源·漏区的第1P型杂质的离子注入工序;(b)用于激活注入的离子的热处理工序(参看图1(A)),第2P型杂质的离子注入工序(参看图1(B));(c)至少使源·漏部位的扩散层非晶化的第3杂质的离子注入工序(参看图1(C));和(d)形成硅化钛(TiSi2)的工序(参看图1(D))。
在上述工序中,第1P型杂质以BF2为好。而且上述第2P型杂质以B或BF2为好。上述第3P型杂质以As为好。
本发明的优选实施方式中,上述形成TiSi2的工序(d)包括:(d-1)通过溅射法形成Ti的工序,(d-2)第1热退火工序,(d-3)通过湿法腐蚀去除未反应的Ti的工序,和(d-4)第2热退火工序。
而且,本发明的优选实施方式中,上述第2P型杂质的离子注入是通过旋转倾斜注入的。
以下,一面对上述本发明的实施方式做更详细说明,一面参照附图说明本发明的实施例。
图1(A)、(B)是展示根据本发明的半导体器件的制造方法的第1实施例的工序的剖面图。
图2(C)、(D)是展示根据本发明的半导体器件的制造方法的第1实施例的工序的剖面图。
图3(A)、(B)是展示根据本发明的半导体器件的制造方法的第2实施例的工序的剖面图。
图4(C)、(D)是展示根据本发明的半导体器件的制造方法的第2实施例的工序的剖面图。
图5是本发明第1实施例的作用效果与已有的制造方法比较的图。
图6(A)~(C)是展示已有的半导体器件制造方法的工序的剖面图。
图7(A)~(C)是展示其他已有的半导体器件制造方法的工序的剖面图。
【实施例1】
图1和图2是用于按工序说明本发明第1实施例的制造方法的剖面图。图1和图2只是为图面处置方便而分图制做的图。
首先,参看图1(A),在硅制成的半导体衬底1上选择地形成器件分隔区域2,通过磷的离子注入(注入条件例如是1003E14cm-2)形成N阱区域3,形成膜厚例如是5nm的栅氧化膜4,形成由膜厚例如是200nm的多晶硅制成的栅电极5,在栅电极5的侧壁形成氧化膜侧壁6,以例如20keV加速电压和3E15cm-2剂量的条件离子注入BF2离子,以非氧化气氛例如氮气氛中的1000℃、10秒的条件进行热处理施以激活,由此形成P型源·漏区域7。
其次,如图1(B)所示,在包含P型源·漏区域7的区域,以光刻胶8等作为掩模选择地侧向注入BF2离子。此时的离子注入条件例如是加速电压20keV,剂量1E15cm-2,注入角度0°。
然后,如图2(C)所示,以例如30keV、13E14cm-2的剂量的条件离子注入砷,由此使P型源·漏区域7的区域和栅电极5的表面非晶化。
然后,如图2(D)所示,通过溅射法形成钛,通过例如700℃下30秒的热处理,至少在P型源·漏区域7的区域和栅电极5上形成硅化钛9,采用以1∶1∶5的比例混合的氨∶过氧化氢∶水溶液,除去未反应的钛,之后通过例如800℃下10的秒热处理进行硅化钛层9的低电阻化。
此时,在氧化膜的器件分隔区域2、侧壁6的表面不形成硅化钛。实际上,之后形成层间绝缘膜,开出接触孔,形成布线,但是这些工序与本发明的主题无直接关系,故而省略。
以下,说明本发明第1实施例的作用效果。本发明的第1实施例中,由于在源·漏的杂质激活之前、TiSi2化之前,在P型源·漏区域再次注入BF2,所以硅化钛化之时即使硅中的硼被吸收,但由于硅中存在足够量的硼,硅化钛层与硅的接触电阻降低,提高了晶体管的导通电流。
本发明的第1实施例中,由于是利用溅射法形成钛,所以在硅化钛的形成中存在足够浓度的钛原子,因而获得了低电阻的硅化钛层。
图5中展示了本实施例与作为比较例参考图6说明的第1已有例和参考图7说明的第2已有例的P型MOS晶体管的导通电流进行的比较。
参看图5,根据本实施例,可以实现导通电流比第1已有例提高约5%、比第2已有例提高约8%。
其原因是由于与第1已有例相比,P型源·漏区域的硅与硅化钛之间的接触电阻降低,而且与第2已有例相比,硅化钛的薄层电阻降低。
【实施例2】
以下,参考图3和图4说明本发明的第2实施例。形成器件分隔区域、栅氧化膜、栅电极等,通过离子注入和激活形成源·漏区域,与上述第1实施例相同,所以省略其说明。图3(A)相当于上述第1实施例中的图1(A)。而且,图3和图4只是为图面处置方便而分图制做的图。
然后,如图3(B)所示,在包含P型源·漏区域7的区域,以光刻胶8作为掩模选择地离子注入硼。此时的离子注入条件例如是加速电压5keV、剂量1E15cm-2、注入角度7°~15°的旋转注入条件。
然后,如图4(C)所示,以例如30keV、3E14cm-2的剂量的条件离子注入砷,由此使P型源·漏区域7的区域和栅电极5的表面非晶化。
然后,如图4(D)所示,通过溅射法形成钛,通过例如700℃下30秒的热处理,至少在P型源·漏区域7的区域和栅电极5上形成硅化钛9,采用以1∶1∶5的比例混合的氨∶过氧化氢∶水溶液,除去未反应的钛,之后通过例如800℃下10的秒热处理进行硅化钛层9的低电阻化。实际上,之后形成层间绝缘膜,开出接触孔,形成布线,但是这些工序与本发明的主题无直接关系,故而省略。
本实施例中,由于是以倾斜角度旋转注入硼,所以与源·漏端附近的TiSi2接触的部分的硅中的硼浓度更高,具有可进一步提高P型MOS晶体管的导通电流的优点。
而且,上述实施例中,作为金属硅化物举例说明了TiSi2,但是本发明并不限于此,也可使用例如Co、Ni、Mo和Pt各金属的硅化物。
如上所述,根据本发明可实现降低TiSi2与硅的接触电阻、提高晶体管导通电流的效果。
其原因在于即使TiSi2化时硅中的硼被吸收,由于硅表面中的存在足够量的硼,所以可降低硅与TiSi2的接触电阻。
Claims (9)
1.一种半导体器件的制造方法,其特征在于包括:用于形成源·漏的第1P型杂质的离子注入工序;
用于激活注入离子的热处理工序;
第2P型杂质的离子注入工序;
用于至少使源·漏部位的扩散层非晶化的第3杂质注入工序;
形成硅化钛(TiSi2)的工序。
2.根据权利要求1的半导体器件的制造方法,其特征在于所述第1P型杂质是BF2。
3.根据权利要求1的半导体器件的制造方法,其特征在于所述第2P型杂质是B或BF2。
4.根据权利要求1的半导体器件的制造方法,其特征在于所述第2P型杂质的离子注入是倾斜旋转注入的。
5.根据权利要求1的半导体器件的制造方法,其特征在于所述第3杂质是As。
6.根据权利要求1的半导体器件的制造方法,其特征在于所述形成TiSi2的工序包括:
通过溅射法形成Ti的工序;
第1热退火工序;
通过湿法腐蚀去除未反应的Ti的工序;
第2热退火工序。
7.一种半导体器件的制造方法,其特征在于包括:
(a)在形成源·漏的区域离子注入第1P型杂质之后,进行热处理激活该离子的源·漏区形成工序;
(b)在包含所述源·漏区域的区域离子注入第2P型杂质的工序;
(c)离子注入第3杂质,至少使源·漏区域表面非晶化的的工序;
(d)通过溅射法形成金属,通过热处理形成金属硅化物的工序;
(e)通过腐蚀去除未反应的所述金属之后,通过热处理使所述金属硅化物低电阻化的工序。
8、根据权利要求7的半导体器件的制造方法,其特征在于所述金属是Co、Ni、Mo和Pt中的任一种。
9.根据权利要求7的半导体器件的制造方法,其特征在于所述工序(b)中通过倾斜旋转注入进行第2P型杂质的离子注入。
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JP09026203A JP3119190B2 (ja) | 1997-01-24 | 1997-01-24 | 半導体装置の製造方法 |
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Cited By (3)
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CN100442478C (zh) * | 2004-06-17 | 2008-12-10 | 尔必达存储器股份有限公司 | 具有多晶硅插头的半导体器件的制造方法 |
CN104838504A (zh) * | 2012-12-07 | 2015-08-12 | 三菱电机株式会社 | 半导体装置的制造方法 |
CN105280704A (zh) * | 2014-06-23 | 2016-01-27 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
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KR100341588B1 (ko) * | 1999-12-28 | 2002-06-22 | 박종섭 | 실리사이드층의 저항 및 누설전류 감소를 위한 반도체소자 제조 방법 |
US6440806B1 (en) * | 2001-04-30 | 2002-08-27 | Advanced Micro Devices, Inc. | Method for producing metal-semiconductor compound regions on semiconductor devices |
KR100620235B1 (ko) | 2004-12-29 | 2006-09-08 | 동부일렉트로닉스 주식회사 | 타이타늄 실리사이드 제조 방법 |
US20100112788A1 (en) * | 2008-10-31 | 2010-05-06 | Deepak Ramappa | Method to reduce surface damage and defects |
KR101669470B1 (ko) | 2009-10-14 | 2016-10-26 | 삼성전자주식회사 | 금속 실리사이드층을 포함하는 반도체 소자 |
JP2022032659A (ja) * | 2020-08-13 | 2022-02-25 | 東京エレクトロン株式会社 | 半導体装置の電極部及びその製造方法 |
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JP2630290B2 (ja) * | 1995-01-30 | 1997-07-16 | 日本電気株式会社 | 半導体装置の製造方法 |
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-
1997
- 1997-01-24 JP JP09026203A patent/JP3119190B2/ja not_active Expired - Fee Related
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1998
- 1998-01-17 KR KR1019980001319A patent/KR100350748B1/ko not_active IP Right Cessation
- 1998-01-22 US US09/010,927 patent/US6313036B1/en not_active Expired - Fee Related
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN100442478C (zh) * | 2004-06-17 | 2008-12-10 | 尔必达存储器股份有限公司 | 具有多晶硅插头的半导体器件的制造方法 |
CN104838504A (zh) * | 2012-12-07 | 2015-08-12 | 三菱电机株式会社 | 半导体装置的制造方法 |
CN105280704A (zh) * | 2014-06-23 | 2016-01-27 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
US10084063B2 (en) | 2014-06-23 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
CN105280704B (zh) * | 2014-06-23 | 2019-07-16 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
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JP3119190B2 (ja) | 2000-12-18 |
KR100350748B1 (ko) | 2002-11-18 |
US6313036B1 (en) | 2001-11-06 |
KR19980070583A (ko) | 1998-10-26 |
JPH10209078A (ja) | 1998-08-07 |
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