CN104838504A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN104838504A
CN104838504A CN201280077547.0A CN201280077547A CN104838504A CN 104838504 A CN104838504 A CN 104838504A CN 201280077547 A CN201280077547 A CN 201280077547A CN 104838504 A CN104838504 A CN 104838504A
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semiconductor substrate
semiconductor device
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增冈史仁
中村胜光
加地考男
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Mitsubishi Electric Corp
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Abstract

在具有激活区域和终端区域的半导体衬底(1)的主面上形成绝缘膜(2)。对激活区域上的绝缘膜(2)进行蚀刻而形成开口(3)。使用绝缘膜(2)作为掩模，一边使半导体衬底(1)旋转，一边从相对于半导体衬底(1)的主面的法线方向倾斜大于或等于20°的方向向半导体衬底(1)注入杂质，在激活区域形成扩散层(7)。扩散层(7)与开口(3)相比延伸至终端区域侧的绝缘膜(2)的下方。

Description

半导体装置的制造方法
技术领域
本发明涉及一种适用于高耐压功率模块(≥600V)的半导体装置的制造方法。
背景技术
在适用于高耐压功率模块的二极管、IGBT等半导体装置中，为了使耐压提高而在激活区域的周边设置终端区域。在此，所谓激活区域是指在半导体装置的ON状态时主电流流过的区域。所谓终端区域是指在ON状态下主电流不流过，在OFF状态时(施加反向偏置时)将耗尽层在器件横向上延伸而保持耐压的区域。
在现有的半导体装置中，在恢复动作时，在终端区域和激活区域的边界，载流子浓度上升，因此正极侧的电场强度上升，超过临界电场强度而促进碰撞电离化。由于该部分的电流密度上升，因此温度局部地变高，超过临界温度(大于或等于800K)导致热破坏(例如，参照非专利文献1)。作为该问题的对策，提出了在激活区域的正极层的端部设置镇流电阻(例如，参照非专利文献2)。
非专利文献1：K.Nakamura，et al，“Advanced RFC Technologywith New Cathode Structure of Field Limited Rings for High VoltagePlanar Diode，”Proc.ISPSD’10，pp.133-136，2010
非专利文献2：A.Nishii，et al.，Proc.ISPSD’11，pp96-99，2011
发明内容
如果设置镇流电阻，则能够提高恢复破坏耐量。但是，当前存在下述问题，即，由于通过与形成正极层的工序不同的其他工序形成镇流电阻，因此制造工序变得复杂。
本发明就是为了解决上述的课题而提出的，其目的在于得到一种能够不增加制造工序，而提高恢复破坏耐量的半导体装置的制造方法。
本发明所涉及的半导体装置的制造方法，其特征在于，具有下述工序：在具有激活区域和终端区域的半导体衬底的主面上形成绝缘膜，并对所述激活区域上的所述绝缘膜进行蚀刻而形成第1开口；以及使用所述绝缘膜作为掩模，一边使所述半导体衬底旋转，一边从相对于所述半导体衬底的所述主面的法线方向倾斜大于或等于20°的方向向所述半导体衬底注入杂质，在所述激活区域形成扩散层，所述扩散层与所述第1开口相比延伸至所述终端区域侧的所述绝缘膜的下方。
发明的效果
根据本发明，能够提高恢复破坏耐量，而不增加制造工序。
附图说明
图1是表示本发明的实施方式1所涉及的半导体装置的制造方法的剖面图。
图2是表示本发明的实施方式1所涉及的半导体装置的制造方法的剖面图。
图3是表示本发明的实施方式2所涉及的半导体装置的制造方法的剖面图。
图4是表示本发明的实施方式3所涉及的半导体装置的制造方法的剖面图。
图5是表示本发明的实施方式4所涉及的半导体装置的制造方法的剖面图。
图6是表示本发明的实施方式5所涉及的半导体装置的制造方法的剖面图。
图7是表示本发明的实施方式6所涉及的半导体装置的制造方法的剖面图。
图8是表示本发明的实施方式7所涉及的半导体装置的制造方法的剖面图以及俯视图。
图9是表示本发明的实施方式8所涉及的半导体装置的制造方法的剖面图以及俯视图。
具体实施方式
参照附图对本发明的实施方式所涉及的半导体装置的制造方法进行说明。有时对于相同或对应的结构要素标注相同标号，省略重复的说明。
实施方式1.
图1以及图2是表示本发明的实施方式1所涉及的半导体装置的制造方法的剖面图。
首先，如图1所示，在具有激活区域和终端区域的n-型半导体衬底1的主面上形成氧化膜2。通过照相制版技术对激活区域上的氧化膜2进行蚀刻而形成开口3，与此同时，对终端区域上的氧化膜2进行蚀刻而形成多个开口4。此时，在开口3内残留薄膜5，在多个开口4内残留薄膜6。
然后，使用氧化膜2作为掩模，一边使n-型半导体衬底1旋转，一边从相对于n-型半导体衬底1的主面的法线方向倾斜大于或等于20°的方向，经由薄膜5、6向n-型半导体衬底1注入杂质，进行高温激励。由此，分别同时在激活区域形成p型正极层7、在终端区域形成多个p型环状层8。p型正极层7与开口3相比延伸至终端区域侧的氧化膜2的下方。其进入宽度为w1。
然后，如图2所示，在终端区域的端部形成n型沟道截断层9。利用湿蚀刻对薄膜5、6进行过蚀刻，形成正极电极10、环状电极11。为了将来自外部的影响抑制为最小限度，在终端区域形成SiOx、SiN等钝化膜12。有时根据所要保持的耐压，在钝化膜12上形成聚酰亚胺类材料。在n-型半导体衬底1的背面形成n型负极层13，形成与该n型负极层13连接的负极电极14。
在本实施方式中，由于从相对于半导体衬底的主面的法线方向倾斜大于或等于20°的方向注入杂质，因此，p型正极层7相对于开口3向横向扩展。由此，p型正极层7与开口3相比延伸至终端区域侧的氧化膜2的下方。该延伸出的区域成为镇流电阻。如上所述，通过在激活区域的p型正极层7的端部设置镇流电阻，从而能够对由于在恢复(截止)动作时积蓄在终端区域中的载流子向p型正极层7的端部集中而引起的热破坏进行抑制。因此，能够不增加制造工序，而提高恢复破坏耐量。
另外，在本实施方式中，同时形成分别配置在激活区域和终端区域的开口，同时形成两个区域的扩散层。由此，能够将制造工序简化，而不会对器件特性(例如，耐压VRRM、漏电流IRRM、阶跃恢复耐量等)造成不良影响。
另外，将薄膜5、6的膜厚设为作为与所要注入的离子种类对应的衬垫氧化膜所需要的膜厚。由此，能够降低对n-型半导体衬底1的损伤，使电气特性稳定化。另外，无需单独地形成衬垫氧化膜，因此能够将制造工序简化。并且，能够通过调整薄膜5、6的膜厚，从而将两个区域的扩散层的实际剂量设定为最优的值。
在此，如果降低p型正极层7的剂量，则正向电压VF增加，恢复损耗(Erec)减少。即，VF－EREC折衷关系曲线向高速侧偏移。因此，作为安装于高频用途的逆变器的续流二极管，即使VF增加，使EREC减少的优点也明显，因此p型正极层7的剂量优选降低至能够确保静耐压的程度。
另外，pn结的VF的温度依赖性基本上为正，如果温度上升则电流变得容易流过。在大容量的功率模块内，由于大多将功率芯片并联连接，因此，在模块内芯片的温度分布不均匀的情况下，产生电流进一步流过发热量较大的芯片而进行发热的正反馈，存在引起模块破坏的可能性。因此，室温的VF曲线和高温的VF曲线相交叉的电流值即交点越低越好。因此，降低正极·负极的有效剂量，降低来自两者的载流子注入效率，从而降低交点。
此外，p型正极层7和p型环状层8的剂量、扩散深度、宽度、数量、正极电极10、环状电极11、氧化膜2的设计是根据所要保持的耐压而不同的设计参数。
实施方式2.
图3是表示本发明的实施方式2所涉及的半导体装置的制造方法的剖面图。通过多次进行照相制版和蚀刻，使薄膜5的厚度t1和薄膜6的厚度t2不同。在此，由于t1>t2，因此激活区域的p型正极层7的剂量变得低于终端区域的p型环状层8的剂量。而且，与实施方式1相同地，一边使n-型半导体衬底1旋转，一边从相对于n-型半导体衬底1的主面的法线方向倾斜大于或等于20°的方向，经由薄膜5、6向n-型半导体衬底1注入杂质，进行高温激励。
如上所述，在本实施方式中薄膜5和薄膜6的厚度不同。由此，能够通过一次离子注入分别形成适当剂量的p型正极层7和p型环状层8。
在此，存在对p型正极层7的剂量进行调整而得到适于高速恢复动作(低EREC)、且也适于低速恢复动作(低正向电压VF)的二极管的方法。但是，该p型正极层7对二极管的电气特性造成较大的影响。如果提高剂量，则恢复时的电压振荡现象变得容易发生。相反地，如果降低剂量，则向正极侧的耗尽层进入宽度变大，耐压下降。即，在由p型正极层7实现的VF－EREC折衷关系特性的控制范围中存在限制。另一方面，在终端区域的p型环状层8、Resurf构造中分别存在最优的剂量。
因此，在本实施方式中，使薄膜5、6的膜厚不同。由此，能够在激活区域和终端区域使扩散层的剂量出现差异。而且，由于无需分别形成两者，因此，能够将制造工序简化，也不会发生激活区域和终端区域中的照相制版时的重合错位。
另外，通过设为t1>t2，从而能够同时形成表面浓度较低、扩散深度较浅的激活区域的p型正极层7，以及表面浓度较高、扩散深度较深的终端区域的p型环状层8。由此，可以得到能够保持静耐压并且高速通断动作的半导体装置，而不会增加制造工序。
实施方式3.
图4是表示本发明的实施方式3所涉及的半导体装置的制造方法的剖面图。在形成开口3时，在开口3的终端区域侧的端部残留薄膜15。经由薄膜5、15向n-型半导体衬底1注入杂质而形成p型正极层7。薄膜15的膜厚t3比薄膜5的膜厚t1薄(t1>t3)，例如将t3的膜厚设定为与t2相同的膜厚或设定为t2和t1之间的膜厚。而且，与实施方式1相同地，一边使n-型半导体衬底1旋转，一边从相对于n-型半导体衬底1的主面的法线方向倾斜大于或等于20°的方向，向n-型半导体衬底1注入杂质，进行高温激励。
另外，如果t1>t3，则能够增大p型正极层7的进入宽度w1，因此，能够使恢复破坏耐量进一步提高。并且，如果t1>t3，则在p型正极层7的终端区域侧的端部形成较深的部分。使该较深的部分的宽度w2与进入宽度w1相比宽15μm左右。由此，能够抑制恢复时的在p型正极层7的端部处的电场，使恢复破坏耐量进一步提高。
实施方式4.
图5是表示本发明的实施方式4所涉及的半导体装置的制造方法的剖面图。在薄膜5设置有多个台阶。由此，能够调整p型正极层7的剂量。其他的结构以及效果与实施方式3相同。
实施方式5.
图6是表示本发明的实施方式5所涉及的半导体装置的制造方法的剖面图。在开口3的终端区域侧的端部，薄膜5的膜厚为t4，与薄膜5的其他部分的膜厚t1相比较厚(t4>t1)。而且，与实施方式1相同地，一边使n-型半导体衬底1旋转，一边从相对于n-型半导体衬底1的主面的法线方向倾斜大于或等于20°的方向，经由薄膜5、6向n-型半导体衬底1注入杂质，进行高温激励。
在开口3的终端区域侧的端部，薄膜5的膜厚越朝向终端区域侧变得越厚。由此，在延伸至终端区域侧的氧化膜2的下方的部分中，与其他部分相比，薄膜5的剂量变低。由此，能够进一步提高恢复破坏耐量。
实施方式6.
图7是表示本发明的实施方式6所涉及的半导体装置的制造方法的剖面图。在开口3的终端区域侧的端部，在薄膜5设置倾斜，薄膜5的膜厚越朝向终端区域侧变得越厚。由此，能够得到与实施方式5相同的效果。
实施方式7.
图8是表示本发明的实施方式7所涉及的半导体装置的制造方法的剖面图以及俯视图。但是，在俯视图中省略了氧化膜2。
首先，在具有激活区域和终端区域的n-型半导体衬底1的主面上形成氧化膜2。然后，对激活区域上的氧化膜2进行蚀刻，残留膜厚不同的薄膜16、17而形成开口3。薄膜17为条纹状。与此同时，对终端区域上的氧化膜2进行蚀刻，残留薄膜18而形成开口4。
然后，经由薄膜16、17向n-型半导体衬底1注入杂质，进行高温激励。由此，在激活区域形成杂质浓度不同的p-型正极层19和p型正极层20。在此，p型正极层20为条纹状。与此同时，经由薄膜18向n-型半导体衬底1注入杂质，在终端区域形成p型环状层8。之后的工序与实施方式1相同。
通过在残留于开口3内的薄膜设置台阶，从而能够一并形成表面浓度以及扩散深度不同的p-型正极层19和p型正极层20。另外，能够通过杂质浓度较高的p型正极层20确保与电极的欧姆接触。而且，通过调整p-型正极层19的杂质浓度，也能够实现高速通断动作。
实施方式8
图9是表示本发明的实施方式8所涉及的半导体装置的制造方法的剖面图以及俯视图。在本实施方式中，由于薄膜17为点状，因此，p型正极层20也成为点状。其他结构与实施方式7相同，并能够得到与实施方式7相同的效果。
此外，无论耐压等级如何，都得到上述的效果。另外，本实施方式的半导体装置并不限定于由硅形成的半导体装置，由与硅相比带隙较宽的宽带隙半导体形成的半导体装置也能够得到上述的效果。宽带隙半导体是例如碳化硅、氮化镓类材料或者金刚石。由这种宽带隙半导体形成的半导体装置，由于耐电压性、容许电流密度高，因此能够小型化。通过使用该小型化后的半导体装置，从而能够将组装有该半导体装置的半导体模块也小型化。另外，由于半导体装置的耐热性高，因此能够使散热器的散热片小型化，能够使水冷部实现风冷化，因此，能够使半导体模块进一步小型化。另外，由于元件的电力损耗低、效率高，因此能够使半导体模块高效率化。
标号的说明
1n-型半导体衬底(半导体衬底)，2氧化膜(绝缘膜)，3开口(第1开口)，4开口(第2开口)，5、16薄膜(第1薄膜)，6、17薄膜(第2薄膜)，7p型正极层(扩散层)，8p型环状层(环状层)，15薄膜(第3薄膜)，19p-型正极层(第1扩散层)，20p型正极层(第2扩散层)。
权利要求书(按照条约第19条的修改)
1.(删除)
2.(修改后)一种半导体装置的制造方法，其特征在于，具有下述工序：
在具有激活区域和终端区域的半导体衬底的主面上形成绝缘膜，并对所述激活区域上的所述绝缘膜进行蚀刻而形成第1开口；
使用所述绝缘膜作为掩模，一边使所述半导体衬底旋转，一边从相对于所述半导体衬底的所述主面的法线方向倾斜大于或等于20°的方向向所述半导体衬底注入杂质，在所述激活区域形成扩散层；
对所述终端区域上的所述绝缘膜进行蚀刻，与所述第1开口同时形成第2开口；以及
向所述半导体衬底注入所述杂质，在所述激活区域形成所述扩散层的同时，在所述终端区域形成环状层，
所述扩散层与所述第1开口相比延伸至所述终端区域侧的所述绝缘膜的下方。
3.根据权利要求2所述的半导体装置的制造方法，其特征在于，
在形成所述第1以及第2开口时，在所述第1开口内残留第1薄膜，在所述第2开口内残留第2薄膜，
经由所述第1以及第2薄膜向所述半导体衬底注入所述杂质，形成所述扩散层和所述环状层。
4.根据权利要求3所述的半导体装置的制造方法，其特征在于，
所述第1以及第2薄膜的膜厚不同。
5.根据权利要求3或4所述的半导体装置的制造方法，其特征在于，
在形成所述第1开口时，在所述第1开口的所述终端区域侧的端部残留第3薄膜，
所述第3薄膜的膜厚比所述第1薄膜薄，
经由所述第1以及第3薄膜向所述半导体衬底注入所述杂质，形成所述扩散层。
6.根据权利要求3或4所述的半导体装置的制造方法，其特征在于，
在所述第1开口的所述终端区域侧的端部，所述第1薄膜的厚度越朝向所述终端区域侧变得越厚。
7.一种半导体装置的制造方法，其特征在于，具有下述工序：
在具有激活区域和终端区域的半导体衬底的主面上形成绝缘膜，并对所述激活区域上的所述绝缘膜进行蚀刻而残留膜厚不同的第1以及第2薄膜；以及
经由所述第1以及第2薄膜向所述半导体衬底注入杂质，在所述激活区域形成杂质浓度不同的第1以及第2扩散层。
8.根据权利要求7所述的半导体装置的制造方法，其特征在于，
所述第2扩散层为条纹状或点状。
说明或声明(按照条约第19条的修改)
在权利要求2中追加权利要求1的内容并改为独立权利要求。相应地，将权利要求1删除。

Claims (8)

1.一种半导体装置的制造方法，其特征在于，具有下述工序：
在具有激活区域和终端区域的半导体衬底的主面上形成绝缘膜，并对所述激活区域上的所述绝缘膜进行蚀刻而形成第1开口；以及
使用所述绝缘膜作为掩模，一边使所述半导体衬底旋转，一边从相对于所述半导体衬底的所述主面的法线方向倾斜大于或等于20°的方向向所述半导体衬底注入杂质，在所述激活区域形成扩散层，
所述扩散层与所述第1开口相比延伸至所述终端区域侧的所述绝缘膜的下方。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于，还具有下述工序：
对所述终端区域上的所述绝缘膜进行蚀刻，与所述第1开口同时形成第2开口；以及
向所述半导体衬底注入所述杂质，在所述激活区域形成所述扩散层的同时，在所述终端区域形成环状层。
3.根据权利要求2所述的半导体装置的制造方法，其特征在于，
在形成所述第1以及第2开口时，在所述第1开口内残留第1薄膜，在所述第2开口内残留第2薄膜，
经由所述第1以及第2薄膜向所述半导体衬底注入所述杂质，形成所述扩散层和所述环状层。
4.根据权利要求3所述的半导体装置的制造方法，其特征在于，
所述第1以及第2薄膜的膜厚不同。
5.根据权利要求3或4所述的半导体装置的制造方法，其特征在于，
在形成所述第1开口时，在所述第1开口的所述终端区域侧的端部残留第3薄膜，
所述第3薄膜的膜厚比所述第1薄膜薄，
经由所述第1以及第3薄膜向所述半导体衬底注入所述杂质，形成所述扩散层。
6.根据权利要求3或4所述的半导体装置的制造方法，其特征在于，
在所述第1开口的所述终端区域侧的端部，所述第1薄膜的厚度越朝向所述终端区域侧变得越厚。
7.一种半导体装置的制造方法，其特征在于，具有下述工序：
在具有激活区域和终端区域的半导体衬底的主面上形成绝缘膜，并对所述激活区域上的所述绝缘膜进行蚀刻而残留膜厚不同的第1以及第2薄膜；以及
经由所述第1以及第2薄膜向所述半导体衬底注入杂质，在所述激活区域形成杂质浓度不同的第1以及第2扩散层。
8.根据权利要求7所述的半导体装置的制造方法，其特征在于，
所述第2扩散层为条纹状或点状。
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