TW201423845A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

Info

Publication number
TW201423845A
TW201423845A TW102103423A TW102103423A TW201423845A TW 201423845 A TW201423845 A TW 201423845A TW 102103423 A TW102103423 A TW 102103423A TW 102103423 A TW102103423 A TW 102103423A TW 201423845 A TW201423845 A TW 201423845A
Authority
TW
Taiwan
Prior art keywords
film
opening
semiconductor substrate
semiconductor device
manufacturing
Prior art date
Application number
TW102103423A
Other languages
English (en)
Other versions
TWI478216B (zh
Inventor
Fumihito Masuoka
Katsumi Nakamura
Takao Kachi
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of TW201423845A publication Critical patent/TW201423845A/zh
Application granted granted Critical
Publication of TWI478216B publication Critical patent/TWI478216B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

在具有活性區域和終端區域的半導體基板(1)的主面上形成絕緣膜(2)。蝕刻活性區域上的絕緣膜(2)，形成開口(3)。絕緣膜(2)用作遮光罩，邊旋轉半導體基板(1)，邊從半導體基板(1)的主面離法線方向20°以上傾斜的方向注入不純物至半導體基板(1)，在活性區域形成擴散層(7)。擴散層(7)比開口(3)更延伸至終端區域側的絕緣膜(2)下方。

Description

半導體裝置之製造方法
本發明係關於適用於高耐壓功率模組(≧600V)的半導體裝置的製造方法。
適用於高耐壓功率模組的二極體、IGBT(絕緣柵雙極電晶體)等的半導體裝置中，為了提高耐壓，在活性區域的周邊設置終端區域。所謂活性區域係半導體裝置在ON(導通)狀態時，主電流流動的區域。所謂終端區域係ON(導通)狀態時，主電流不流過，且在OFF(關斷)狀態時(施加逆偏壓時)空乏層往元件橫方向延伸而保持耐壓的區域。
習知的半導體裝置，在復原動作時，在終端區域與活性區域的邊界，因為載子濃度升高，陽極側的電場強度上升，超過臨界電場強度，促進撞擊離子化。因為此部分的電流密度上升，溫度局部變高，超過臨界溫度(800K以上)，達到熱破壞(例如，參照非專利文件1)。提議在活性區域的陽極層端設置鎮流電阻，作為此對策(例如，參照非專利文件2)。
[先行專利文件]
[非專利文件1]K. Nakamura，等人，”Advanced RFC Technology with New Cathode Structure of Field Limiting Rings for High Voltage Planar Diode(對於高壓平面二極體具有場限制環體的新陰極結構之先進的射頻連接器技術)”，2010年ISPDS(功率半導體元件國際座談會)會議記錄，第133-136頁
[非專利文件2]A. Nishii，等人，2011年ISPSD(功率半導體元件國際座談會)會議記錄，第96-99頁
設置鎮流電阻的話，可以提高復原破壞耐量。不過，由於目前為止鎮流電阻與陽極層在不同的步驟中形成，有製造步驟變複雜的問題。
本發明，係用以解決上述的課題而形成的，所以其目的係可以不增加製造步驟，而得到提高復原破壞耐量之半導體裝置的製造方法。
根據本發明的半導體裝置的製造方法，包括下列步驟：在具有活性區域和終端區域的半導體基板的主面上形成絕緣膜，蝕刻上述活性區域上的上述絕緣膜，形成第1開口；以及上述絕緣膜用作遮光罩，邊旋轉上述半導體基板，邊從上述半導體基板的上述主面離法線方向20°以上傾斜的方向注入不純物至上述半導體基板，在活性區域形成擴散層；上述擴散層比上述第1開口更延伸至上述終端區域側的上述絕緣膜下方。
根據本發明，可以不增加製造步驟，而提高復原破壞耐量。
1‧‧‧n-型半導體基板(半導體基板)
2‧‧‧氧化膜(絕緣膜)
3‧‧‧開口(第1開口)
4‧‧‧開口(第2開口)
5、16‧‧‧薄膜(第1薄膜)
6、17‧‧‧薄膜(第2薄膜)
7‧‧‧p型陽極層(擴散層)
8‧‧‧p型環體層(環體層)
9‧‧‧n型通道阻絕層
10‧‧‧陽極電極
11‧‧‧環體電極
12‧‧‧鈍態膜
13‧‧‧n型陰極層
14‧‧‧陽極電極
15‧‧‧(薄膜第3薄膜)
17‧‧‧薄膜
18‧‧‧薄膜
19‧‧‧p-型陽極層(第1擴散層)
20‧‧‧p型陽極層(第2擴散層)
t1、t2、t3、t4‧‧‧膜厚
[第1圖]係顯示根據本發明第一實施例的半導體裝置的製造方法之剖面圖；[第2圖]係顯示根據本發明第一實施例的半導體裝置的製造方法之剖面圖；[第3圖]係顯示根據本發明第二實施例的半導體裝置的製造方法之剖面圖；[第4圖]係顯示根據本發明第三實施例的半導體裝置的製造方法之剖面圖；[第5圖]係顯示根據本發明第四實施例的半導體裝置的製造方法之剖面圖；[第6圖]係顯示根據本發明第五實施例的半導體裝置的製造方法之剖面圖；[第7圖]係顯示根據本發明第六實施例的半導體裝置的製造方法之剖面圖；[第8圖]係顯示根據本發明第七實施例的半導體裝置的製造方法之剖面圖及上面圖；以及[第9圖]係顯示根據本發明第八實施例的半導體裝置的製造方法之剖面圖及上面圖。
關於本發明實施例的半導體裝置的製造方法，參 照圖面說明。相同或對應的構成要素，附以相同的符號，有時省略重複的說明。
[第一實施例]
第1圖及第2圖，係顯示根據本發明第一實施例的半導體裝置的製造方法之剖面圖。
首先，如第1圖所示，在具有活性區域和終端區域的n-型半導體基板1的主面上形成氧化膜2。以照像製版技術蝕刻活性區域上的氧化膜2形成開口3，與此同時，蝕刻終端區域上的氧化膜2，形成複數的開口4。此時，開口3內留下薄膜5，在複數的開口4內留下薄膜6。
其次，使用氧化膜2作為遮光罩，邊旋轉n-型半導體基板1，邊從n-型半導體基板1的主面離法線方向20°以上傾斜的方向，通過薄膜5、6，注入不純物至n-半導體基板1，執行高溫驅動。因此，同時分別在活性區域形成p型陽極層7，在終端區域形成複數的p型環體層8。p型陽極層7比開口3更延伸至終端區域側的氧化膜2下方。此深入寬度為w1。
其次，如第2圖所示，在終端區域端形成n型通道阻絕層9。以溼蝕刻過度蝕刻薄膜5、6，形成陽極電極10、環體電極11。為了抑制來自外部的影響至最低限度，在終端區域形成SiOx(氧化矽)、SiN(氮化矽)等的鈍態膜12。由於保持的耐壓，在鈍態膜12上也有形成聚醯亞胺(Polyimide)系材料的情況。n-型半導體基板1的背面形成n型陰極層13，而且形成連接的陽極電極14。
本實施例中，由於從半導體基板1的主面離法線 方向20°以上傾斜的方向注入不純物，p型陽極層7對開口3往橫方向擴展。因此，p型陽極層7比開口3更延伸至終端區域側的氧化膜2下方。此延伸的區域成為鎮流電阻。藉由如此地在活性區域的p型陽極層7端設置鎮流電阻，可以抑制復原(關斷)動作時終端區域中累積的載子集中在p型陽極層7端引起的熱破壞。因此，可以不增加製造步驟，而提高復原破壞耐量。
又，本實施例中，同時形成分別配置在活性區域與終端區域的開口，並同時形成兩區域的擴散層。因此，對元件特性(例如，耐壓VRRM(反向重複峰值電壓)，漏電流IRRM(反向重複峰值電流)間距(snapoff)耐量等)可以不帶來壞影響，而簡化製造步驟。
又，薄膜5、6的膜厚，依照注入的離子種類，作為底下氧化膜，設為必須的膜厚。因此，降低對n-型半導體基板1的損傷，可以穩定電氣特性。又，因為底下氧化膜不必個別形成，可以簡化製造步驟。又，藉由調整薄膜5、6的膜厚，可以設定兩區域的擴散層的實效劑量至最適當值。
在此，降低p型陽極層7的劑量時，順電壓VF增加，且復原損失(Erec)。即，VF-EREC取捨曲線(trade-off curve)往高速側位移。因此，作為納入高頻用途反相器的續流二極體，由於即使VF增加也可以減少EREC的優點很大，p型陽極層7的劑量最好降低至可以確保靜耐壓的程度。
又，pn接合的VF的溫度依存性基本上是正的，溫度上升時，電流變得容易流過。由於大電容的功率模組內功 率晶片並聯連接的情況很多，模組內晶片的溫度分佈產生偏向時，發熱量大的晶片又發生電流流動發熱之類的正返回，有引起模組破壞的可能性。於是，室溫的VF曲線與高溫的VF曲線的交叉電流值之交叉點最好是低的。於是，降低陽極．陰極的實效劑量，而降低來自兩者的載子注入效率，藉此降低交叉點。
又，p型陽極層7與p型環體層8的劑量、擴散深度、寬度、數量、陽極電極10、環體電極11、氧化膜2的設計，根據保持的耐壓，係不同的設計參數。
[第二實施例]
第3圖，係顯示根據本發明第二實施例的半導體裝置的製造方法之剖面圖。藉由執行複數的照像製版和蝕刻，使薄膜5的膜厚t1與薄膜6的膜厚t2不同。在此，由於t1>t2，活性區域的p型陽極層7的劑量變得比終端區域的p型環體層8的劑量低。於是，與第一實施例相同，邊旋轉n-型半導體基板1，邊從n-型半導體基板1的主面離法線方向20°以上傾斜的方向，通過薄膜5、6，注入不純物至n-型半導體基板1，執行高溫驅動。
如上述，本實施例中，薄膜5與薄膜6的膜厚不同。因此，可以以一次離子注入分別形成適當劑量的p型陽極層7與p型環體層8。
在此，有方法調整p型陽極層7的劑量，得到適於高速復原動作(低EREC)，且也適於低速復原動作(低順電壓VF)的二極體。不過，此p型陽極層7給二極體的電氣特性帶 來大的影響。提高劑量時，變得容易發生復原時的電壓振盪現象。相反地，降低劑量時，往陽極側的空乏層深入寬度變大，耐壓下降。即，對於p型陽極層7引起的VF-EREC取捨曲線特性的控制範圍有限制。另一方面，對於終端區域的p型環體層8、Resurf(高耐壓低表面電場)構造，分別有最適當的劑量。
於是，本實施例中，使薄膜5、6的膜厚不同。因此，活性區域與終端區域中擴散層的劑量可以有差距。於是，因為兩者不必分別形成，可以簡化製造步驟，也不會發生活性區域與終端區域中照像製版時的相互重疊差距。
又，由於假設t1>t2，可以同時形成表面濃度低而擴散深度淺的活性區域的p型陽極層7與表面濃度高而擴散深度深的終端區域的p型環體層8。因此，可以不增加製造步驟，而保持靜耐壓的同時，可以得到高速切換動作的半導體裝置。
[第三實施例]
第4圖，係顯示根據本發明第三實施例的半導體裝置的製造方法之剖面圖。形成開口3之際，開口3的終端區域側的端部留下薄膜15。通過薄膜5、15，注入不純物至n-半導體基板1，形成p型陽極層7。薄膜15的膜厚t3比薄膜5的膜厚t1薄(t1>t3)，例如設定t3的膜厚為與t2相同膜厚或是在t2與t1之間的膜厚。於是，與第一實施例相同，邊旋轉n-型半導體基板1，邊從n-型半導體基板1的主面離法線方向20°以上傾斜的方向，注入不純物至半導體基板1，執行高溫驅動。
又，t1>t3的話，由於可以得到大的p型陽極層7的深入寬度w1，可以更加提高復原破壞耐量。又，t1>t3的話， p型陽極層7的終端區域側的端部形成深的部分。使此深的部分的寬度w2比深入寬度w1寬15微米。因此，抑制復原時在p型陽極層7的端部的電場，可以更加提高復原破壞耐量。
[第四實施例]
第5圖，係顯示根據本發明第四實施例的半導體裝置的製造方法之剖面圖。薄膜5中設置複數的段差。因此可以調整p型陽極層7的劑量。其他的構成及效果與第三實施例相同。
[第五實施例]
第6圖，係顯示根據本發明第五實施例的半導體裝置的製造方法之剖面圖。在開口3的終端區域側的端部，薄膜5的膜厚為t4，比薄膜5的其他部分的膜厚t1厚(t4>t1)。於是，與第一實施例相同，邊旋轉n-型半導體基板1，邊從n-型半導體基板1的主面離法線方向20°以上傾斜的方向，通過薄膜5、6，注入不純物至n-型半導體基板1，執行高溫驅動。
在開口3的終端區域側的端部，薄膜5的膜厚越往終端區域側越厚。因此，延伸至終端區域側的氧化膜2下方的部分，比其他部分薄膜5的劑量變更低。因此，可以更加提高復原破壞耐量。
[第六實施例]
第7圖，係顯示根據本發明第六實施例的半導體裝置的製造方法之剖面圖。在開口3的終端區域側的端部，薄膜5中設置傾斜，薄膜5的膜厚越往終端區域側越厚。因此，可以得到與第五實施例相同的效果。
[第七實施例]
第8圖，係顯示根據本發明第七實施例的半導體裝置的製造方法之剖面圖及上面圖。但是，上面圖中省略氧化膜2。
首先，具有活性區域和終端區域的n-型半導體基板1的主面上，形成氧化膜2。其次，蝕刻活性區域上的氧化膜2，留下膜厚不同的薄膜16、17，形成開口3。薄膜17是條狀。與此同時，蝕刻終端區域上的氧化膜2，留下薄膜18，形成開口4。
其次，通過薄膜16、17，注入不純物至n-半導體基板1，執行高溫驅動。因此，在活性區域形成不純物濃度不同的p-型陽極層19以及p型陽極層20。在此，p型陽極層20係條紋狀。與此同時，通過薄膜18，注入不純物至n-半導體基板1，在終端區域中形成p型環體層8。之後的步驟與第一實施例相同。
藉由在開口3內留下的薄膜中設置段差，表面濃度及擴散深度不同的p-型陽極層19以及p型陽極層20可以一次形成。又，由於不純物濃度高的p型陽極層20，可以確保與電極的歐姆接觸。於是，藉由調整p-型陽極層19的不純物濃度，高速切換動作也是可以。
[第八實施例]
第9圖，係顯示根據本發明第八實施例的半導體裝置的製造方法之剖面圖及上面圖。本實施例中，由於薄膜17為點狀，p型陽極層20也成為點狀。其他的構成與第七實施例 相同，可以得到與第七實施例相同的效果。
又，不論耐壓等級，可以得到上述的效果。又，本實施例的半導體裝置，不限於以矽形成，與矽相較，即使以能隙大的寬能隙半導體形成，也可以得到上述的效果。寬能隙半導體，例如，碳化矽(SiC)、氮化鎵系材料、或鑽石。如此的寬能隙半導體形成的半導體裝置，由於耐電壓特性、容許電流密度高，可以小型化。藉由使用此小型化的半導體裝置，納入此半導體裝置的半導體模組也可以小型化。又，由於半導體裝置的耐熱性高，吸熱裝置的鰭片可以小型化，由於可以空冷化水冷部，半導體模組可以更小型化。又，由於元件的電力損失低且高效率，可以高效率化半導體模組。
1‧‧‧n-型半導體基板(半導體基板)
2‧‧‧氧化膜(絕緣膜)
3‧‧‧開口(第1開口)
4‧‧‧開口(第2開口)
5‧‧‧薄膜(第1薄膜)
6‧‧‧薄膜(第2薄膜)
7‧‧‧p型陽極層(擴散層)
8‧‧‧p型環體層(環體層)
w1‧‧‧深入寬度

Claims (8)

  1. 一種半導體裝置的製造方法，包括下列步驟：形成第1開口步驟，在具有活性區域和終端區域的半導體基板的主面上形成絕緣膜，蝕刻上述活性區域上的上述絕緣膜，形成第1開口；以及形成擴散層步驟，上述絕緣膜用作遮光罩，邊旋轉上述半導體基板，邊從上述半導體基板的上述主面離法線方向20°以上傾斜的方向注入不純物至上述半導體基板，在上述活性區域形成擴散層；其特徵在於：上述擴散層比上述第1開口更延伸至上述終端區域側的上述絕緣膜下方。
  2. 如申請專利範圍第1項所述的半導體裝置的製造方法，更包括下列步驟：同時形成開口步驟，蝕刻上述終端區域上的上述絕緣膜，與上述第1開口同時形成第2開口；以及形成環體層步驟，注入上述不純物至上述半導體基板，在上述活性區域形成上述擴散層的同時，在上述終端區域形成環體層。
  3. 如申請專利範圍第2項所述的半導體裝置的製造方法，其中，形成上述第1及第2開口之際，上述第1開口內留下第1薄膜，上述第2開口內留下第2薄膜；以及通過上述第1及第2薄膜，注入上述不純物至上述半導體基板，形成上述擴散層與上述環體層。
  4. 如申請專利範圍第3項所述的半導體裝置的製造方法，其中，上述第1及第2薄膜的膜厚不同。
  5. 如申請專利範圍第3或4項所述的半導體裝置的製造方法，其中，形成上述第1開口之際，在上述第1開口的上述終端區域側的端部留下第3薄膜；上述第3薄膜的膜厚比上述第1薄膜薄；以及通過上述第1及第3薄膜，注入上述不純物至上述半導體基板，形成上述擴散層。
  6. 如申請專利範圍第3或4項所述的半導體裝置的製造方法，其中，在上述第1開口的上述終端區域側的端部，上述第1薄膜的膜厚越往上述終端區域側變得越厚。
  7. 一種半導體裝置的製造方法，其特徵在於包括下列步驟：留下第1及第2薄膜步驟，在具有活性區域和終端區域的半導體基板的主面上形成絕緣膜，蝕刻上述活性區域上的上述絕緣膜，留下膜厚不同的第1及第2薄膜；以及形成第1及第2擴散層步驟，通過上述第1及第2薄膜，注入不純物至上述半導體基板，在上述活性區域形成不純物濃度不同的第1及第2擴散層。
  8. 如申請專利範圍第7項所述的半導體裝置的製造方法，其中，上述第2擴散層係條紋狀或點狀。
TW102103423A 2012-12-07 2013-01-30 半導體裝置之製造方法 TWI478216B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2012/081833 WO2014087543A1 (ja) 2012-12-07 2012-12-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201423845A true TW201423845A (zh) 2014-06-16
TWI478216B TWI478216B (zh) 2015-03-21

Family

ID=50882987

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102103423A TWI478216B (zh) 2012-12-07 2013-01-30 半導體裝置之製造方法

Country Status (6)

Country Link
US (1) US9455148B2 (zh)
JP (1) JP5822032B2 (zh)
CN (1) CN104838504B (zh)
DE (1) DE112012007206B4 (zh)
TW (1) TWI478216B (zh)
WO (1) WO2014087543A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6337964B2 (ja) * 2014-07-23 2018-06-06 富士電機株式会社 半導体装置および半導体装置の製造方法
CN108122758A (zh) * 2016-11-30 2018-06-05 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN109560122A (zh) * 2019-01-24 2019-04-02 派恩杰半导体（杭州）有限公司 一种带有沟槽结构的高压宽禁带二极管芯片
EP3742476A1 (en) 2019-05-20 2020-11-25 Infineon Technologies AG Method of implanting an implant species into a substrate at different depths
JP7450516B2 (ja) * 2020-10-22 2024-03-15 三菱電機株式会社 電力用半導体装置
CN113782440A (zh) * 2021-08-31 2021-12-10 上海华力集成电路制造有限公司 FinFET的阈值电压调节方法
CN116110943A (zh) * 2023-04-11 2023-05-12 通威微电子有限公司 一种耐压器件及其制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04119632A (ja) 1990-09-10 1992-04-21 Kawasaki Steel Corp 半導体素子の高耐圧ｐｎ接合形成方法
JPH04254323A (ja) 1991-02-06 1992-09-09 Fujitsu Ltd 半導体装置の製造方法
JPH07193018A (ja) * 1993-12-27 1995-07-28 Takaoka Electric Mfg Co Ltd 高耐圧半導体素子の製造方法
JPH07221326A (ja) 1994-02-07 1995-08-18 Fuji Electric Co Ltd プレーナ型半導体素子
KR0154702B1 (ko) * 1995-06-09 1998-10-15 김광호 항복전압을 향상시킨 다이오드 제조 방법
JP3211865B2 (ja) 1996-05-31 2001-09-25 日本電気株式会社 イオン注入方法
US6043112A (en) * 1996-07-25 2000-03-28 International Rectifier Corp. IGBT with reduced forward voltage drop and reduced switching loss
JP3119190B2 (ja) * 1997-01-24 2000-12-18 日本電気株式会社 半導体装置の製造方法
JP3266117B2 (ja) * 1998-11-11 2002-03-18 サンケン電気株式会社 半導体装置及びその製造方法
JP2007096006A (ja) 2005-09-29 2007-04-12 Nippon Inter Electronics Corp ガードリングの製造方法および半導体装置
JP2007184439A (ja) * 2006-01-10 2007-07-19 Shindengen Electric Mfg Co Ltd 半導体装置
US7944018B2 (en) * 2006-08-14 2011-05-17 Icemos Technology Ltd. Semiconductor devices with sealed, unlined trenches and methods of forming same
JP5515922B2 (ja) * 2010-03-24 2014-06-11 富士電機株式会社 半導体装置
JP5605073B2 (ja) 2010-08-17 2014-10-15 株式会社デンソー 半導体装置
DE112012006215B4 (de) 2012-04-13 2020-09-10 Mitsubishi Electric Corp. Diode

Also Published As

Publication number Publication date
TWI478216B (zh) 2015-03-21
JPWO2014087543A1 (ja) 2017-01-05
CN104838504B (zh) 2017-08-15
WO2014087543A1 (ja) 2014-06-12
US9455148B2 (en) 2016-09-27
DE112012007206T5 (de) 2015-09-10
JP5822032B2 (ja) 2015-11-24
US20150255290A1 (en) 2015-09-10
CN104838504A (zh) 2015-08-12
DE112012007206B4 (de) 2021-07-01

Similar Documents

Publication Publication Date Title
US9653599B2 (en) Semiconductor device and method of manufacturing semiconductor device
US9601485B2 (en) Reverse-conducting IGBT with buffer layer and separation layer for reducing snapback
TWI478216B (zh) 半導體裝置之製造方法
TWI637527B (zh) 半導體裝置及其製造方法
US10056450B2 (en) Semiconductor device
TWI437690B (zh) 半導體裝置
US9614106B2 (en) Semiconductor device
US10840238B2 (en) Semiconductor device
JP5725083B2 (ja) 半導体装置
WO2011129443A1 (ja) 半導体装置
JP5810522B2 (ja) 異種材料接合型ダイオード及びその製造方法
CN104576710B (zh) 半导体装置
KR101745437B1 (ko) 바이폴라 넌-펀치-쓰루 전력 반도체 디바이스
US9543289B2 (en) Manufacturing method of semiconductor device
JP2007258742A (ja) 高耐電圧半導体装置
JP5233158B2 (ja) 炭化珪素半導体装置
US9018633B2 (en) Semiconductor device
JP5310291B2 (ja) 半導体装置およびその製造方法
US9257544B2 (en) Semiconductor device and fabrication method of semiconductor device
US10069000B2 (en) Bipolar non-punch-through power semiconductor device
US8969959B2 (en) Semiconductor device and method of manufacturing the same
JP2011165924A (ja) 半導体装置
JP2017028150A (ja) 半導体装置