CN1161843C - 具有小宽/长比的闭合晶体管 - Google Patents

具有小宽/长比的闭合晶体管 Download PDF

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CN1161843C
CN1161843C CNB981149030A CN98114903A CN1161843C CN 1161843 C CN1161843 C CN 1161843C CN B981149030 A CNB981149030 A CN B981149030A CN 98114903 A CN98114903 A CN 98114903A CN 1161843 C CN1161843 C CN 1161843C
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CN1204157A (zh
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彼得・波赫米勒
彼得·波赫米勒
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)

Abstract

本发明提供一种集成电路中用的闭合晶体管，它具有能很好限定W/L比小的器件尺寸，该闭合晶体管包括：围绕有源器件区的浅沟槽隔离区，该浅沟槽隔离区包括一介质；和该闭合晶体管是在该器件区上，它包括覆盖在有源器件区上的栅；位于有源器件区内而没有浅沟槽隔离区与有源器件区之间的接触界面的源和漏，其中，用所述栅使所述源和漏相互隔开。有围绕源和漏的折合的栅导体的晶体管，能很好控制长和宽的尺寸，使宽(W)与长(L)之比W/L小。

Description

具有小宽/长比的 闭合晶体管
技术领域
本发明涉及半导体器件，特别涉及良好限定阈值电压和小宽/长(以下称作W/L)比的晶体管。
背景技术
在器件制造中，在衬底或晶片上形成绝缘层，半导体层和导电层。对这些膜层构图，确定元件和空间，形成器件，如晶体管，电容器和电阻器。之后，互连这些器件，获得要求的电功能，构成集成电路(IC)或芯片。
参见图1A，图中示出了常规的晶体管布图或设计。如图示，晶体管的有源区包括栅140，源135和漏136。栅下面在源与漏之间形成是重掺杂区的较簿的绝缘层。绝缘层是指栅氧化层。在栅上加超过栅阈值电压(VT)的电压，使在栅下面形成导电沟道。该导电沟道连接源和漏，使电流由此流过。
沟道的宽/长(W/L)比确定从源流到漏的电流量。比值越大，流过的电流越大。因此，晶体管的长和宽与设计参量和要求有关，以获得要求的W/L比。
晶体管有源区周围的隔离区1 30使其与其它器件隔离。隔离区通常包括较厚的氧化硅(SiO2)或其它介质材料。可用各种隔离，如LOCOS或浅沟槽隔离(STI)。
常规晶体管布图中，在隔离区与源和漏之间的栅的界面180处形成寄生晶体管器件。由于不能控制在STI氧化层与栅氧化层之间的过渡区中的氧化层厚度，因此，形成寄生器件。如图1B所示，附加的寄生晶体管190与设计的晶体管并联。
由于不能精确确定沟道上的氧化层厚度，因此不能正确确定寄生晶体管的VTS。由于并联寄生晶体管，所以不能正确确定的VTS使器件的VT出现总的变化。不希望设计器件的总VT变化，特别用在如参考电压发生器或差分放大器这些要求精确匹配的晶体管器件和精确的栅阈值电压的地方更更不希望出现器件的VT变化。
为防止寄生晶体管的不利影响，已采用闭合晶体管器件。在闭合晶体管中，可避免源与漏之间出现STI界面。通常，在有源区上以闭合环形式构成栅。尽管不可能避免在栅下面的STI边缘，但是STI边缘不再连接有不同电位的区域，即源和漏。因此，不会形成寄生角器件。
但是，常规的闭合晶体管布图对小W/L比如W/L≤4是不合适的。某些用小W/L比的应用中，要达到规定的电流要求，闭合晶体管不能用。
因此，从上述情况看，要求提供具有小W/L比的闭合晶体管。
发明内容
本发明涉及具有小W/L比的闭合晶体管，该晶体管包括围绕源和漏区的折合的(folded)栅导体，从而避免ST1界面与有不同电位的晶体管区接触。包围源和漏周围的栅的折合(folding)使其能很好地控制宽度和长度尺寸从而能达到小的W/L比。
为此，本发明提供一种集成电路中用的闭合晶体管，它具有能很好限定通道的宽度和长度比小的器件尺寸，该闭合晶体管包括：围绕有源器件区的浅沟槽隔离区，该浅沟槽隔离区包括一介质；和该闭合晶体管是在该器件区上，它包括一栅，其在有源区之内形成为闭合的环或回路，并且覆盖浅沟槽隔离区；位于有源器件区内而没有浅沟槽隔离区与有源器件区之间的接触界面的源和漏，其中，用所述栅使所述源和漏相互隔开。
附图说明
图1A-1B示出常规晶体管和寄生器件的布图；
图2-3示出常规闭合晶体管的布图；
图4是按本发明实施例的布图。
具体实施方式
本发明涉及IC，特别涉及具有小W/L比的闭合晶体管，通常以并联方式在半导体晶片上构成IC。制成之后，切割晶片，把IC分割成单个芯片。为了简化说明，以IC如存储器器件中用的闭合晶体管为例说明本发明。存储器器件包括随机存取存储器(RAM)、如动态随机存取存储器(DRAM)，同步DRAM(SDRAM)或其它存储器IC。也用其它IC如专用集成电路的IC(ASIC)或逻辑器件。为了简化说明，先说明常规W/L比晶体管。
参见图2，图中示出常规闭合晶体管布图的顶视图。如图示，在衬底210表面上形成闭合晶体管201。在衬底中确定其上要形成晶体管的有源区215。隔离区，如有源区周围的STI使晶体管与IC中的其它器件隔离。
晶体管包括栅240。在有源区215中形成如闭合环或回路的栅。有源区内的回路内外分别是源区235和漏区236。因此，栅把源和漏区相互隔开。当栅上加适当电压时，在栅下面形成构成导电沟道的栅氧化物，使电流能在源与漏之间流动。
如图所示，栅的一部分244覆盖STI。设置的覆盖部分中可以形成接触开口，由于设计方面的限制，通常禁止在有源区上接触到栅。结果，STI在覆盖部分244与栅相接。但是，该边缘只连接有相同电位的源区。由于只有相同电位的区域被连接，因此，无电流流动。因此，不形成寄生晶体管。
用改变栅的宽度或长度来调节器件的长和宽。但是，由于要形成闭合回路，栅是弯曲形成，因此不能精确确定闭合晶体管的栅的长度和宽度。通常，器件宽度W约为内边缘265和外边缘266的中间260的周边。长度约为内边缘265至外边缘266的距离。
常规闭合晶体管的缺点是不可能获得小W/L比。
参见图3，它示出W/L比约为4的闭合晶体管。如图所示，晶体管有一特别形状，在该形状中有位于栅回路340内的小漏区336。这种晶体管不会像图1所示的常规的平直晶体管一样工作。这是因为这种形状使W和L更不确定。由于在栅弯曲处的实际栅长(从S至D的距离)达到21/2×L，因此很难确定L的有效平均值。同样，由于漏几乎消失了。平均周边不可能是有效晶体管宽度。因此，很难确定W。由于标准的提取工具不能确定这种布图的有效W和L，因此，很难产生布图的检验工具。对大W/L比而言。W和L的近似值是相当精确，但问题是W/L小于4。
按本发明，提供具有小W/L比的闭合晶体管布图。图4是本发明布图的顶视图。如图所示，在例如硅晶片的衬底410上设置有源区415。其它衬底，如砷化镓或锗也能用。衬底通常用第一导电类型的杂质掺杂。为了获得要求的电性能和特性，衬底可以轻掺杂也可以重掺杂。围绕有源区的是隔离区430，如STI。STI包括如SiO2的介质材料。
有源区内设有源区435和漏区436。通常，源和漏区是用第二导电类型的杂质重掺杂。在一个实施例中，第一导电类型是P型，第二导电类型是N型。P型杂质包括硼，N型杂质包括砷和磷。
有源区上设栅导体440。栅导体包括例如多晶硅。可用任何多晶硅化物形成栅导体折合的(folded)栅环绕或包围源和漏，以有效地防止它接触STI区。栅覆盖STI，能充分防止形成寄生电阻。
晶体管有控制很好的W和L尺寸。如图4所示，W是沿漏或源的栅的尺寸，L是从漏到源的尺寸。从图3能清楚地看到，调节W和/或L能获得W/L≤4，W/L优选为1至4，1至4更好。按本发明，甚至能得到具有W/L≤1的晶体管。
尽管用各个说明例特别展示和说明了发明，但本领域的技术人员会发现，不脱离发明的精神和范围还能对发明做出各种改进和变化。元件的尺寸和形状可以变化，仅仅是为了举例。以上说明不应作为确定本发明的范围，而应以权利要求及其等同物的全部范围来确定本发明的保护范围。

Claims (1)

1.一种集成电路中用的闭合晶体管，它具有能很好限定沟道的宽度和长度比小的器件尺寸，该闭合晶体管包括：
围绕有源器件区的浅沟槽隔离区，该浅沟槽隔离区包括一介质；和
该闭合晶体管是在该器件区上，它包括
一栅，其在有源区之内形成为闭合的环或回路，并且覆盖浅沟槽隔离区；
位于有源器件区内而没有浅沟槽隔离区与有源器件区之间的接触界面的源和漏，其中，用所述栅使所述源和漏相互隔开。
CNB981149030A 1997-06-30 1998-06-17 具有小宽/长比的闭合晶体管 Expired - Lifetime CN1161843C (zh)

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KR (1) KR100541826B1 (zh)
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EP1501130A1 (en) * 2003-07-21 2005-01-26 STMicroelectronics S.r.l. Semiconductor MOS device and related manufacturing method
US7042009B2 (en) * 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US8635573B2 (en) * 2011-08-01 2014-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a semiconductor device having a defined minimum gate spacing between adjacent gate structures
CN107516677A (zh) * 2016-06-17 2017-12-26 上海新微科技服务有限公司 一种mos场效应晶体管
CN109935636B (zh) * 2019-03-11 2022-08-26 长江存储科技有限责任公司 晶体管及其形成方法、存储器

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US4240093A (en) * 1976-12-10 1980-12-16 Rca Corporation Integrated circuit device including both N-channel and P-channel insulated gate field effect transistors
US4173022A (en) * 1978-05-09 1979-10-30 Rca Corp. Integrated gate field effect transistors having closed gate structure with controlled avalanche characteristics
DE3925123A1 (de) * 1989-07-28 1991-02-07 Siemens Ag Elektrodenanordnung fuer feldeffekttransistoren
KR0149527B1 (ko) * 1994-06-15 1998-10-01 김주용 반도체 소자의 고전압용 트랜지스터 및 그 제조방법

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DE69804907T2 (de) 2002-11-07
HK1015547A1 (en) 1999-10-15
CN1204157A (zh) 1999-01-06
EP0889530A1 (en) 1999-01-07
KR100541826B1 (ko) 2006-06-01
TW406315B (en) 2000-09-21
JPH1168091A (ja) 1999-03-09
EP0889530B1 (en) 2002-04-17
DE69804907D1 (de) 2002-05-23

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