CN1158700C - 具有自对准的非集成电容器排布的存储器装置 - Google Patents

具有自对准的非集成电容器排布的存储器装置 Download PDF

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Publication number
CN1158700C
CN1158700C CNB971983755A CN97198375A CN1158700C CN 1158700 C CN1158700 C CN 1158700C CN B971983755 A CNB971983755 A CN B971983755A CN 97198375 A CN97198375 A CN 97198375A CN 1158700 C CN1158700 C CN 1158700C
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CN
China
Prior art keywords
contact
main surface
memory device
raised
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB971983755A
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English (en)
Chinese (zh)
Other versions
CN1231761A (zh
Inventor
W
W·哈特纳
G·欣德勒
-
C·马祖雷-埃斯佩佐
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Siemens Corp
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Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of CN1231761A publication Critical patent/CN1231761A/zh
Application granted granted Critical
Publication of CN1158700C publication Critical patent/CN1158700C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07227—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/281—Auxiliary members
    • H10W72/285—Alignment aids, e.g. alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Memories (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
CNB971983755A 1996-09-30 1997-08-07 具有自对准的非集成电容器排布的存储器装置 Expired - Fee Related CN1158700C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19640213A DE19640213C1 (de) 1996-09-30 1996-09-30 Speicheranordnung mit selbstjustierender nicht integrierter Kondensatoranordnung
DE19640213.1 1996-09-30

Publications (2)

Publication Number Publication Date
CN1231761A CN1231761A (zh) 1999-10-13
CN1158700C true CN1158700C (zh) 2004-07-21

Family

ID=7807379

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB971983755A Expired - Fee Related CN1158700C (zh) 1996-09-30 1997-08-07 具有自对准的非集成电容器排布的存储器装置

Country Status (9)

Country Link
US (1) US6097050A (enExample)
EP (1) EP0931337A1 (enExample)
JP (1) JP3280988B2 (enExample)
KR (1) KR100414237B1 (enExample)
CN (1) CN1158700C (enExample)
DE (1) DE19640213C1 (enExample)
IN (1) IN192035B (enExample)
TW (1) TW369695B (enExample)
WO (1) WO1998014996A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100551607B1 (ko) * 1998-01-19 2006-02-13 시티즌 도케이 가부시키가이샤 반도체 패키지
JP3743891B2 (ja) * 2003-05-09 2006-02-08 松下電器産業株式会社 不揮発性メモリおよびその製造方法
KR100778227B1 (ko) 2006-08-23 2007-11-20 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
KR100852603B1 (ko) * 2006-12-27 2008-08-14 동부일렉트로닉스 주식회사 반도체소자 및 그 제조방법
JP5585167B2 (ja) * 2010-03-30 2014-09-10 富士通株式会社 電子デバイス及び電子デバイスの製造方法
CN116076163A (zh) * 2020-09-29 2023-05-05 华为技术有限公司 三维存储器及其制备方法、电子设备

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912545A (en) 1987-09-16 1990-03-27 Irvine Sensors Corporation Bonding of aligned conductive bumps on adjacent surfaces
JP2788265B2 (ja) * 1988-07-08 1998-08-20 オリンパス光学工業株式会社 強誘電体メモリ及びその駆動方法，製造方法
DE3824008A1 (de) * 1988-07-15 1990-01-25 Contraves Ag Elektronische schaltung sowie verfahren zu deren herstellung
US5406701A (en) * 1992-10-02 1995-04-18 Irvine Sensors Corporation Fabrication of dense parallel solder bump connections
US5335138A (en) * 1993-02-12 1994-08-02 Micron Semiconductor, Inc. High dielectric constant capacitor and method of manufacture
KR960009074A (ko) * 1994-08-29 1996-03-22 모리시다 요이치 반도체 장치 및 그 제조방법

Also Published As

Publication number Publication date
WO1998014996A1 (de) 1998-04-09
TW369695B (en) 1999-09-11
US6097050A (en) 2000-08-01
JP3280988B2 (ja) 2002-05-13
KR20000048721A (ko) 2000-07-25
EP0931337A1 (de) 1999-07-28
JP2001501370A (ja) 2001-01-30
CN1231761A (zh) 1999-10-13
DE19640213C1 (de) 1998-03-05
IN192035B (enExample) 2004-02-14
KR100414237B1 (ko) 2004-01-13

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20040721

Termination date: 20090907