CN115836386A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN115836386A
CN115836386A CN202080102980.XA CN202080102980A CN115836386A CN 115836386 A CN115836386 A CN 115836386A CN 202080102980 A CN202080102980 A CN 202080102980A CN 115836386 A CN115836386 A CN 115836386A
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additional
semiconductor device
unit
circuit
cell
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Pending
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CN202080102980.XA
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Chinese (zh)
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本间一郎
川越刚
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Ultramemory Inc
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Ultramemory Inc
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Publication of CN115836386A publication Critical patent/CN115836386A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0253—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01351—Changing the shapes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN202080102980.XA 2020-07-16 2020-07-16 半导体装置及其制造方法 Pending CN115836386A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/027728 WO2022014022A1 (ja) 2020-07-16 2020-07-16 半導体装置及びその製造方法

Publications (1)

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CN115836386A true CN115836386A (zh) 2023-03-21

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US (1) US20230282618A1 (https=)
JP (1) JPWO2022014022A1 (https=)
CN (1) CN115836386A (https=)
WO (1) WO2022014022A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250386478A1 (en) * 2024-06-14 2025-12-18 Intel Corporation Multi-layer conductive vias with etch-selective liners

Citations (8)

* Cited by examiner, † Cited by third party
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US20110133339A1 (en) * 2009-12-03 2011-06-09 Meng-Jen Wang Semiconductor Structure and Method for Making the Same
JP2011171567A (ja) * 2010-02-19 2011-09-01 Elpida Memory Inc 基板構造物の製造方法及び半導体装置の製造方法
JP2012227328A (ja) * 2011-04-19 2012-11-15 Sony Corp 半導体装置、半導体装置の製造方法、固体撮像装置及び電子機器
CN104412372A (zh) * 2012-06-29 2015-03-11 索尼公司 半导体装置、半导体装置的制造方法和电子设备
CN104718622A (zh) * 2012-10-18 2015-06-17 索尼公司 半导体装置、固体摄像装置和电子设备
CN104916619A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置及其制造方法
CN108573977A (zh) * 2017-03-10 2018-09-25 东芝存储器株式会社 半导体装置及其制造方法
CN110838481A (zh) * 2018-08-15 2020-02-25 台湾积体电路制造股份有限公司 用于堆叠集成电路的混合接合技术

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JP2006287211A (ja) * 2005-03-08 2006-10-19 Sharp Corp 半導体装置、積層半導体装置およびそれらの製造方法
CN105900233A (zh) * 2013-12-13 2016-08-24 Wow研究中心有限公司 半导体装置及其制造方法
JP6391999B2 (ja) * 2014-06-13 2018-09-19 株式会社ディスコ 積層デバイスの製造方法
KR102515965B1 (ko) * 2016-04-29 2023-03-31 에스케이하이닉스 주식회사 Tsv 구조체를 갖는 적층형 이미지 센서
WO2020108387A1 (en) * 2018-11-28 2020-06-04 Changxin Memory Technologies, Inc. Semiconductor device, fabrication method thereof, package and fabrication method thereof
WO2020229914A1 (ja) * 2019-05-10 2020-11-19 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
KR102751538B1 (ko) * 2019-11-27 2025-01-10 삼성전자주식회사 반도체 패키지
KR102729133B1 (ko) * 2019-12-02 2024-11-14 삼성전자주식회사 반도체 패키지
KR102789025B1 (ko) * 2019-12-16 2025-04-01 삼성전기주식회사 전자부품 내장기판
KR102822691B1 (ko) * 2020-06-05 2025-06-20 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110133339A1 (en) * 2009-12-03 2011-06-09 Meng-Jen Wang Semiconductor Structure and Method for Making the Same
JP2011171567A (ja) * 2010-02-19 2011-09-01 Elpida Memory Inc 基板構造物の製造方法及び半導体装置の製造方法
JP2012227328A (ja) * 2011-04-19 2012-11-15 Sony Corp 半導体装置、半導体装置の製造方法、固体撮像装置及び電子機器
CN104412372A (zh) * 2012-06-29 2015-03-11 索尼公司 半导体装置、半导体装置的制造方法和电子设备
CN104718622A (zh) * 2012-10-18 2015-06-17 索尼公司 半导体装置、固体摄像装置和电子设备
CN104916619A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置及其制造方法
CN108573977A (zh) * 2017-03-10 2018-09-25 东芝存储器株式会社 半导体装置及其制造方法
CN110838481A (zh) * 2018-08-15 2020-02-25 台湾积体电路制造股份有限公司 用于堆叠集成电路的混合接合技术

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JPWO2022014022A1 (https=) 2022-01-20
US20230282618A1 (en) 2023-09-07

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Application publication date: 20230321