JPWO2022014022A1 - - Google Patents

Info

Publication number
JPWO2022014022A1
JPWO2022014022A1 JP2022536078A JP2022536078A JPWO2022014022A1 JP WO2022014022 A1 JPWO2022014022 A1 JP WO2022014022A1 JP 2022536078 A JP2022536078 A JP 2022536078A JP 2022536078 A JP2022536078 A JP 2022536078A JP WO2022014022 A1 JPWO2022014022 A1 JP WO2022014022A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2022536078A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2022014022A1 publication Critical patent/JPWO2022014022A1/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0253—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01351—Changing the shapes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
JP2022536078A 2020-07-16 2020-07-16 Pending JPWO2022014022A1 (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/027728 WO2022014022A1 (ja) 2020-07-16 2020-07-16 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
JPWO2022014022A1 true JPWO2022014022A1 (https=) 2022-01-20

Family

ID=79554623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022536078A Pending JPWO2022014022A1 (https=) 2020-07-16 2020-07-16

Country Status (4)

Country Link
US (1) US20230282618A1 (https=)
JP (1) JPWO2022014022A1 (https=)
CN (1) CN115836386A (https=)
WO (1) WO2022014022A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250386478A1 (en) * 2024-06-14 2025-12-18 Intel Corporation Multi-layer conductive vias with etch-selective liners

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006287211A (ja) * 2005-03-08 2006-10-19 Sharp Corp 半導体装置、積層半導体装置およびそれらの製造方法
US20110133339A1 (en) * 2009-12-03 2011-06-09 Meng-Jen Wang Semiconductor Structure and Method for Making the Same
JP2011171567A (ja) * 2010-02-19 2011-09-01 Elpida Memory Inc 基板構造物の製造方法及び半導体装置の製造方法
JP2012227328A (ja) * 2011-04-19 2012-11-15 Sony Corp 半導体装置、半導体装置の製造方法、固体撮像装置及び電子機器
WO2014002852A1 (ja) * 2012-06-29 2014-01-03 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
JP2014099582A (ja) * 2012-10-18 2014-05-29 Sony Corp 固体撮像装置
WO2015087450A1 (ja) * 2013-12-13 2015-06-18 株式会社Ｗｏｗリサーチセンター 半導体装置及びその製造方法
JP2015176958A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置及びその製造方法
JP2016004835A (ja) * 2014-06-13 2016-01-12 株式会社ディスコ 積層デバイスの製造方法
US20200058617A1 (en) * 2018-08-15 2020-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding technology for stacking integrated circuits

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102515965B1 (ko) * 2016-04-29 2023-03-31 에스케이하이닉스 주식회사 Tsv 구조체를 갖는 적층형 이미지 센서
JP2018152412A (ja) * 2017-03-10 2018-09-27 東芝メモリ株式会社 半導体装置及びその製造方法
WO2020108387A1 (en) * 2018-11-28 2020-06-04 Changxin Memory Technologies, Inc. Semiconductor device, fabrication method thereof, package and fabrication method thereof
WO2020229914A1 (ja) * 2019-05-10 2020-11-19 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
KR102751538B1 (ko) * 2019-11-27 2025-01-10 삼성전자주식회사 반도체 패키지
KR102729133B1 (ko) * 2019-12-02 2024-11-14 삼성전자주식회사 반도체 패키지
KR102789025B1 (ko) * 2019-12-16 2025-04-01 삼성전기주식회사 전자부품 내장기판
KR102822691B1 (ko) * 2020-06-05 2025-06-20 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006287211A (ja) * 2005-03-08 2006-10-19 Sharp Corp 半導体装置、積層半導体装置およびそれらの製造方法
US20110133339A1 (en) * 2009-12-03 2011-06-09 Meng-Jen Wang Semiconductor Structure and Method for Making the Same
JP2011171567A (ja) * 2010-02-19 2011-09-01 Elpida Memory Inc 基板構造物の製造方法及び半導体装置の製造方法
JP2012227328A (ja) * 2011-04-19 2012-11-15 Sony Corp 半導体装置、半導体装置の製造方法、固体撮像装置及び電子機器
WO2014002852A1 (ja) * 2012-06-29 2014-01-03 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
JP2014099582A (ja) * 2012-10-18 2014-05-29 Sony Corp 固体撮像装置
WO2015087450A1 (ja) * 2013-12-13 2015-06-18 株式会社Ｗｏｗリサーチセンター 半導体装置及びその製造方法
JP2015176958A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置及びその製造方法
JP2016004835A (ja) * 2014-06-13 2016-01-12 株式会社ディスコ 積層デバイスの製造方法
US20200058617A1 (en) * 2018-08-15 2020-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding technology for stacking integrated circuits

Also Published As

Publication number Publication date
WO2022014022A1 (ja) 2022-01-20
CN115836386A (zh) 2023-03-21
US20230282618A1 (en) 2023-09-07

Similar Documents

Publication Publication Date Title
BR112023005462A2 (https=)
BR112023012656A2 (https=)
BR112021014123A2 (https=)
BR112023009656A2 (https=)
BR112022009896A2 (https=)
BR112021017747A2 (https=)
BR112022024743A2 (https=)
BR112022026905A2 (https=)
BR112023011738A2 (https=)
BR112023004146A2 (https=)
BR112023006729A2 (https=)
BR102021018859A2 (https=)
JPWO2022014022A1 (https=)
BR112023016292A2 (https=)
BR112023011539A2 (https=)
BR112023011610A2 (https=)
BR112023008976A2 (https=)
BR102021020147A2 (https=)
BR102021018926A2 (https=)
BR102021018167A2 (https=)
BR102021017576A2 (https=)
BR102021016837A2 (https=)
BR102021016551A2 (https=)
BR102021016375A2 (https=)
BR102021016200A2 (https=)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20221202

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230905

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231018

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20240116

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20240702