CN1157779C - 一种处理装入智能插卡的削薄的芯片的方法 - Google Patents

一种处理装入智能插卡的削薄的芯片的方法 Download PDF

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Publication number
CN1157779C
CN1157779C CNB008072833A CN00807283A CN1157779C CN 1157779 C CN1157779 C CN 1157779C CN B008072833 A CNB008072833 A CN B008072833A CN 00807283 A CN00807283 A CN 00807283A CN 1157779 C CN1157779 C CN 1157779C
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smart card
chip
adhesive layer
foil
adhesive
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Expired - Fee Related
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Chinese (zh)
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CN1350701A (zh
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托马斯·格拉斯尔
̩
亚亚·哈吉里-泰拉尼
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Giesecke and Devrient GmbH
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    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448Located on chip prior to dicing and remaining on chip after dicing
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Credit Cards Or The Like (AREA)
CNB008072833A 1999-05-07 2000-05-04 一种处理装入智能插卡的削薄的芯片的方法 Expired - Fee Related CN1157779C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19921230.9 1999-05-07
DE19921230A DE19921230B4 (de) 1999-05-07 1999-05-07 Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten

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CN1350701A CN1350701A (zh) 2002-05-22
CN1157779C true CN1157779C (zh) 2004-07-14

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EP (1) EP1183726A1 (enExample)
JP (1) JP2002544669A (enExample)
CN (1) CN1157779C (enExample)
AU (1) AU4561200A (enExample)
DE (1) DE19921230B4 (enExample)
WO (1) WO2000068990A1 (enExample)

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JP2004273895A (ja) * 2003-03-11 2004-09-30 Disco Abrasive Syst Ltd 半導体ウエーハの分割方法
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DE10341186A1 (de) * 2003-09-06 2005-03-31 Martin Michalk Verfahren und Vorrichtung zum Kontaktieren von Halbleiterchips
GB2412786A (en) * 2004-03-24 2005-10-05 E2V Tech Uk Ltd Method and apparatus for manufacturing chip scale components or microcomponents
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DE102004036962A1 (de) * 2004-07-30 2006-03-23 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von Halbleiterchips in Dünnfilmtechnik und Halbleiterchip in Dünnfilmtechnik
US8728937B2 (en) 2004-07-30 2014-05-20 Osram Opto Semiconductors Gmbh Method for producing semiconductor chips using thin film technology
EP1774599B1 (de) 2004-07-30 2015-11-04 OSRAM Opto Semiconductors GmbH Verfahren zur herstellung von halbleiterchips in dünnfilmtechnik und halbleiterchip in dünnfilmtechnik
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EP1183726A1 (de) 2002-03-06
JP2002544669A (ja) 2002-12-24
DE19921230B4 (de) 2009-04-02
AU4561200A (en) 2000-11-21
CN1350701A (zh) 2002-05-22
DE19921230A1 (de) 2000-11-09
WO2000068990A1 (de) 2000-11-16

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