DE19921230B4 - Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten - Google Patents

Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten Download PDF

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Publication number
DE19921230B4
DE19921230B4 DE19921230A DE19921230A DE19921230B4 DE 19921230 B4 DE19921230 B4 DE 19921230B4 DE 19921230 A DE19921230 A DE 19921230A DE 19921230 A DE19921230 A DE 19921230A DE 19921230 B4 DE19921230 B4 DE 19921230B4
Authority
DE
Germany
Prior art keywords
chip
adhesive layer
chip card
wafer
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19921230A
Other languages
German (de)
English (en)
Other versions
DE19921230A1 (de
Inventor
Thomas Grassl
Yahya Haghiri Tehrani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Giesecke and Devrient GmbH
Original Assignee
Giesecke and Devrient GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giesecke and Devrient GmbH filed Critical Giesecke and Devrient GmbH
Priority to DE19921230A priority Critical patent/DE19921230B4/de
Priority to PCT/EP2000/003988 priority patent/WO2000068990A1/de
Priority to AU45612/00A priority patent/AU4561200A/en
Priority to EP00927133A priority patent/EP1183726A1/de
Priority to CNB008072833A priority patent/CN1157779C/zh
Priority to JP2000617491A priority patent/JP2002544669A/ja
Publication of DE19921230A1 publication Critical patent/DE19921230A1/de
Application granted granted Critical
Publication of DE19921230B4 publication Critical patent/DE19921230B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448Located on chip prior to dicing and remaining on chip after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01005Boron [B]
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01013Aluminum [Al]
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    • H01L2924/0102Calcium [Ca]
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    • H01L2924/01029Copper [Cu]
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    • H01L2924/01047Silver [Ag]
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    • H01L2924/01082Lead [Pb]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Credit Cards Or The Like (AREA)
DE19921230A 1999-05-07 1999-05-07 Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten Expired - Fee Related DE19921230B4 (de)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE19921230A DE19921230B4 (de) 1999-05-07 1999-05-07 Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten
PCT/EP2000/003988 WO2000068990A1 (de) 1999-05-07 2000-05-04 Verfahren zum handhaben von gedünnten chips zum einbringen in chipkarten
AU45612/00A AU4561200A (en) 1999-05-07 2000-05-04 Method for handling thinned chips for introducing them into chip cards
EP00927133A EP1183726A1 (de) 1999-05-07 2000-05-04 Verfahren zum handhaben von gedünnten chips zum einbringen in chipkarten
CNB008072833A CN1157779C (zh) 1999-05-07 2000-05-04 一种处理装入智能插卡的削薄的芯片的方法
JP2000617491A JP2002544669A (ja) 1999-05-07 2000-05-04 スマートカードに組み込むための薄化チップ取扱方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19921230A DE19921230B4 (de) 1999-05-07 1999-05-07 Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten

Publications (2)

Publication Number Publication Date
DE19921230A1 DE19921230A1 (de) 2000-11-09
DE19921230B4 true DE19921230B4 (de) 2009-04-02

Family

ID=7907399

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19921230A Expired - Fee Related DE19921230B4 (de) 1999-05-07 1999-05-07 Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten

Country Status (6)

Country Link
EP (1) EP1183726A1 (enExample)
JP (1) JP2002544669A (enExample)
CN (1) CN1157779C (enExample)
AU (1) AU4561200A (enExample)
DE (1) DE19921230B4 (enExample)
WO (1) WO2000068990A1 (enExample)

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FR2823012B1 (fr) * 2001-04-03 2004-05-21 Commissariat Energie Atomique Procede de transfert selectif d'au moins un element d'un support initial sur un support final
DE10117880B4 (de) * 2001-04-10 2009-01-29 Mühlbauer Ag Verfahren zum Vereinzeln von elektronischen Bauteilen aus einem Verbund
US6964086B2 (en) * 2002-03-04 2005-11-15 Matsushita Electric Industrial Co., Ltd. Method of manufacturing thin film piezoelectric element, and element housing jig
US6943056B2 (en) * 2002-04-16 2005-09-13 Renesas Technology Corp. Semiconductor device manufacturing method and electronic equipment using same
JP2004273895A (ja) * 2003-03-11 2004-09-30 Disco Abrasive Syst Ltd 半導体ウエーハの分割方法
DE10339559B4 (de) * 2003-08-26 2006-03-02 W.C. Heraeus Gmbh Verfahren zur Lagebestimmung von Bauelementträgern
DE10341186A1 (de) * 2003-09-06 2005-03-31 Martin Michalk Verfahren und Vorrichtung zum Kontaktieren von Halbleiterchips
GB2412786A (en) * 2004-03-24 2005-10-05 E2V Tech Uk Ltd Method and apparatus for manufacturing chip scale components or microcomponents
EP1782455A4 (en) * 2004-07-09 2013-07-10 Semiconductor Energy Lab IC-CHIP AND PROCESS FOR ITS MANUFACTURE
US8728937B2 (en) 2004-07-30 2014-05-20 Osram Opto Semiconductors Gmbh Method for producing semiconductor chips using thin film technology
DE102004036962A1 (de) * 2004-07-30 2006-03-23 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von Halbleiterchips in Dünnfilmtechnik und Halbleiterchip in Dünnfilmtechnik
WO2006012838A2 (de) 2004-07-30 2006-02-09 Osram Opto Semiconductors Gmbh Verfahren zur herstellung von halbleiterchips in dünnfilmtechnik und halbleiterchip in dünnfilmtechnik
FR2878076B1 (fr) * 2004-11-17 2007-02-23 St Microelectronics Sa Amincissement d'une plaquette semiconductrice
DE102004059599B3 (de) * 2004-12-09 2006-08-17 Infineon Technologies Ag Verfahren zum Aufbringen einer Klebstoffschicht auf dünngeschliffene Halbleiterchips eines Halbleiterwafers
DE102006032821B4 (de) * 2006-07-14 2008-04-10 Mühlbauer Ag Verfahren und Vorrichtung zur Herstellung einer Vielzahl von Chipkarten mit einer klebstofffreien Fixierung der Chipmodule
JP5248518B2 (ja) * 2006-11-24 2013-07-31 フラウンホッファー−ゲゼルシャフト・ツァー・フォデラング・デル・アンゲワンテン・フォーシュング・エー.ファウ. 電子、特に微細電子機能群とその製造方法
JP4958287B2 (ja) * 2007-05-30 2012-06-20 東京応化工業株式会社 剥がし装置における剥離方法
DE102010025774A1 (de) 2010-07-01 2012-01-05 Giesecke & Devrient Gmbh Verfahren zur Herstellung eines Inlays für einen tragbaren Datenträger und Inlay
JP6417164B2 (ja) * 2014-09-18 2018-10-31 芝浦メカトロニクス株式会社 積層体製造装置、積層体、分離装置及び積層体製造方法
CN114334678A (zh) * 2020-09-30 2022-04-12 日月光半导体制造股份有限公司 形成半导体封装结构的方法

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US4722130A (en) * 1984-11-07 1988-02-02 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
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EP1183726A1 (de) 2002-03-06
JP2002544669A (ja) 2002-12-24
CN1350701A (zh) 2002-05-22
CN1157779C (zh) 2004-07-14
AU4561200A (en) 2000-11-21
DE19921230A1 (de) 2000-11-09
WO2000068990A1 (de) 2000-11-16

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