CN115565979A - 一种半导体晶体管结构及制作方法 - Google Patents

一种半导体晶体管结构及制作方法 Download PDF

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CN115565979A
CN115565979A CN202110749993.2A CN202110749993A CN115565979A CN 115565979 A CN115565979 A CN 115565979A CN 202110749993 A CN202110749993 A CN 202110749993A CN 115565979 A CN115565979 A CN 115565979A
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汤继峰
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Changxin Memory Technologies Inc
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Abstract

本申请公开了一种半导体晶体管结构，包括：形成有第一导电类型阱区的衬底，在所述衬底上设置有栅极结构；第二导电类型的源漏区，设置于所述第一导电类型阱区内,且源漏区分别位于栅极结构的两侧；在源漏区相对应的位置处开设有接触孔，所述接触孔向下延伸至第一导电类型阱区中；所述接触孔内填充有导电金属，接触孔底部有注入用于降低其接触电阻的杂质离子，所述接触孔底部与所述源漏区相接触的周边区域的杂质离子浓度低于其位于中间区域杂质离子的浓度。本申请通过在填充接触孔时，保持接触孔底部与源/漏区相接触的周边区域处的杂质离子浓度低于其中间区域杂质离子的浓度，以此来降低源漏区与阱区之间的离子浓度差，从而减小漏电流。

Description

一种半导体晶体管结构及制作方法
技术领域
本申请涉及半导体集成电路的技术领域，尤其涉及一种半导体晶体管结构及制作方法。
背景技术
金氧半导体晶体管(metal-oxide semiconductor transistor，MOS transistor)是现今半导体产品中相当重要的电子元件，其电性表现是关系到集成电路品质好坏的关键。MOS晶体管是由栅极、源极、漏极以及衬底所构成的四端点电子元件，栅极结构和衬底之间有一层氧化物绝缘层。当MOS晶体管工作时，通过对栅极施加一工作电压，使衬底靠近氧化物绝缘层那一侧形成反型沟道，由于源、漏极也是反型掺杂，进而导通源极与漏极，并藉此达到控制晶体管开关的运作目的。
目前MOSFET源漏区域形成之后，在源漏区通过光刻掩膜打开特定区域，进行刻蚀，形成接触孔，再在接触孔内沉积导电材料。现在的工艺流程为了降低接触孔的接触电阻,通常会在接触孔沉积导电材料之前，源漏区掺杂之后，向接触孔底部再注入一道杂质离子进行同类型的离子掺杂叠加(低浓度的掺杂，通常在源漏掺杂浓度的十分之一)如此一来会增加源漏区杂质离子的掺杂浓度，源漏区和衬底之间会形成离子浓度差更大的PN结，对源漏区施加电压的话，更易使PN结导通，从而产生漏电流，另外在接触孔的底部拐角或者尖端的地方，会形成较高的电场强度,在尖端电场的影响下,会加强PN结的漏电流，漏电对器件的性能影响非常大，因此需要提出一种新型MOS晶体管结构及制作方法减小漏电流。
发明内容
(一)发明目的
本申请的目的是提供一种半导体晶体管结构，为解决现有半导体晶体管中因接触孔掺杂导致的源漏区与衬底之间漏电流的问题，通过使接触孔底部与源漏区相接触的周边区域的杂质离子浓度低于其位于中间区域杂质离子的浓度，在保证接触孔垂直方向阻值不变的情况下来降低源漏区与衬底之间的离子浓度差，从而减小漏电流。
(二)技术方案
为解决上述技术问题，本申请的第一方面提供了一种半导体晶体管结构，其特征在于，包括：形成有第一导电类型阱区的衬底，在所述衬底上设置有栅极结构；第二导电类型的源区/漏区，设置于所述第一导电类型阱区内,且源区与漏区分别位于栅极结构的两侧；在源区/漏区相对应的位置处开设有接触孔，所述接触孔向下延伸至第一导电类型阱区中；所述接触孔内填充有导电金属，接触孔底部有注入用于降低其接触电阻的杂质离子，所述接触孔底部与所述源区/漏区相接触的周边区域的杂质离子浓度低于其位于中间区域杂质离子的浓度。
通过采用上述技术方案，在往接触孔内填充杂质离子的时候，保持接触孔底部与源漏区相接触的周边区域的杂质离子浓度低于中间区域杂质离子的浓度，在保证接触孔内垂直方向的阻值不变的情况下，降低源漏区与衬底之间的离子浓度差，从而减小漏电流，同时也降低了接触孔底部与源漏区相接触的周边区域位置处的电场强度，在对源漏区施加电压时，可以减小PN结漏电流。
优选的是，在所述接触孔底部与所述源/漏区相接触的周边区域填充有用于中和杂质离子浓度的反型离子。
优选的是，所述反型离子的注射能量是15KeV,注射剂量是5e13 atom,所述反型离子选自磷离子、砷离子和锑离子中的任意一种。
优选的是，所述杂质离子的注射能量是2～3KeV,注射剂量是8E14～1E15atom,所述杂质离子选自硼离子、铝离子和铟离子中的任意一种。
优选的是，所述第一导电类型阱区为N型掺杂，掺杂离子选自磷离子、砷离子和锑离子中的任意一种；所述第二导电类型的源区/漏区为P型掺杂，掺杂离子选自硼离子、铝离子和铟离子中的任意一种。
优选的是，所述接触孔的导电金属包括金属硅化物和金属材料。
优选的是，所述金属材料包括钨、铝、钼。
优选的是，所述接触孔向下延伸的深度是20-50nm。
优选的是，所述栅极结构包括依次叠加设置于第一导电类型阱区上的介质层、多晶硅导电层、绝缘氮化硅层以及氧化硅层。
本申请的第二方面提供了一种半导体晶体管的制作方法，包括形成有第一导电类型阱区的衬底；在所述第一导电类型阱区表面区域形成栅极结构；在所述栅极结构两侧的所述第一导电类型阱区内分别形成第二导电类型的源区和漏区；在所述源区/漏区处分别形成接触孔；在所述接触孔底部的中间区域形成具有杂质离子的高浓度区，在所述接触孔底部与所述源区/漏区相接触的周边区域形成具有杂质离子的低浓度区；在所述接触孔内沉积导电层，形成导电接触。
优选的是，在所述接触孔的中间区域形成具有杂质离子的高浓度区包括：往接触孔内垂直注入杂质离子，使其填充接触孔底部区域，再通过RTP激活，使其通过接触孔底部向源区/漏区扩散。
优选的是，在所述接触孔底部与所述源区/漏区相接触的周边区域形成具有杂质离子的低浓度区包括：往接触孔内注入反型离子，使反型离子均匀分布于接触孔底部与所述源区/漏区相接触的周边区域。
优先的是，所述反型离子采用倾斜注入的方式，其角度是8-12度。
优先的是，在所述接触孔内沉积导电层，形成导电接触包括：在接触孔内溅射沉积金属钴，再热氧化，使钴和源区/漏区的硅反应，形成金属硅化物；然后沉积金属材料，填充接触孔，形成导电层。
(三)有益效果
本申请的上述技术方案具有如下有益的技术效果：通过往接触孔内填充杂质离子，保持接触孔底部与源漏区相接触的周边区域处的杂质离子浓度低于中间区域杂质离子的浓度，在保证接触孔内垂直方向的阻值不变的情况下，来降低源漏区与衬底之间的离子浓度差，从而减小漏电流，提高器件的使用性能。
附图说明
图1是本申请实施例的全剖结构示意图；
图2是本申请实施例MOS晶体管结构的形成方法流程图；
图3-图8是本申请具体实施方式在形成MOS晶体管结构的过程中主要的工艺截面示意图。
附图标记：
1、衬底；11、第一导电类型阱区；2、栅极结构；21、介质层；22、多晶硅栅层；221、第一侧外部；222、第二侧外部；23、绝缘氮化硅层；24、氧化硅层；3、源区；4、漏区；5、杂质离子；6、反型离子；7、金属硅化物；8、金属材料。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本发明进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本发明的范围。
如图1所示，本具体实施方式提供了一种半导体晶体管结构，包括：衬底1，在衬底1的表面区域形成有第一导电类型阱区11，所述第一导电类型阱区11为N型掺杂，掺杂离子选自磷离子、砷离子和锑离子中的任意一种。可选的，衬底1为硅衬底。
在第一导电类型阱区11的表面上设置有栅极结构2，栅极结构2包括介质层21和多晶硅栅层22，介质层21位于第一导电类型阱区11的表面上，介质层21的构成材料可以是诸如氧化铪、硅酸铪、氧化镧、氧化锌、硅酸锌、氧化钽、氧化钛、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、铁电薄膜、铌锌酸、铅钛酸铅这样的高k材料中的一种。多晶硅栅层22设置于介质层21上，多晶硅栅层22的构成材料例如可以包含多晶硅、铪、钛、钽、铝、锆、钌、钯、铂、钴、镍及其氧化物和碳化物中的一种或多种。
在第一导电类型阱区11表面内形成有第二导电类型掺杂的源区3和漏区4，源区3和漏区4对称设置于介质层21的两侧。所述源区3和漏区4可以通过对第一导电类型阱区11表面中位于栅极结构2两侧的区域进行反型离子注入而形成。源区3和漏区4中所掺杂的导电离子的类型由其形成的具体半导体器件类型决定。本申请实施例中为PMOS器件，则源漏区是P型掺杂，掺杂离子选自硼离子、铝离子和铟离子中的任意一种。
源区3/漏区4相对应的位置区域刻蚀有接触孔111，接触孔111向下延伸至第一导电类型阱区11中，接触孔111向下延伸的深度是20-50nm。在接触孔111底部区域掺杂有杂质离子5，杂质离子5选自硼离子、铝离子和铟离子中的任意一种，在本实施例中以硼离子为例进行说明。通过快速退火工艺(Rapid thermal processing,RTP)激活硼离子，使硼离子在接触孔111底部区域进行扩散，以此来降低接触孔111的接触阻值。
在接触孔111底部与源区3/漏区4相接触的周边区域填充有反型离子6，反型离子6用于中和硼离子，反型离子6选自磷离子、砷离子和锑离子中的任意一种，在本实施例中以磷离子为例进行说明。加入磷离子后使得位于所述接触孔111底部与源区3/漏区4相接触的周边区域的多数载流子硼离子浓度要低于其位于中间区域硼离子的浓度，在不影响接触孔111垂直方向的阻值的情况下，来降低源区3/漏区4与第一导电类型阱区11之间的离子浓度差，从而减小漏电流。
附图2是本申请中MOS晶体管结构的形成方法流程图；
附图3-8是本申请中在形成MOS晶体管结构过程中主要的工艺截面示意图。
本申请还提供了一种半导体晶体管结构的制作方法，包括如下步骤：
步骤S11，第一导电类型阱区形成，如图2、3所示，
具体来说，提供一P型的衬底1，采用离子注入的方式，对P型的衬底1进行N型掺杂，以此方式，形成N型的第一导电类型阱区11。可选的，所述衬底1的具体材料，本领域技术人员可以根据实际需要进行选择，本具体实施方式以所述衬底1的材料为硅衬底为例进行说明。
步骤S12，形成覆盖所述第一导电类型阱区的介质层，如图2、4所示，
具体来说，采用热氧化工艺在所述衬底1的第一导电类型阱区11表面上沉积介质层21，使得介质层21覆盖所述第一导电类型阱区11表面区域。其中，所述介质层21的材料为绝缘材料，其具体类型本领域技术人员可以根据实际需要进行选择。所述介质层21的厚度可以根据需要进行设置，较佳的厚度可以为30～50埃。
步骤S13，形成位于介质层上的多晶硅栅层，如图2、4所示，
具体来说，将包括介质层21的半导体晶片转入低压化学气相淀积设备，并在设备的工艺腔中通入硅烷，硅烷分解后，多晶硅淀积在介质层21表面。在多晶硅淀积完成后，还可以进行多晶硅掺杂操作。在光刻胶层中，通过曝光和显影工序后形成栅区图形，并以光刻胶层为掩模，通过腐蚀工艺去除栅区图形外部的介质层21和多晶硅层，形成多晶硅栅层22。
步骤S14，形成位于多晶硅栅层上的绝缘层，如图2、5所示，
在图中，通过化学气相沉积形成覆盖于多晶硅栅层22的顶部以及侧壁的绝缘氮化硅层23，顶部厚度一般在0.1μm～3μm，侧壁厚度一般在10nm～30nm之间。在绝缘氮化硅层23的基础上形成一层氧化硅层24，氧化硅层24延伸至绝缘氮化硅层23的侧面，即绝缘氮化硅层23被包裹在氧化硅层24内，防止栅极结构2在后续源漏区离子注入时受到影响，以及氧化硅层24侧边厚度定义出源漏区的位置，绝缘氮化硅层23/氧化硅层24同时作为自对准结构，用于后续的源漏区离子注入。
步骤S15，于第一导电类型阱区内形成漏区和源区，如图4、5所示，
具体来说，可以利用栅极结构2/氧化硅层24实现自对准，在第一导电类型阱区11表面且位于栅极结构2的左右两边会形成源漏形成区域，所述源漏注入时以氧化硅层24的两侧为自对准边界，将导电杂质通过离子注入方式同时注入到源/漏区形成区域中以形成源区3和漏区4.
步骤S16，于源区/漏区内形成接触孔，如图2、6所述。
具体来说，在漏区4表面形成具有图案的光刻胶层，然后，以该光刻胶层为掩膜，刻蚀位于多晶硅栅层22的第二侧外部222的漏区4表面区域，于漏区4表面区域形成暴露其内部的接触孔111。源区3内形成接触孔111的方式与漏区4内形成接触孔111的形成方式一致，在此不再进行一一阐述。蚀刻所采用的掩膜不限于本实施例中的光刻胶，还可以采用其他的掩膜技术，例如金属硬掩膜等。
步骤S17，于接触孔内填充杂质离子，如图2、7所示，
具体来说，采用离子注入的工艺方法对接触孔111内注入杂质离子5，较佳的为硼离子和其氟化物，因为硼离子质量较轻和易扩散，硼的氟化物可以减少硼的扩散，以及形成非晶化区，减少离子注入的隧道效应。采用快速热处理或高温退火的工艺方法对注入的离子进行激活处理使杂质离子5在接触孔111的底部进行扩散。较佳的杂质离子5采取垂直注入的方式，注射能量是2～3KeV,注射剂量是8E14～1E15atom。
步骤S18，于所述接触孔底部拐角位置处注入反型离子，如图2、7所示，
具体来说，采用往接触孔111内注入反型离子6，较佳的为磷离子，反型离子6用来中和杂质离子5，具体为采用带角度的倾斜注入，使反型离子6均匀分布在接触孔111底部与源区3/漏区4相接触的周边区域，在不影响接触孔111垂直方向的阻值的情况下，来降低源区3/漏区4与第一导电类型阱区11之间的离子浓度差，从而减小漏电流。较佳为，所述反型离子6的注入角度是8-12度，注射能量是15KeV,注射剂量是5e13atom。
步骤S19，于所述接触孔沉积导电层并形成导电接触，如图2、8所示，
具体来说，在源区3/漏区4的接触孔111内通过物理气相沉积或者离子溅射沉积金属钴，通过热处理使硅层与钴反应形成金属硅化物7，也即形成硅化钴层。在硅化钴层上通过低压化学气相沉积、快速热化学气相沉积等沉积金属材料8，填充接触孔(111)，形成导电层。可选的金属材料8可以是金属钨、铝和钼中的至少一种。
本具体实施方式提供的半导体晶体管结构及其制作方法，在不影响接触孔111内垂直方向的阻值的情况下，往接触孔111内倾斜注入一道反型离子6来中和杂质离子5，使反型离子6分布在接触孔111底部与源区3/漏区4相接触的周边区域，由此来降低源区3/漏区4与第一导电类型阱区11之间的离子浓度差，从而减小漏电流，提高器件的性能。
应当理解的是，本发明的上述具体实施方式仅仅用于示例性说明或解释本发明的原理，而不构成对本发明的限制。因此，在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。此外，本发明所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (14)

1.一种半导体晶体管结构，其特征在于，包括：
形成有第一导电类型阱区(11)的衬底(1)，在所述衬底(1)上设置有栅极结构(2)；
第二导电类型的源区(3)/漏区(4)，设置于所述第一导电类型阱区(1)内,且源区(3)与漏区(4)分别位于栅极结构(2)的两侧；
在源区(3)/漏区(4)相对应的位置处开设有接触孔(111)，所述接触孔(111)向下延伸至第一导电类型阱区(11)中；
所述接触孔(111)内填充有导电金属，接触孔(111)底部有注入用于降低其接触电阻的杂质离子(5)，所述接触孔(111)底部与所述源区(3)/漏区(4)相接触的周边区域的杂质离子(5)浓度低于其位于中间区域杂质离子(5)的浓度。
2.根据权利要求1所述的一种半导体晶体管结构，其特征在于，在所述接触孔(111)底部与所述源区(3)/漏区(4)相接触的周边区域填充有用于中和杂质离子(5)浓度的反型离子(6)。
3.根据权利要求2所述的一种半导体晶体管结构，其特征在于，所述反型离子(6)的注射能量是15KeV,注射剂量是5e13 atom,所述反型离子(6)选自磷离子、砷离子和锑离子中的任意一种。
4.根据权1所述的一种半导体晶体管结构，其特征在于,所述杂质离子(5)的注射能量是2～3KeV,注射剂量是8E14～1E15 atom,所述杂质离子(5)选自硼离子、铝离子和铟离子中的任意一种。
5.根据权利要求1所述的一种半导体晶体管结构，其特征在于，
所述第一导电类型阱区(11)为N型掺杂，掺杂离子选自磷离和砷离子和锑离子中的任意一种；
所述第二导电类型的源区(3)/漏区(4)为P型掺杂，掺杂离子选自硼离子、铝离子和铟离子中的任意一种。
6.根据权利要求1所述的一种半导体晶体管结构，其特征在于，所述接触孔(111)的导电金属包括金属硅化物(7)和金属材料(8)。
7.根据权利要求6所述的一种半导体晶体管结构，其特征在于，所述金属材料(8)包括钨、铝、钼。
8.根据权利要求1所述的一种半导体晶体管结构，其特征在于，所述接触孔(111)向下延伸的深度是20-50nm。
9.根据权利要求1所述的一种半导体晶体管结构，其特征在于，所述栅极结构(2)包括依次叠加设置于第一导电类型阱区(11)上的介质层(21)、多晶硅导电层(22)、绝缘氮化硅层(23)以及氧化硅层(24)。
10.一种半导体晶体管的制作方法，其特征在于，包括：
提供形成有第一导电类型阱区(11)的衬底(1)；
在所述第一导电类型阱区(11)表面区域形成栅极结构(2)；
在所述栅极结构(2)两侧的所述第一导电类型阱区(11)内分别形成第二导电类型的源区(3)/漏区(4)；
在所述源区(3)/漏区(4)处分别形成接触孔(111)；
在所述接触孔(111)底部的中间区域形成具有杂质离子(5)的高浓度区，在所述接触孔(111)底部与所述源区(3)/漏区(4)相接触的周边区域形成具有杂质离子(5)的低浓度区；
在所述接触孔(111)内沉积导电层，形成导电接触。
11.根据权利要求10所述的方法，其特征在于，在所述接触孔(111)的中间区域形成具有杂质离子(5)的高浓度区包括：
往接触孔(111)内垂直注入杂质离子(5)，使其填充接触孔(111)底部区域，再通过RTP激活，使其通过接触孔(111)底部向源区(3)/漏区(4)扩散。
12.根据权利要求10所述的方法，其特征在于，在所述接触孔(111)底部与所述源区(3)/漏区(4)相接触的周边区域形成具有杂质离子(5)的低浓度区包括：
往接触孔(111)内注入反型离子(6)，使反型离子(6)均匀分布于接触孔(111)底部与所述源区(3)/漏区(4)相接触的周边区域。
13.根据权利要求12所述的方法，其特征在于，所述反型离子(6)采用倾斜注入的方式，其角度是8-12度。
14.根据权利要求10所述的方法，其特征在于，在所述接触孔(111)内沉积导电层，形成导电接触包括：
在接触孔(111)内溅射沉积金属钴，再热氧化，使钴和源区(3)/漏区(4)的硅反应，形成金属硅化物(7)；然后沉积金属材料(8)，填充接触孔(111)，形成导电层。
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