CN1153349C - 多值逻辑电路体系结构:补充对称逻辑电路结构 - Google Patents

多值逻辑电路体系结构:补充对称逻辑电路结构 Download PDF

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Publication number
CN1153349C
CN1153349C CNB998079677A CN99807967A CN1153349C CN 1153349 C CN1153349 C CN 1153349C CN B998079677 A CNB998079677 A CN B998079677A CN 99807967 A CN99807967 A CN 99807967A CN 1153349 C CN1153349 C CN 1153349C
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input
logic
output
signal
circuit
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CN1307748A (zh
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埃德加・丹尼・奥尔森
埃德加·丹尼·奥尔森
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Integrated Base Logistics Co
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
CNB998079677A 1998-05-29 1999-05-21 多值逻辑电路体系结构:补充对称逻辑电路结构 Expired - Fee Related CN1153349C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/086,869 1998-05-29
US09/086,869 US6133754A (en) 1998-05-29 1998-05-29 Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)

Publications (2)

Publication Number Publication Date
CN1307748A CN1307748A (zh) 2001-08-08
CN1153349C true CN1153349C (zh) 2004-06-09

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CNB998079677A Expired - Fee Related CN1153349C (zh) 1998-05-29 1999-05-21 多值逻辑电路体系结构:补充对称逻辑电路结构

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US (1) US6133754A (enExample)
EP (1) EP1092267A1 (enExample)
JP (1) JP4427188B2 (enExample)
KR (1) KR100683235B1 (enExample)
CN (1) CN1153349C (enExample)
AU (1) AU750648B2 (enExample)
CA (1) CA2333623C (enExample)
WO (1) WO1999063669A1 (enExample)
ZA (1) ZA200007686B (enExample)

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RU2648565C1 (ru) * 2017-06-01 2018-03-26 Сергей Петрович Маслов Устройство троичной схемотехники на токовых зеркалах
KR101928223B1 (ko) 2017-12-29 2018-12-11 울산과학기술원 삼진 논리 회로 장치
CN109376867B (zh) * 2018-09-17 2021-05-07 合肥本源量子计算科技有限责任公司 两量子比特逻辑门的处理方法及装置
KR102130980B1 (ko) * 2018-12-31 2020-07-07 포항공과대학교 산학협력단 변조 퀸맥클러스키 알고리즘을 이용한 삼진 논리 합성 장치 및 방법
DE102019123555B4 (de) 2019-09-03 2022-12-01 Infineon Technologies Ag Physisch obfuskierter schaltkreis
CN112783472B (zh) * 2019-11-05 2023-12-12 何群 多值逻辑宽位高速加法器
CN111371448A (zh) * 2020-04-15 2020-07-03 联合华芯电子有限公司 一种实现多电平逻辑异或、比同运算的电路和方法
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KR20220145226A (ko) * 2021-04-21 2022-10-28 에스케이하이닉스 주식회사 다중 연산 회로와 이를 포함하는 곱셈-누적 오퍼레이터 및 프로세싱-인-메모리 장치
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Also Published As

Publication number Publication date
ZA200007686B (en) 2002-01-30
US6133754A (en) 2000-10-17
KR100683235B1 (ko) 2007-02-28
JP4427188B2 (ja) 2010-03-03
CN1307748A (zh) 2001-08-08
JP2002517937A (ja) 2002-06-18
CA2333623A1 (en) 1999-12-09
AU4407399A (en) 1999-12-20
CA2333623C (en) 2009-12-22
EP1092267A1 (en) 2001-04-18
KR20010082557A (ko) 2001-08-30
WO1999063669A1 (en) 1999-12-09
AU750648B2 (en) 2002-07-25

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