JP4427188B2 - 多値論理回路構成 - Google Patents

多値論理回路構成 Download PDF

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Publication number
JP4427188B2
JP4427188B2 JP2000552777A JP2000552777A JP4427188B2 JP 4427188 B2 JP4427188 B2 JP 4427188B2 JP 2000552777 A JP2000552777 A JP 2000552777A JP 2000552777 A JP2000552777 A JP 2000552777A JP 4427188 B2 JP4427188 B2 JP 4427188B2
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input
output
logic
circuit
signal
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JP2002517937A5 (enExample
JP2002517937A (ja
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エドガー ダニー オルソン
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オムニベイス ロジック インコーポレイテッド
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
JP2000552777A 1998-05-29 1999-05-21 多値論理回路構成 Expired - Fee Related JP4427188B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/086,869 US6133754A (en) 1998-05-29 1998-05-29 Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)
US09/086,869 1998-05-29
PCT/US1999/011349 WO1999063669A1 (en) 1998-05-29 1999-05-21 Multiple-valued logic circuit architecture: supplementary symmetrical logic circuit structure (sus-loc)

Publications (3)

Publication Number Publication Date
JP2002517937A JP2002517937A (ja) 2002-06-18
JP2002517937A5 JP2002517937A5 (enExample) 2006-06-29
JP4427188B2 true JP4427188B2 (ja) 2010-03-03

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JP2000552777A Expired - Fee Related JP4427188B2 (ja) 1998-05-29 1999-05-21 多値論理回路構成

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US (1) US6133754A (enExample)
EP (1) EP1092267A1 (enExample)
JP (1) JP4427188B2 (enExample)
KR (1) KR100683235B1 (enExample)
CN (1) CN1153349C (enExample)
AU (1) AU750648B2 (enExample)
CA (1) CA2333623C (enExample)
WO (1) WO1999063669A1 (enExample)
ZA (1) ZA200007686B (enExample)

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KR101928223B1 (ko) 2017-12-29 2018-12-11 울산과학기술원 삼진 논리 회로 장치
CN111371448A (zh) * 2020-04-15 2020-07-03 联合华芯电子有限公司 一种实现多电平逻辑异或、比同运算的电路和方法

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JP4288355B2 (ja) * 2006-01-31 2009-07-01 国立大学法人北陸先端科学技術大学院大学 三値論理関数回路
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US8975922B2 (en) * 2008-02-29 2015-03-10 California Institute Of Technology Method and apparatus for simultaneous processing of multiple functions
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JP5363511B2 (ja) * 2011-01-14 2013-12-11 利康 鈴木 多値論理回路
JP5249379B2 (ja) * 2011-03-29 2013-07-31 利康 鈴木 多値用双方向性スイッチング手段
US8847625B2 (en) * 2012-02-16 2014-09-30 Southern Methodist University Single clock distribution network for multi-phase clock integrated circuits
CN103973296B (zh) * 2013-01-29 2018-04-10 中国航空工业集团公司西安飞机设计研究所 一种基于时序逻辑的双座舱指令综合方法及其电路
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US9576244B2 (en) * 2013-09-03 2017-02-21 Roger Midmore Methods and systems of four-valued simulation
US9575951B2 (en) * 2013-09-03 2017-02-21 Roger Midmore Methods and systems of four valued analogical transformation operators used in natural language processing and other applications
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CN104320126A (zh) * 2014-11-14 2015-01-28 浙江工商大学 Qc变换bc21的电路单元
CN104320128A (zh) * 2014-11-14 2015-01-28 浙江工商大学 一种基于cmos的qbc23电路
CN104333370A (zh) * 2014-11-14 2015-02-04 浙江工商大学 基于四二值时钟的qbc20电路
CN104320127A (zh) * 2014-11-14 2015-01-28 浙江工商大学 一种qc转换为bc13的cmos电路单元
CN104579310A (zh) * 2014-11-14 2015-04-29 浙江工商大学 基于cmos的qb32模块电路单元
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RU2618901C1 (ru) * 2016-06-17 2017-05-11 Сергей Петрович Маслов Пороговый элемент троичной логики на токовых зеркалах
CN106847328B (zh) * 2016-12-23 2018-09-18 宁波大学 一种利用cnfet实现的三值2-9线地址译码器
CN108268240A (zh) * 2017-01-03 2018-07-10 胡五生 多值寄存器
RU2648565C1 (ru) * 2017-06-01 2018-03-26 Сергей Петрович Маслов Устройство троичной схемотехники на токовых зеркалах
CN109376867B (zh) * 2018-09-17 2021-05-07 合肥本源量子计算科技有限责任公司 两量子比特逻辑门的处理方法及装置
KR102130980B1 (ko) * 2018-12-31 2020-07-07 포항공과대학교 산학협력단 변조 퀸맥클러스키 알고리즘을 이용한 삼진 논리 합성 장치 및 방법
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CN112783472B (zh) * 2019-11-05 2023-12-12 何群 多值逻辑宽位高速加法器
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KR20220145226A (ko) * 2021-04-21 2022-10-28 에스케이하이닉스 주식회사 다중 연산 회로와 이를 포함하는 곱셈-누적 오퍼레이터 및 프로세싱-인-메모리 장치
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Publication number Priority date Publication date Assignee Title
KR101928223B1 (ko) 2017-12-29 2018-12-11 울산과학기술원 삼진 논리 회로 장치
CN111371448A (zh) * 2020-04-15 2020-07-03 联合华芯电子有限公司 一种实现多电平逻辑异或、比同运算的电路和方法

Also Published As

Publication number Publication date
JP2002517937A (ja) 2002-06-18
CA2333623A1 (en) 1999-12-09
KR20010082557A (ko) 2001-08-30
AU4407399A (en) 1999-12-20
CN1307748A (zh) 2001-08-08
KR100683235B1 (ko) 2007-02-28
WO1999063669A1 (en) 1999-12-09
CA2333623C (en) 2009-12-22
EP1092267A1 (en) 2001-04-18
ZA200007686B (en) 2002-01-30
US6133754A (en) 2000-10-17
CN1153349C (zh) 2004-06-09
AU750648B2 (en) 2002-07-25

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