CN115274657A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN115274657A
CN115274657A CN202210131715.5A CN202210131715A CN115274657A CN 115274657 A CN115274657 A CN 115274657A CN 202210131715 A CN202210131715 A CN 202210131715A CN 115274657 A CN115274657 A CN 115274657A
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Prior art keywords
dielectric
gate
gate stack
fill material
liner
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CN202210131715.5A
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陈亭纲
卢柏全
黄泰钧
徐志安
王捷平
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体器件包括：第一晶体管，具有第一栅极堆叠件和位于第一栅极堆叠件的相对侧上的第一源极/漏极区域；第二晶体管，具有第二栅极堆叠件和位于第二栅极堆叠件的相对侧上的第二源极/漏极区域；以及栅极隔离结构，将第一栅极堆叠件与第二栅极堆叠件分隔开。栅极隔离结构包括沿第一栅极堆叠件和第二栅极堆叠件的侧壁具有变化的厚度的介电衬垫以及位于介电衬垫上方的介电填充材料，其中，介电填充材料包括接缝。本申请的实施例还涉及形成半导体器件的方法。

Description

半导体器件及其形成方法
技术领域
本申请的实施例涉及半导体器件及其形成方法。
背景技术
半导体器件用于各种电子应用中，诸如例如，个人计算机、手机、数码相机和其它电子设备。半导体器件通常通过在半导体衬底上方依次沉积材料的绝缘层或介电层、导电层和半导体层以及使用光刻图案化各个材料层以在其上形成电路组件和元件来制造。
半导体工业通过不断减小最小部件尺寸来不断提高各个电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多的组件集成至给定区域中。
发明内容
本申请的一些实施例提供了一种半导体器件，包括：第一晶体管，具有第一栅极堆叠件和位于所述第一栅极堆叠件的相对侧上的第一源极/漏极区域；第二晶体管，具有第二栅极堆叠件和位于所述第二栅极堆叠件的相对侧上的第二源极/漏极区域；栅极隔离结构，将所述第一栅极堆叠件与所述第二栅极堆叠件分隔开，其中，所述栅极隔离结构包括：介电衬垫，沿所述第一栅极堆叠件和所述第二栅极堆叠件的侧壁具有变化的厚度；以及介电填充材料，位于所述介电衬垫上方，其中，所述介电填充材料包括接缝。
本申请的另一些实施例提供了一种半导体器件，包括：第一栅极堆叠件，位于层间电介质中；第二栅极堆叠件，位于所述层间电介质中；以及栅极隔离结构，位于所述第一栅极堆叠件和所述第二栅极堆叠件之间，其中，所述栅极隔离结构接触所述第一栅极堆叠件的侧壁和所述第二栅极堆叠件的侧壁，其中，所述栅极隔离结构包括：介电衬垫，其中，所述介电衬垫的第一横向尺寸小于所述介电衬垫的第二横向尺寸，其中，所述介电衬垫的所述第一横向尺寸在所述层间电介质的顶面的水平面处测量，其中，所述介电衬垫的所述第二横向尺寸在所述层间电介质的底面的水平面处测量；以及介电填充材料，位于所述介电衬垫上方，其中，所述介电填充材料包括接缝。
本申请的又一些实施例提供了一种形成半导体器件的方法，包括：图案化延伸穿过伪栅极堆叠件的开口；在所述开口的侧壁和底面上沉积介电衬垫，其中，沉积所述介电衬垫包括非共形沉积工艺；在所述介电衬垫上方的所述开口中沉积介电填充材料，其中，沉积所述介电填充材料包括与沉积所述介电衬垫不同类型的沉积工艺，并且其中，沉积所述介电填充材料包括在所述介电填充材料中形成接缝；去除所述伪栅极堆叠件；以及在所述介电衬垫的相对侧上形成第一栅极堆叠件和第二栅极堆叠件。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的三维视图中的FinFET的实例。
图2、图3、图4、图5、图6、图7、图8A、图8B、图9A、图9B、图10A、图10B、图10C、图10D、图11A、图11B、图12A、图12B、图13A、图13B、图13C、图14A、图14B、图15A、图15B、图16A、图16B、图17A、图17B、图17C、图18A、图18B、图19A、图19B、图19C、图19D、图19E、图19F、图20A、图20B、图21A、图21B、图22A和图22B是根据一些实施例的在FinFET的制造中的中间阶段的截面图。
图23A和图23B是根据一些实施例的FinFET的截面图。
图24A和图24B是根据一些实施例的FinFET的截面图。
图25A和图25B是根据一些实施例的FinFET的截面图。
图26示出了根据一些实施例的NSFET的立体图。
图27A和图27B是根据一些实施例的NSFET的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
在各个实施例中，实施栅极切割工艺以将相邻的伪栅极分隔开并且限定替换栅极堆叠件的图案。作为栅极切割工艺的一部分，蚀刻伪栅极以限定开口，并且在开口中形成栅极隔离结构。栅极隔离结构可以包括介电衬垫(有时称为间隔件)，其使用非共形沉积工艺来沉积为具有锥形轮廓，并且栅极隔离结构还可以包括沉积在介电衬垫上方的介电填充材料。通过在介电衬垫中保持锥形轮廓，开口的顶部处的宽度可以保持相对较大，并且改进了介电填充材料的沉积窗口。因此，介电填充材料可以形成为具有较少的制造误差，诸如减少的接缝/空隙。接缝/空隙的尺寸/数量的减少可以进一步减少电缺陷(例如，短路)，该电缺陷可能是由于在随后的处理步骤期间(例如，在栅极或源极/漏极接触件的形成期间)导电材料被无意地捕获在暴露的接缝中而导致的。
图1示出了根据一些实施例的三维视图中的FinFET的实例。FinFET包括衬底50(例如，半导体衬底)上的鳍52。隔离区域56设置在衬底50中，并且鳍52突出至相邻隔离区域56之上并且从相邻隔离区域56之间突出。虽然隔离区域56描述/示出为与衬底50分隔开，但是如本文所用，术语“衬底”可以用于仅指半导体衬底或包括隔离区域的半导体衬底。此外，虽然鳍52示出为与衬底50一样的单一、连续材料，但是鳍52和/或衬底50可以包括单一材料或多种材料。在这个背景下，鳍52是指在相邻隔离区域56之间延伸的部分。
栅极介电层92沿鳍52的侧壁并且位于鳍52的顶面上方，并且栅电极94位于栅极介电层92上方。源极/漏极区域82设置在鳍52的相对于栅极介电层92和栅电极94的相对侧中。图1还示出了在后面的图中使用的参考截面。截面A-A沿栅电极94的纵轴，并且在例如垂直于FinFET的源极/漏极区域82之间的电流流动方向的方向上。截面B-B垂直于截面A-A并且沿鳍52的纵轴，并且在例如FinFET的源极/漏极区域82之间的电流流动的方向上。截面C-C平行于截面A-A，并且延伸穿过FinFET的源极/漏极区域。为了清楚，随后的图参考这些参考截面。
本文讨论的一些实施例是在使用后栅极工艺形成的FinFET的背景下讨论的。在其它实施例中，可以使用先栅极工艺。而且，一些实施例考虑了在平面器件中使用的方面，诸如平面FET、纳米结构(例如，纳米片、纳米线、全环栅等)场效应晶体管(NSFET)等。
图2至图22B是根据一些实施例的在器件100中的FinFET的制造中的中间阶段的截面图。图2至图7示出了图1中所示的参考截面A-A，除了多个鳍/FinFET和/或具有栅极隔离结构。图8A、图9A、图10A、图11A、图12A、图13A、图14A、图15A、图16A、图17A、图18A、图19A、图19C、图20A、图21A和图22A沿图1中所示的参考截面A-A示出，并且图8B、图9B、图10B、图11B、图12B、图13B、图14B、图15B、图16B、图17B、图17C、图18B、图19B、图19D、图19E、图20B、图21B和图22B沿图1中所示的类似截面的B-B示出，除了多个鳍/FinFET和/或具有栅极隔离结构。图10C和图10D沿图1中所示的参考截面C-C示出，除了多个鳍/FinFET。图13C和图19F示出了根据一些实施例的栅极结构的顶视图。
在图2中，提供了衬底50。衬底50可以是半导体衬底，诸如块状半导体、绝缘体上半导体(SOI)衬底等，其可以是掺杂的(例如，具有p型或n型掺杂剂)或未掺杂的。衬底50可以是晶圆，诸如硅晶圆。通常，SOI衬底是形成在绝缘层上的半导体材料层。绝缘层可以是例如埋氧(BOX)层、氧化硅层等。在通常为硅或玻璃衬底的衬底上提供绝缘层。也可以使用其它衬底，诸如多层或梯度衬底。在一些实施例中，衬底50的半导体材料可以包括：硅；锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟和/或磷砷化镓铟；或它们的组合。
衬底50具有n型区域50N和p型区域50P。n型区域50N可以用于形成n型器件，诸如NMOS晶体管，例如n型FinFET。p型区域50P可以用于形成p型器件，诸如PMOS晶体管，例如p型FinFET。n型区域50N可以与p型区域50P物理分隔开(如分隔器51所示)，并且任何数量的器件部件(例如，其它有源器件、掺杂区域、隔离结构等)可以设置在n型区域50N和p型区域50P之间。
在图3中，在衬底50中形成鳍52。鳍52是半导体条。在一些实施例中，可以通过在衬底50中蚀刻沟槽来在衬底50中形成鳍52。蚀刻可以是任何可接受的蚀刻工艺，诸如反应离子蚀刻(RIE)、中性束蚀刻(NBE)等或它们的组合。蚀刻可以是各向异性的。
鳍可以通过任何合适的方法来图案化。例如，鳍52可以使用一种或多种光刻工艺来图案化，包括双重图案化或多重图案化工艺。通常，双重图案化或多重图案化工艺结合光刻和自对准工艺，从而允许创建具有例如小于使用单个、直接光刻工艺可获得的间距的图案。例如，在一个实施例中，在衬底上方形成并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，并且然后剩余的间隔件可以用于图案化鳍。在一些实施例中，掩模(或其它层)可以保留在鳍52上。
在图4中，在衬底50上方和相邻鳍52之间形成绝缘材料54。绝缘材料54可以是氧化物，诸如氧化硅、氮化物等或它们的组合，并且可以通过高密度等离子体化学气相沉积(HDP-CVD)、可流动CVD(FCVD)(例如，远程等离子体系统中的基于CVD的材料沉积以及后固化以使其转化为另一材料，诸如氧化物)等或它们的组合来形成。可以使用通过任何可接受的工艺形成的其它绝缘材料。在所示实施例中，绝缘材料54是通过FCVD工艺形成的氧化硅。一旦形成绝缘材料，可以实施退火工艺。在实施例中，绝缘材料54形成为使得过量绝缘材料54覆盖鳍52。虽然绝缘材料54示出为单层，但是一些实施例可以利用多层。例如，在一些实施例中，可以首先沿衬底50和鳍52的表面形成衬垫(未显示)。此后，可以在衬垫上方形成填充材料，诸如上面讨论的那些。
在图5中，对绝缘材料54施加去除工艺以去除鳍52上方的过量绝缘材料54。在一些实施例中，可以利用诸如化学机械抛光(CMP)、回蚀工艺、它们的组合等的平坦化工艺。平坦化工艺暴露鳍52，从而使得在平坦化工艺完成之后，鳍52的顶面和绝缘材料54齐平。在掩模保留在鳍52上的实施例中，平坦化工艺可以暴露掩模或者去除掩模，从而使得在平坦化工艺完成之后，掩模或鳍52的顶面和绝缘材料54分别齐平。
在图6中，使绝缘材料54凹进以形成浅沟槽隔离(STI)区域56。使绝缘材料54凹进，从而使得n型区域50N和p型区域50P中的鳍52的上部从相邻STI区域56之间突出。此外，STI区域56的顶面可以具有如图所示的平坦表面、凸面、凹面(诸如凹陷)或它们的组合。STI区域56的顶面可以通过适当的蚀刻形成为平坦的、凸的和/或凹的。STI区域56可以使用可接受的蚀刻工艺来凹进，诸如对绝缘材料54的材料具有选择性的蚀刻工艺(例如，以比鳍52的材料快的速率蚀刻绝缘材料54的材料)。例如，可以使用氧化物去除(使用例如稀氢氟(dHF)酸)。
关于图2至图6描述的工艺只是如何形成鳍52的一个实例。在一些实施例中，鳍可以通过外延生长工艺来形成。例如，可以在衬底50的顶面上方形成介电层，并且可以穿过介电层蚀刻沟槽以暴露下面的衬底50。可以在沟槽中外延生长同质外延结构，并且可以使介电层凹进，从而使得同质外延结构从介电层突出以形成鳍。此外，在一些实施例中，异质外延结构可以用于鳍52。例如，可以使图5中的鳍52凹进，并且可以在凹进的鳍52上方外延生长与鳍52不同的材料。在这样的实施例中，鳍52包括凹进的材料以及设置在凹进的材料上方的外延生长的材料。在更进一步实施例中，可以在衬底50的顶面上方形成介电层，并且可以穿过介电层蚀刻沟槽。然后可以使用与衬底50不同的材料在沟槽中外延生长异质外延结构，并且可以使介电层凹进，从而使得异质外延结构从介电层突出以形成鳍52。在外延生长同质外延或异质外延结构的一些实施例中，外延生长的材料可以在生长期间原位掺杂，这可以避免之前和随后的注入，但是原位和注入掺杂可以一起使用。
更进一步，在n型区域50N(例如，NMOS区域)中外延生长与p型区域50P(例如，PMOS区域)中的材料不同的材料可能是有利的。在各个实施例中，鳍52的上部可以由硅锗(SixGe1-x，其中x可以在0至1的范围内)、碳化硅、纯或基本纯的锗、III-V族化合物半导体、II-VI族化合物半导体等形成。例如，用于形成III-V族化合物半导体的可用材料包括但不限于砷化铟、砷化铝、砷化镓、磷化铟、氮化镓、砷化铟镓、砷化铟铝、锑化镓、锑化铝、磷化铝、磷化镓等。
进一步在图6中，可以在鳍52和/或衬底50中形成适当的阱(未显示)。在一些实施例中，可以在n型区域50N中形成P阱，并且可以在p型区域50P中形成N阱。在一些实施例中，在n型区域50N和p型区域50P中形成P阱或N阱。
在具有不同阱类型的实施例中，用于n型区域50N和p型区域50P的不同注入步骤可以使用光刻胶和/或其它掩模(未显示)来实现。例如，可以在n型区域50N中的鳍52和STI区域56上方形成光刻胶。图案化光刻胶以暴露衬底50的p型区域50P。光刻胶可以通过使用旋涂技术来形成并且可以使用可接受的光刻技术来图案化。一旦图案化光刻胶，在p型区域50P中实施n型杂质注入，并且光刻胶可以用作掩模以基本防止n型杂质注入至n型区域50N中。n型杂质可以是注入区域中的浓度等于或小于1018cm-3的磷、砷、锑等，诸如在约1016cm-3和约1018cm-3之间。在注入之后，去除光刻胶，诸如通过可接受的灰化工艺。
在注入p型区域50P之后，在p型区域50P中的鳍52和STI区域56上方形成光刻胶。图案化光刻胶以暴露衬底50的n型区域50N。光刻胶可以通过使用旋涂技术来形成并且可以使用可接受的光刻技术来图案化。一旦图案化光刻胶，可以在n型区域50N中实施p型杂质注入，并且光刻胶可以用作掩模以基本防止p型杂质注入至p型区域50P中。p型杂质可以是注入区域中的浓度等于或小于1018cm-3的硼、氟化硼、铟等，诸如在约1016cm-3和约1018cm-3之间。在注入之后，可以去除光刻胶，诸如通过可接受的灰化工艺。
在注入n型区域50N和p型区域50P之后，可以实施退火以修复注入损伤并且以激活注入的p型和/或n型杂质。在一些实施例中，外延鳍的生长材料可以在生长期间原位掺杂，这可以避免注入，但是原位和注入掺杂可以一起使用。
在图7中，在鳍52上形成伪介电层60。伪介电层60可以是例如氧化硅、氮化硅、它们的组合等，并且可以根据可接受的技术沉积或热生长。在伪介电层60上方形成伪栅极层62，并且在伪栅极层62上方形成掩模层64。可以在伪介电层60上方沉积并且然后平坦化(诸如通过CMP)伪栅极层62。掩模层64可以沉积在伪栅极层62上方。伪栅极层62可以是导电或非导电材料并且可以选自包括非晶硅、多晶硅(poly硅)、多晶硅锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物和金属的组。伪栅极层62可以通过物理气相沉积(PVD)、CVD、溅射沉积或用于沉积所选材料的其它技术来沉积。伪栅极层62可以由相对于隔离区域(例如，STI区域56和/或伪介电层60)的蚀刻具有高蚀刻选择性的其它材料制成。掩模层64可以包括例如氮化硅、氮氧化硅等的一个或多个层。在该实例中，横跨n型区域50N和p型区域50P形成单个伪栅极层62和单个掩模层64。应该指出，仅出于说明的目的，伪介电层60显示为仅覆盖鳍52。在一些实施例中，伪介电层60可以沉积为使得伪介电层60覆盖STI区域56、在STI区域上方以及伪栅极层62和STI区域56之间延伸。
图8A至图22B示出了实施例器件的制造中的各个额外步骤。图8A至图22B示出了n型区域50N和p型区域50P中的任何一个中的部件。例如，图8A至图22B中所示的结构可以适用于n型区域50N和p型区域50P。n型区域50N和p型区域50P的结构的差异(如果有)在每个图所附的文字中描述。
在图8A和图8B中，掩模层64(见图7)可以使用可接受的光刻和蚀刻技术来图案化以形成掩模74。然后掩模74的图案可以转移至伪栅极层62。在一些实施例中(未示出)，掩模74的图案也可以通过可接受的蚀刻技术转移至伪介电层60以形成伪栅极72。伪栅极72覆盖鳍52的相应沟道区域58。掩模74的图案可以用于将伪栅极72的每个与相邻的伪栅极物理分隔开。伪栅极72也可以具有基本垂直于相应外延鳍52的纵向方向的纵向方向。
进一步在图8A和图8B中，可以在伪栅极72、掩模74和/或鳍52的暴露表面上形成栅极密封间隔件80。热氧化或沉积以及随后的各向异性蚀刻可以形成栅极密封间隔件80。栅极密封间隔件80可以由氧化硅、氮化硅、氮氧化硅等形成。
在形成栅极密封间隔件80之后，可以实施用于轻掺杂源极/漏极(LDD)区域(未明确示出)的注入。在具有不同器件类型的实施例中，类似于上面在图6中讨论的注入，可以在n型区域50N上方形成掩模，诸如光刻胶，同时暴露p型区域50P，并且适当类型(例如，p型)的杂质可以注入至p型区域50P中的暴露鳍52中。然后可以去除掩模。随后，可以在p型区域50P上方形成掩模，诸如光刻胶，同时暴露n型区域50N，并且适当类型的杂质(例如，n型)可以注入至n型区域50N中的暴露鳍52中。然后可以去除掩模。n型杂质可以是先前讨论的任何n型杂质，并且p型杂质可以是先前讨论的任何p型杂质。轻掺杂源极/漏极区域可以具有约1015cm-3至约1019cm-3的杂质浓度。可以使用退火以修复注入损伤并且以激活注入的杂质。
在图9A和图9B中，沿伪栅极72和掩模74的侧壁在栅极密封间隔件80上形成栅极间隔件86。栅极间隔件86可以通过共形沉积绝缘材料并且随后各向异性蚀刻绝缘材料来形成。栅极间隔件86的绝缘材料可以是氧化硅、氮化硅、氮氧化硅、碳氮化硅、它们的组合等。
应该指出，以上公开内容概括地描述了形成间隔件和LDD区域的工艺。可以使用其它工艺和顺序。例如，可以利用更少或额外的间隔件，可以利用不同的步骤顺序(例如，可以在形成栅极间隔件86之前不蚀刻栅极密封间隔件80，产生“L形”栅极密封间隔件，可以形成和去除间隔件等)。此外，n型和p型器件可以使用不同的结构和步骤来形成。例如，可以在形成栅极密封间隔件80之前形成用于n型器件的LDD区域，而可以在形成栅极密封间隔件80之后形成用于p型器件的LDD区域。
在图10A和图10B中，在鳍52中形成外延源极/漏极区域82。外延源极/漏极区域82形成在鳍52中，从而使得每个伪栅极72设置在外延源极/漏极区域82的相应相邻对之间。在一些实施例中，外延源极/漏极区域82可以延伸至鳍52中并且也可以穿透鳍52。在一些实施例中，栅极间隔件86用于将外延源极/漏极区域82与伪栅极72分隔开适当的横向距离，使得外延源极/漏极区域82不会使所得FinFET的随后形成的栅极短路。可以选择外延源极/漏极区域82的材料以在相应沟道区域58中施加应力，从而提高性能。
n型区域50N中的外延源极/漏极区域82可以通过掩蔽p型区域50P并且蚀刻n型区域50N中的鳍52的源极/漏极区域以在鳍52中形成凹槽来形成。然后，在凹槽中外延生长n型区域50N中的外延源极/漏极区域82。外延源极/漏极区域82可以包括任何可接受的材料，诸如适用于n型FinFET。例如，如果鳍52是硅，则n型区域50N中的外延源极/漏极区域82可以包括在沟道区域58中施加拉伸应变的材料，诸如硅、碳化硅、磷掺杂的碳化硅、磷化硅等。n型区域50N中的外延源极/漏极区域82可以具有从鳍52的相应表面凸起的表面并且可以具有小平面。
p型区域50P中的外延源极/漏极区域82可以通过掩蔽n型区域50N并且蚀刻p型区域50P中的鳍52的源极/漏极区域以在鳍52中形成凹槽来形成。然后，在凹槽中外延生长p型区域50P中的外延源极/漏极区域82。外延源极/漏极区域82可以包括任何可接受的材料，诸如适用于p型FinFET。例如，如果鳍52是硅，则p型区域50P中的外延源极/漏极区域82可以包括在沟道区域58中施加压缩应变的材料，诸如硅锗、硼掺杂的硅锗、锗、锗锡等。p型区域50P中的外延源极/漏极区域82可以具有从鳍52的相应表面凸起的表面并且可以具有小平面。
外延源极/漏极区域82和/或鳍52可以注入有掺杂剂以形成源极/漏极区域，类似于先前讨论的用于形成轻掺杂源极/漏极区域的工艺以及随后的退火。源极/漏极区域可以具有在约1019cm-3和约1021cm-3之间的杂质浓度。用于源极/漏极区域的n型和/或p型杂质可以是先前讨论的任何杂质。在一些实施例中，外延源极/漏极区域82可以在生长期间原位掺杂。
由于用于在n型区域50N和p型区域50P中形成外延源极/漏极区域82的外延工艺，外延源极/漏极区域的上表面具有横向向外扩展超过鳍52的侧壁的小平面。在一些实施例中，这些小平面使得相同FinFET的相邻源极/漏极区域82合并，如图10C所示。在其它实施例中，在外延工艺完成之后，相邻源极/漏极区域82保持分隔开，如图10D所示。在图10C和图10D中所示的实施例中，栅极间隔件86形成为覆盖鳍52的侧壁的延伸至STI区域56之上的部分，从而阻挡外延生长。在一些其它实施例中，可以调整用于形成栅极间隔件86的间隔件蚀刻以去除间隔件材料以允许外延生长区域延伸至STI区域56的表面。
在图11A和图11B中，在图10A和图10B中所示的结构上方沉积第一层间电介质(ILD)88。第一ILD 88可以由介电材料形成，并且可以通过任何合适的方法来沉积，诸如CVD、等离子体增强CVD(PECVD)或FCVD。介电材料可以包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)等。可以使用通过任何可接受的工艺形成的其它绝缘材料。在一些实施例中，接触蚀刻停止层(CESL)87设置在第一ILD 88和外延源极/漏极区域82、掩模74以及栅极间隔件86之间。CESL 87可以包括具有比上面的第一ILD 88的材料低的蚀刻速率的介电材料，诸如氮化硅、氧化硅、氮氧化硅等。
在图12A和图12B中，可以实施诸如CMP的平坦化工艺以使第一ILD 88的顶面与伪栅极72或掩模74的顶面齐平。平坦化工艺也可以去除伪栅极72上的掩模74，以及栅极密封间隔件80和栅极间隔件86的沿掩模74的侧壁的部分。在平坦化工艺之后，伪栅极72、栅极密封间隔件80、栅极间隔件86、CESL 87和第一ILD 88的顶面齐平。因此，伪栅极72的顶面通过第一ILD 88暴露。在一些实施例中，掩模74可以保留，在这种情况下，平坦化工艺使第一ILD88的顶面与掩模74的顶面齐平。
在图13A至图17C中，实施栅极切割工艺以形成延伸穿过某些伪栅极72的栅极隔离结构130(见图17A至图17C)，从而分隔并且图案化伪栅极72。在各个实施例中，栅极切割工艺可以用于限定随后形成的替换栅极结构的图案。
首先参考图13A至图13C，可以在第一ILD 88、伪栅极72、栅极密封间隔件80、CESL87和栅极间隔件86上方沉积并且图案化硬掩模120。可以图案化硬掩模120以提供暴露伪栅极72的部分的开口122。图13C示出了硬掩模120和开口122的顶视图。伪栅极72和鳍52的位置以虚线示出以供参考。如图13C中进一步所示，提供了截面A-A和B-B的位置。为了清楚，随后的图参考这些截面。具体地，图13A、图14A、图15A、图16A和图17A示出了沿截面A-A(例如，在平行于鳍52的纵向方向的方向上)并且通过开口122中的一个的视图，并且图13B、图14B、图15B、图16B、图17B和图17C示出了沿截面B-B(例如，在垂直于鳍52的纵向方向的方向上)并且通过开口122中的一个的视图。
可以选择硬掩模120的材料，使得它可以相对于下面的层(诸如伪栅极72和/或第一ILD 88)的材料被选择性图案化。例如，硬掩模120可以包括任何合适的材料，诸如氮化硅、氮氧化硅、碳氮化硅、非晶硅、Al2O3等，其使用合适的工艺来沉积，诸如PVD、CVD、ALD、它们的组合等。
例如，硬掩模120可以使用光刻和蚀刻的组合来图案化，以包括暴露伪栅极72的部分的开口122。开口122的图案可以对应于伪栅极72的栅极切割位置(例如，伪栅极72的相邻部分将物理分隔开的区域)。由于用于图案化硬掩模120的蚀刻工艺，硬掩模120的顶面处的开口122的宽度可以小于硬掩模120的底面处的开口122的宽度。例如，蚀刻工艺可能在硬掩模120的顶面处留下轻微的悬垂，这在开口122顶部处产生比开口122的底部略窄的临界尺寸(例如，宽度)。
在图14A和图14B中，开口122延伸穿过伪栅极72和鳍52进入衬底50中。延伸开口122可以包括一种或多种蚀刻工艺，诸如干蚀刻、湿蚀刻等或它们的任何组合。例如，延伸开口122可以包括第一蚀刻工艺，该第一蚀刻工艺去除伪栅极72的由硬掩模120暴露的部分和伪介电层60的由硬掩模120暴露的部分。随后，可以施加第二蚀刻工艺以去除鳍52的由掩模120暴露的部分，从而延伸开口122穿过鳍52并且进入衬底50中。第二蚀刻工艺可以与用于去除伪栅极72和伪介电层60的部分的第一蚀刻工艺相同或不同。第二蚀刻工艺可以是可以以比STI区域56高的速率选择性蚀刻鳍52和衬底50的选择性蚀刻工艺。因此，开口122可以在STI区域56中延伸至与衬底50不同的深度(例如，更小)。此外，第二蚀刻工艺可以在不同深度处横向蚀刻鳍52不同的量。例如，鳍52的顶面处的开口122的宽度W2可以小于图14B所示的截面中的开口122的最大宽度W1。在一些实施例中，最大宽度W1可以在28nm至38nm的范围内，并且宽度W2可以在13nm至30nm的范围内。在其它实施例中，其它尺寸也是可能的。
在图15A和图15B中，在掩模120上方、开口122的侧壁上并且沿开口122的底面沉积介电衬垫124。随后介电衬垫124也可以称为间隔件124或间隔件层124。介电衬垫124可以包括氮化硅、氮氧化硅、碳氮化硅、碳氮氧化硅等，其使用非共形沉积工艺来沉积。由于非共形沉积工艺，介电衬垫124可以在它沿伪栅极72的侧壁延伸时具有变化的厚度。在一些实施例中，第一ILD 88的顶面处的介电衬垫124的厚度T1可以与第一ILD 88的底面/鳍52的顶面处的介电衬垫124的厚度T2不同。具体地，厚度T1可以小于厚度T2，并且开口122的顶部处的宽度W2可以大于第一ILD 88的底面/鳍52的顶面处的宽度W3。因此，在沉积介电衬垫124之后，用于随后沉积至开口122中的介电填充材料的沉积窗口有利地加宽至开口122的顶部处的增加的宽度。
在一些实施例中，非共形沉积工艺是等离子体增强原子层沉积(PEALD)工艺，该工艺施加等离子体处理以实现上述介电衬垫124的变化宽度。PEALD工艺可以包括将包括氮(N2)等离子体的前体工艺气体流入沉积室。当介电衬垫124包括氮化硅时，前体工艺气体还可以包括热SiH2I2(例如，加热至气态)、氢(H2)等离子体等和/或它们的组合。通过流动氮等离子体前体作为PEALD工艺的一部分，将氮等离子体工艺施加至由开口122暴露的表面。由于氮等离子体处理，与开口122的底部相比，用于沉积介电衬垫124的培养时间在开口122的顶部处可能变差，并且与开口122的底部相比，介电衬垫124在开口122的顶部处沉积得更薄。在一些实施例中，例如，PEALD等离子体可以在300℃至600℃的范围内的温度下、7.5Torr至90Torr的范围内的压力下实施，并且进行10分钟至60分钟的持续时间。其它实施例可以利用不同的处理参数实施PEALD工艺。
在图16A和图16B中，在介电衬垫124上方的开口122中沉积介电填充材料126。在一些实施例中，介电填充材料126可以包括与介电衬垫124类似的材料(例如，氮化硅)。但是，介电填充材料126可以使用与介电衬垫124不同类型的工艺来沉积。例如，介电填充材料126可以利用共形工艺来沉积，诸如ALD工艺，而不是用于沉积介电衬垫124的非共形、PEALD工艺。在一些实施例中，用于沉积介电填充材料126的ALD工艺可以是不使用等离子体的热工艺。作为ALD工艺的一部分，介电填充材料126可以沉积在开口122的表面上，直至介电填充材料126的部分合并在一起，限定接缝128并且填充开口122。由于介电衬垫124的轮廓(例如，在开口122的顶部处较薄)，介电填充材料126的沉积窗口可以加宽并且可以在介电填充材料内形成相对较小的接缝128。此外，接缝128可以包括介电填充材料126的下部中的空隙128’，并且空隙128’可以有利地减小所得栅极隔离结构的介电常数，从而减小寄生电容。
在图17A至图17C中，施加平坦化工艺以去除介电衬垫124和介电填充材料126的过量部分(例如，开口122外部的部分)。平坦化工艺可以进一步去除硬掩模120。平坦化工艺可以是CMP工艺、回蚀工艺等或它们的组合。因此，形成包括介电衬垫124和介电填充材料126的剩余部分的栅极隔离结构130。栅极隔离结构130可以用于物理分隔伪栅极72的部分并且帮助限定随后形成的替换栅极结构的图案。
由于上述示例性沉积工艺，栅极隔离结构130可以具有某些有利的尺寸。图17C以与图17B类似的截面(例如，沿上述截面B-B)示出了栅极隔离结构130的详细视图。介电衬垫124可以在鳍52的顶面处具有横向尺寸D1(例如，第一ILD 88的底面的水平面)并且在第一ILD 88的顶面的水平面处具有横向尺寸D2。由于用于形成介电衬垫124的沉积工艺(例如，具有氮等离子体的PEALD)，横向尺寸D2可以小于横向尺寸D1。在一些实施例中，横向尺寸D1可以在3.8nm至22.5nm的范围内，而横向尺寸D2可以在3nm至18nm的范围内。例如，横向尺寸D1与横向尺寸横向D2的比率可以在1.1至1.5的范围内。已经观察到，通过形成具有上述尺寸/轮廓的介电衬垫124，可以实现优势，诸如加宽用于介电填充材料126的沉积窗口，从而减小接缝128的尺寸并且减少制造缺陷。例如，接缝128在栅极隔离结构130的上部中可以具有在1.5nm至9nm的范围内的横向尺寸D4。已经观察到，通过具有上述尺寸的接缝，制造缺陷可以有利地减少。具体地，上述尺寸的接缝可以足够小以避免过蚀刻栅极隔离结构130或在随后的接触件形成工艺期间金属颗粒被捕获接缝内以及导致电短路的风险。此外，接缝128可以包括栅极隔离结构130的下部中的空隙128’，并且空隙128’在其截面中的最宽点处可以具有在0.5nm至3nm的范围内的横向尺寸D3。空隙128’的横向尺寸D3可以比接缝128的上部的横向尺寸D4宽。已经观察到，通过包括上述尺寸的空隙，栅极隔离结构130的介电常数可以减小，从而减小寄生电容。更进一步，介电填充材料126在与第一ILD 88的顶面相同的水平面处具有横向尺寸D5，在鳍52的顶面处具有横向尺寸D6(例如，与第一ILD 88的底面相同的水平面)；以及在截面图中(例如，在鳍52中)介电填充材料126的最宽点处具有横向尺寸D7。横向尺寸D5可以大于横向尺寸D6，并且横向尺寸D7可以大于横向尺寸D5和D6的每个。在一些实施例中，横向尺寸D5可以在3.3nm至19.5nm的范围内；横向尺寸D6可以在2.5nm至15nm的范围内；以及横向尺寸D7可能在5nm至15nm的范围内。例如，横向尺寸D6与横向尺寸D5的比率可以在0.7至0.9的范围内，并且横向尺寸D6与横向尺寸D7的比率可以在0.4至0.6的范围内。
图18A至图22B示出了利用功能栅极堆叠件替换伪栅极72以及形成各个接触件的随后步骤。图18A、图19A、图20A、图21A和图22A示出了沿截面A-A(例如，在平行于鳍52的纵向方向的方向上)并且穿过栅极隔离结构130中的一个的视图，并且图18B、图19B、图20B、图21B和图22B示出了沿截面B-B(例如，在垂直于鳍52的纵向方向的方向上)并且穿过栅极隔离结构130中的一个的视图。图19C至图19F示出了在形成功能栅极堆叠件之后的器件的变化视图。
在图18A和图18B中，在蚀刻步骤中去除伪栅极72，从而形成凹槽90。也可以去除伪介电层60的位于凹槽90中的部分。在一些实施例中，仅去除伪栅极72并且伪介电层60保留并且通过凹槽90暴露。在一些实施例中，伪介电层60从管芯的第一区域(例如，核心逻辑区域)中的凹槽90去除并且保留在管芯的第二区域(例如，输入/输出区域)中的凹槽90中。在一些实施例中，伪栅极72通过各向异性干蚀刻工艺来去除。例如，蚀刻工艺可以包括使用反应气体的干蚀刻工艺，该干蚀刻工艺选择性蚀刻伪栅极72而很少或不蚀刻第一ILD 88、栅极隔离结构130或栅极间隔件86。每个凹槽90暴露和/或位于相应鳍52的沟道区域58上面。每个沟道区域58设置在外延源极/漏极区域82的相邻对之间。在去除期间，当蚀刻伪栅极72时，伪介电层60可以用作蚀刻停止层。然后可以在去除伪栅极72之后可选地去除伪介电层60。
在图19A至图19F中，形成栅极介电层92和栅电极94以用于替换栅极。图19F示出了各个截面的顶视图和位置。图19A示出了沿图19F的线A-A(例如，穿过栅极隔离结构130)的截面图；图19B示出了沿图19F的线B-B(例如，穿过栅极隔离结构130)的截面图；图19C示出了沿图19F的线C-C(例如，不延伸穿过栅极隔离结构130并且平行于截面A-A)的截面图；以及图19D示出了沿图19F的线D-D(例如，不延伸穿过栅极隔离结构130并且平行于截面B-B)的截面图。图19E示出了图19B和图19D的区域89的详细视图。
栅极介电层92包括沉积在凹槽90中的一个或多个层，诸如在鳍52的顶面和侧壁上以及在栅极密封间隔件80/栅极间隔件86的侧壁上。栅极介电层92也可以形成在第一ILD88的顶面上。在一些实施例中，栅极介电层92包括一个或多个介电层，诸如氧化硅、氮化硅、金属氧化物、金属硅酸盐等的一个或多个层。例如，在一些实施例中，栅极介电层92包括通过热氧化或化学氧化形成的氧化硅的界面层以及上面的高k介电材料，诸如铪、铝、锆、镧、锰、钡、钛、铅和它们的组合的金属氧化物或硅酸盐。栅极介电层92可以包括具有大于约7.0的k值的介电层。栅极介电层92的形成方法可以包括分子束沉积(MBD)、ALD、PECVD等。在伪栅极电介质60的部分保留在凹槽90中的实施例中，栅极介电层92包括伪栅极电介质60的材料(例如，SiO2)。
栅电极94分别沉积在栅极介电层92上方，并且填充凹槽90的剩余部分。栅电极94可以包括含金属材料，诸如氮化钛、氧化钛、氮化钽、碳化钽、钴、钌、铝、钨、它们的组合或它们的多层。例如，虽然图19B和图19D中示出了单层栅电极94，但是栅电极94可以包括任何数量的衬垫层94A、任何数量的功函调整层94B和填充材料94C，如图19E所示。在一些实施例中，衬垫层94A和功函调整层94B的顺序可以颠倒。在填充凹槽90之后，可以实施诸如CMP的平坦化工艺以去除栅极介电层92和栅电极94的材料的过量部分，这些过量部分位于ILD 88的顶面上方。栅电极94的材料和栅极介电层92的剩余部分因此形成所得FinFET的替换栅极。栅电极94和栅极介电层92可以统称为“栅极堆叠件”。栅极和栅极堆叠件可以沿鳍52的沟道区域58的侧壁延伸。此外，栅极隔离结构130的每个将相邻的第一栅极堆叠件和第二栅极堆叠件(每个包括栅极介电层92和对应的栅电极94)分隔开，如图19A和图19F所示。
n型区域50N和p型区域50P中的栅极介电层92的形成可以同时发生，从而使得每个区域中的栅极介电层92由相同的材料形成，并且栅电极94的形成可以同时发生，从而使得每个区域中的栅电极94由相同的材料形成。在一些实施例中，每个区域中的栅极介电层92可以通过不同的工艺形成，从而使得栅极介电层92可以是不同的材料，和/或每个区域中的栅电极94可以通过不同的工艺形成，从而使得栅电极94可以是不同的材料。当使用不同的工艺时，可以使用各个掩蔽步骤来掩蔽和暴露适当的区域。
在图20A和图20B中，在栅极堆叠件(包括栅极介电层92和对应的栅电极94)上方形成栅极掩模96，并且栅极掩模可以设置在栅极间隔件86的相对部分之间。在一些实施例中，形成栅极掩模96包括使栅极堆叠件凹进，从而直接在栅极堆叠件上方和栅极间隔件86的相对部分之间形成凹槽。凹槽可以进一步暴露栅极隔离结构130的侧壁。栅极掩模96可以进一步沿栅极隔离结构130的侧壁延伸。在凹槽中填充包括介电材料(诸如氮化硅、氮氧化硅等)的一个或多个层的栅极掩模96，随后是平坦化工艺以去除介电材料的在第一ILD 88上方延伸的过量部分。栅极掩模96是可选的并且在一些实施例中可以省略。在这样的实施例中，栅极堆叠件可以保持与第一ILD 88的顶面齐平。
也如图20A和图20B中所示，根据一些实施例，穿过第一ILD 88形成第一层级源极/漏极接触件112。穿过第一ILD 88形成用于源极/漏极接触件112的开口。开口可以使用可接受的光刻和蚀刻技术来形成。在开口中形成诸如扩散阻挡层、粘合层等的衬垫(未显示)以及导电材料。衬垫可以包括钛、氮化钛、钽、氮化钽等。导电材料可以是铜、铜合金、银、金、钨、钴、铝、镍等。可以实施诸如CMP的平坦化工艺以从第一ILD 88的表面去除过量材料。剩余的衬垫和导电材料在开口中形成源极/漏极接触件112。可以实施退火工艺以在外延源极/漏极区域82和源极/漏极接触件112之间的界面处形成硅化物。源极/漏极接触件112物理和电耦接至外延源极/漏极区域82。由于接缝128的相对较小尺寸，可以形成源极/漏极接触件112而不损坏栅极隔离结构130(例如，过蚀刻或金属颗粒的不期望的捕获)。
在图21A和图21B中，在第一ILD 88上方沉积第二ILD 108。在一些实施例中，第二ILD 108是通过可流动CVD方法形成的可流动膜。在一些实施例中，第二ILD 108由诸如PSG、BSG、BPSG、USG等的介电材料形成，并且可以通过诸如CVD和PECVD的任何合适的方法来沉积。随后形成的栅极接触件110(图16A和图16B)穿透第二ILD 108和栅极掩模96(如果存在)以接触凹进的栅电极94的顶面。
在图22A和图22B中，根据一些实施例，穿过第二ILD 108形成栅极接触件110和第二层级源极/漏极接触件114。穿过第二ILD 108至第一层级源极/漏极接触件112形成用于源极/漏极接触件114的开口，并且穿过第二ILD 108和栅极掩模96(如果存在)形成用于栅极接触件110的开口。开口可以使用可接受的光刻和蚀刻技术来形成。在开口中形成诸如扩散阻挡层、粘合层等的衬垫(未显示)以及导电材料。衬垫可以包括钛、氮化钛、钽、氮化钽等。导电材料可以是铜、铜合金、银、金、钨、钴、铝、镍等。可以实施诸如CMP的平坦化工艺以从ILD 108的表面去除过量材料。剩余的衬垫和导电材料在开口中形成源极/漏极接触件114和栅极接触件110。源极/漏极接触件114物理和电耦接至源极/漏极接触件112，并且栅极接触件110物理和电耦接至栅电极106。源极/漏极接触件112和栅极接触件110可以在不同的工艺中形成，或者可以在相同的工艺中形成。虽然示出为形成在相同的截面中，但是应该理解，源极/漏极接触件112和栅极接触件110的每个可以形成在不同的截面中，这可以避免接触件的短路。此外，为源极/漏极接触件114选择的材料可以与源极/漏极接触件112和/或栅极接触件110的材料相同或不同。因此，在具有分隔相邻栅极堆叠件92/94的栅极隔离结构130的半导体器件100中形成finFET器件。
图1至图22B示出了栅极隔离结构130的特定配置。其它实施例可以包括栅极隔离结构130的其它配置。例如，图23A和图23B示出了根据一些实施例的器件150。图23A示出了沿图1的截面A-A并且穿过栅极隔离结构130的视图，并且图23B示出了沿图1的截面B-B并且穿过栅极隔离结构130的视图。器件150可以类似于器件100，其中相同的参考标号表示通过相同的工艺形成的相同的元件。但是，与在接缝128的下部中包括空隙128’的器件100不同，器件150中的栅极隔离结构130没有空隙128’。例如，可以通过控制形成介电填充材料126的沉积工艺和/或控制沉积介电填充材料126的开口的高宽比来省略空隙128’。接缝128可以具有相对较小的横向尺寸以实现上述益处。
作为另一实例，图24A和图24B示出了根据一些实施例的器件200。图24A示出了沿图1的截面A-A并且穿过栅极隔离结构130的视图，并且图24B示出了沿图1的截面B-B并且穿过栅极隔离结构130的视图。器件200可以类似于器件100，其中相同的参考标号表示通过相同的工艺形成的相同的元件。但是，与介电衬垫124保持未合并的器件100不同，器件200中的栅极隔离结构130可以包括从第一栅极堆叠件的侧壁连续延伸至第二栅极堆叠件的侧壁的合并的介电衬垫124。具体地，介电衬垫124的下部(例如，设置在鳍52、衬底50和STI区域56中的部分)可以在鳍52/STI区域56的顶面处合并在一起。介电衬垫124的下部还可以包括由于合并而形成的空隙132。填充材料126可以设置在介电衬垫124的合并的下部上方，并且填充材料126可以包括具有相对较小的横向尺寸的接缝128以实现上述益处。
作为另一实例，图25A和图25B示出了根据一些实施例的器件250。图25A示出了沿图1的截面A-A并且穿过栅极隔离结构130的视图，并且图25B示出了沿图1的截面B-B并且穿过栅极隔离结构130的视图。器件250可以类似于器件100，其中相同的参考标号表示通过相同的工艺形成的相同的元件。但是，与介电衬垫124直接接触介电填充材料126的器件100不同，器件250中的栅极隔离结构130还可以包括介电衬垫124和介电填充材料126之间的额外介电衬垫134。在一些实施例中，介电衬垫134可以包括氧化物材料，诸如介电衬垫124的材料的氧化物。例如，当介电衬垫124包括氮化硅时，介电衬垫134可以包括氮氧化硅。介电衬垫134可以是由于将介电衬垫124暴露于大气环境从而氧化介电衬垫124而形成的原生氧化物。在一些实施例中，介电衬垫124可在沉积工具(例如，用于沉积介电衬垫124的PEALD工具和用于沉积介电填充材料126的ALD工具)之间转移器件250时暴露于大气。其它衬垫材料也可以用于介电衬垫124。
所公开的FinFET实施例也可以应用于纳米结构器件，诸如纳米结构(例如，纳米片、纳米线、全环栅等)场效应晶体管(NSFET)。在NSFET实施例中，鳍由通过图案化沟道层和牺牲层的交替层的堆叠件形成的纳米结构替换。伪栅极堆叠件和源极/漏极区域以类似于上述实施例的方式形成。也形成栅极隔离结构以延伸穿过伪栅极堆叠件，如上所述。在去除伪栅极堆叠件之后，可以部分或全部去除沟道区域中的牺牲层。替换栅极结构以类似于上述实施例的方式形成，替换栅极结构可以部分或完全填充通过去除牺牲层而留下的开口，并且替换栅极结构可以部分或完全围绕NSFET器件的沟道区域中的沟道层。ILD以及至替换栅极结构和源极/漏极区域的接触件可以以类似于上述实施例的方式形成。
图26示出了根据一些实施例的NSFET的立体图。图27A和图27B示出了NSFET背景下的各个实施例栅极隔离结构130的截面图。参考图26，NSFET器件包括衬底50(例如，半导体衬底)上的鳍52上方的纳米结构55(例如，纳米片、纳米线等)，其中纳米结构55用作用于NSFET器件的沟道区域。纳米结构55可以包括p型纳米结构、n型纳米结构或它们的组合。STI区域56设置在相邻鳍52之间，鳍52可以突出至相邻STI区域56之上并且从相邻STI区域56之间突出。栅极介电材料92位于鳍52的顶面上方并且沿纳米结构55的顶面、侧壁和底面。栅电极94位于栅极介电材料92上方。外延源极/漏极区域82设置在栅极堆叠件92/94的相对侧上的鳍52上。
图26还示出了在后面的图中使用的参考截面。截面X-X沿栅电极94的纵轴，并且在例如垂直于NSFET器件的外延源极/漏极区域82之间的电流流动方向的方向上。截面Y-Y垂直于截面X-X并且平行于NSFET器件的鳍52的纵轴，并且在例如NSFET器件的外延源极/漏极区域82之间的电流流动的方向上。图27A示出了沿图26的截面X-X合并栅极隔离结构130(例如，如上面在图1至图22B中所描述)的实施例NSFET器件，并且图27B示出了沿图26的截面Y-Y合并栅极隔离结构130的NSFET器件。图26至图27B的各个部件可以类似于上面在图1至图22B中描述的那些，其中相同的参考标号表示通过相同的工艺形成的相同的元件。图27A和图27B示出了NSFET器件背景下的栅极隔离结构130。虽然图27A和图27B示出了根据上述器件100的栅极隔离结构130，但是其它实施例可以包括根据上述器件150、200或250中的任何一个的栅极隔离结构130。
在各个实施例中，栅极隔离结构可以包括介电衬垫(有时称为间隔件)，其使用非共形沉积工艺来沉积为具有锥形轮廓，并且栅极隔离结构还可以包括沉积在介电衬垫上方的介电填充材料。通过在介电衬垫中保持锥形轮廓，开口的顶部处的宽度可以保持相对较大，并且改进了介电填充材料的沉积窗口。因此，介电填充材料可以形成为具有较少的制造误差，诸如减少的接缝/空隙。接缝/空隙的尺寸/数量的减少可以进一步减少电缺陷(例如，短路)，该电缺陷可能是由于在随后的处理步骤期间(例如，在栅极或源极/漏极接触件的形成期间)导电材料被无意地捕获在暴露的接缝中而导致的。
在一些实施例中，半导体器件包括：第一晶体管，具有第一栅极堆叠件和位于第一栅极堆叠件的相对侧上的第一源极/漏极区域；第二晶体管，具有第二栅极堆叠件和位于第二栅极堆叠件的相对侧上的第二源极/漏极区域；栅极隔离结构，将第一栅极堆叠件与第二栅极堆叠件分隔开，其中，栅极隔离结构包括：介电衬垫，沿第一栅极堆叠件和第二栅极堆叠件的侧壁具有变化的厚度；以及介电填充材料，位于介电衬垫上方，其中，介电填充材料包括接缝。可选地，在一些实施例中，介电衬垫沿介电填充材料的底面具有横向部分，其中，介电衬垫的变化的厚度在朝向介电衬垫的横向部分的方向上增加。可选地，在一些实施例中，空隙设置在接缝的下部中，其中，空隙比接缝的上部宽。可选地，在一些实施例中，半导体器件还包括：第二介电衬垫，位于介电衬垫和介电填充材料之间。可选地，在一些实施例中，介电衬垫包括第一介电材料，并且第二介电衬垫包括第一介电材料的氧化物。可选地，在一些实施例中，介电衬垫从第一栅极堆叠件的侧壁连续延伸至第二栅极堆叠件的侧壁。可选地，在一些实施例中，半导体器件还包括：空隙，位于介电衬垫的下部中。
在一些实施例中，半导体器件包括：第一栅极堆叠件，位于层间电介质中；第二栅极堆叠件，位于层间电介质中；以及栅极隔离结构，位于第一栅极堆叠件和第二栅极堆叠件之间，其中，栅极隔离结构接触第一栅极堆叠件的侧壁和第二栅极堆叠件的侧壁，其中，栅极隔离结构包括：介电衬垫，其中，介电衬垫的第一横向尺寸小于介电衬垫的第二横向尺寸，其中，介电衬垫的第一横向尺寸在层间电介质的顶面的水平面处测量，其中，介电衬垫的第二横向尺寸在层间电介质的底面的水平面处测量；以及介电填充材料，位于介电衬垫上方，其中，介电填充材料包括接缝。可选地，在一些实施例中，介电填充材料的第一横向尺寸大于介电填充材料的第二横向尺寸，其中，介电填充材料的第一横向尺寸在层间电介质的顶面的水平面处测量，其中，介电填充材料的第二横向尺寸在层间电介质的底面的水平面处测量。可选地，在一些实施例中，介电填充材料的第二横向尺寸与介电填充材料的第一横向尺寸的比率在0.7至0.9的范围内。可选地，在一些实施例中，介电填充材料的第三横向尺寸大于介电填充材料的第一横向尺寸和介电填充材料的第二横向尺寸，其中，第三横向尺寸在截面图中的介电填充材料的最宽点处测量，并且其中，第三横向尺寸在层间电介质的底面下方的水平面处测量。可选地，在一些实施例中，介电填充材料的第二横向尺寸与介电填充材料的第三横向尺寸的比率在0.4至0.6的范围内。可选地，在一些实施例中，接缝包括上部和下部，其中，下部具有横向尺寸大于上部的空隙。可选地，在一些实施例中，介电衬垫的第二横向尺寸与介电衬垫的第一横向尺寸的比率在1.1至1.5的范围内。
在一些实施例中，方法包括：图案化延伸穿过伪栅极堆叠件的开口；在开口的侧壁和底面上沉积介电衬垫，其中，沉积介电衬垫包括非共形沉积工艺；在介电衬垫上方的开口中沉积介电填充材料，其中，沉积介电填充材料包括与沉积介电衬垫不同类型的沉积工艺，并且其中，沉积介电填充材料包括在介电填充材料中形成接缝；去除伪栅极堆叠件；以及在介电衬垫的相对侧上形成第一栅极堆叠件和第二栅极堆叠件。可选地，在一些实施例中，非共形沉积工艺是等离子体增强原子层沉积(PEALD)工艺，其中，PEALD工艺在开口的顶部处比在开口的底部处沉积更薄的介电衬垫。可选地，在一些实施例中，沉积介电填充材料包括原子层沉积(ALD)工艺。可选地，在一些实施例中，PEALD工艺包括实施氮等离子体处理。可选地，在一些实施例中，非共形沉积工艺包括在开口的下部处合并介电衬垫。可选地，在一些实施例中，方法还包括：在沉积介电填充材料之前，氧化介电衬垫。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
第一晶体管，具有第一栅极堆叠件和位于所述第一栅极堆叠件的相对侧上的第一源极/漏极区域；
第二晶体管，具有第二栅极堆叠件和位于所述第二栅极堆叠件的相对侧上的第二源极/漏极区域；
栅极隔离结构，将所述第一栅极堆叠件与所述第二栅极堆叠件分隔开，其中，所述栅极隔离结构包括：
介电衬垫，沿所述第一栅极堆叠件和所述第二栅极堆叠件的侧壁具有变化的厚度；以及
介电填充材料，位于所述介电衬垫上方，其中，所述介电填充材料包括接缝。
2.根据权利要求1所述的半导体器件，其中，所述介电衬垫沿介电填充材料的底面具有横向部分，其中，所述介电衬垫的变化的厚度在朝向所述介电衬垫的所述横向部分的方向上增加。
3.根据权利要求1所述的半导体器件，其中，空隙设置在所述接缝的下部中，其中，所述空隙比所述接缝的上部宽。
4.根据权利要求1所述的半导体器件，还包括：第二介电衬垫，位于所述介电衬垫和所述介电填充材料之间。
5.根据权利要求4所述的半导体器件，其中，所述介电衬垫包括第一介电材料，并且所述第二介电衬垫包括所述第一介电材料的氧化物。
6.根据权利要求1所述的半导体器件，其中，所述介电衬垫从所述第一栅极堆叠件的侧壁连续延伸至所述第二栅极堆叠件的侧壁。
7.根据权利要求6所述的半导体器件，还包括：空隙，位于所述介电衬垫的下部中。
8.一种半导体器件，包括：
第一栅极堆叠件，位于层间电介质中；
第二栅极堆叠件，位于所述层间电介质中；以及
栅极隔离结构，位于所述第一栅极堆叠件和所述第二栅极堆叠件之间，其中，所述栅极隔离结构接触所述第一栅极堆叠件的侧壁和所述第二栅极堆叠件的侧壁，其中，所述栅极隔离结构包括：
介电衬垫，其中，所述介电衬垫的第一横向尺寸小于所述介电衬垫的第二横向尺寸，其中，所述介电衬垫的所述第一横向尺寸在所述层间电介质的顶面的水平面处测量，其中，所述介电衬垫的所述第二横向尺寸在所述层间电介质的底面的水平面处测量；以及
介电填充材料，位于所述介电衬垫上方，其中，所述介电填充材料包括接缝。
9.根据权利要求8所述的半导体器件，其中，所述介电填充材料的第一横向尺寸大于所述介电填充材料的第二横向尺寸，其中，所述介电填充材料的所述第一横向尺寸在所述层间电介质的顶面的水平面处测量，其中，所述介电填充材料的所述第二横向尺寸在所述层间电介质的底面的水平面处测量。
10.一种形成半导体器件的方法，包括：
图案化延伸穿过伪栅极堆叠件的开口；
在所述开口的侧壁和底面上沉积介电衬垫，其中，沉积所述介电衬垫包括非共形沉积工艺；
在所述介电衬垫上方的所述开口中沉积介电填充材料，其中，沉积所述介电填充材料包括与沉积所述介电衬垫不同类型的沉积工艺，并且其中，沉积所述介电填充材料包括在所述介电填充材料中形成接缝；
去除所述伪栅极堆叠件；以及
在所述介电衬垫的相对侧上形成第一栅极堆叠件和第二栅极堆叠件。
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