CN115020258A - 半导体装置、功率模块、半导体装置的制造方法及半导体模块 - Google Patents

半导体装置、功率模块、半导体装置的制造方法及半导体模块 Download PDF

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CN115020258A
CN115020258A CN202210844102.6A CN202210844102A CN115020258A CN 115020258 A CN115020258 A CN 115020258A CN 202210844102 A CN202210844102 A CN 202210844102A CN 115020258 A CN115020258 A CN 115020258A
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electrode
semiconductor device
substrate
substrate electrode
lead
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大塚拓一
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Rohm Co Ltd
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Rohm Co Ltd
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Abstract

本发明提供一种半导体装置、功率模块、半导体装置的制造方法及半导体模块，能够使功率循环耐受容量提高。半导体装置具备半导体芯片(12)、和以覆盖半导体芯片(12)上的源极焊盘电极(14)的方式形成的银烧成盖(22)。半导体芯片(12)配置于第一基板电极(10B)上，通过超声波在银烧成盖(22)上接合铜线(18)的一端。

Description

半导体装置、功率模块、半导体装置的制造方法及半导体模块
本发明是申请号为201780024218.2(国际申请号为PCT/JP2017/015306)、发明名称为“半导体装置、功率模块及其制造方法”、申请日为2017年04月14日的发明申请的分案申请。
技术领域
本实施方式涉及一种半导体装置、功率模块、半导体装置的制造方法及半导体模块。
背景技术
在现有技术(铝线)中，随着功率模块的结温Tj的上升，对功率循环耐受容量的要求更加严格。因此近来出现了为延长寿命使用铜线而非铝线的情况。也有取代线材而使用导体件、电极柱等上部配线的情况。
现有技术文献
专利文献
专利文献1：日本特开2009－4544号公报
专利文献2：日本特开2000－100849号公报
专利文献3：日本特开2016－4796号公报
发明内容
发明所要解决的课题
但是，在将铜线接合到半导体芯片上的情况下，与铝线相比超声波的功率非常大而会导致器件受损。
另外，在使用导体件、电极柱等上部配线的情况下，使用无铅类的焊料作为其接合材料。但是在使用无铅类的焊料时，就碳化硅(SiC)等具备200℃以上的耐热性的器件而言，由于熔点接近结温Tj＝200℃且ΔTj功率循环增大，因此会导致功率循环耐受容量(功率循环寿命)减小。
本实施方式提供一种能够使功率循环耐受容量提高的半导体装置、功率模块及其制造方法。
用于解决课题的方案
根据本实施方式的一方案，提供一种半导体装置，其具备半导体芯片、和以覆盖所述半导体芯片上的电极的方式形成的高耐热性的烧成膜。
根据本实施方式的另一方案，提供一种半导体装置的制造方法，其具有形成半导体芯片的工序、和以覆盖所述半导体芯片上的电极的方式形成高耐热性的烧成膜的工序。
发明效果
根据本实施方式，能提供能够使功率循环耐受容量提高的半导体装置、功率模块及其制造方法。
附图说明
图1是比较例1的半导体装置的示意性的鸟瞰图。
图2是第一实施方式的半导体装置的示意性的鸟瞰图，(a)是铜线接合前的状态，(b)是铜线接合后的状态。
图3是表示第一实施方式的半导体装置的仿真模型的示意性的剖视结构图。
图4是表示图3所示的仿真模型的效果的曲线图表。
图5是比较例2的半导体装置的示意性的鸟瞰图。
图6是第二实施方式的半导体装置的示意性的鸟瞰图。
图7是表示第二实施方式的半导体装置的仿真模型1(盖结构)的示意性的剖视结构图。
图8是表示比较例2的半导体装置的仿真模型2(焊料结构)的示意性的剖视结构图。
图9是表示仿真模型1与仿真模型2的比较结果的曲线图表。
图10是表示ΔTj功率循环与功率循环寿命的关系的曲线图表。
图11是表示线材发生了龟裂的状态的图。
图12是表示应变量随着时间的经过而饱和的曲线图表。
图13是表示第一或第二实施方式的半导体装置的制造方法的图，(a)是表示半导体芯片的图，(b)是表示掩模印刷工序的图，(c)是表示干燥工序的图，(d)表示烧成工序的图。
图14是利用图13所示的制造方法所制造的银烧成盖的照片。
图15是采用了第二实施方式的半导体装置的模块的结构图(照片)，(a)是鸟瞰图，(b)是俯视图。
图16是图15所示模块的成型后的结构图(照片)。
图17是将图15所示模块局部放大的照片。
图18是将图15所示模块局部放大的照片。
图19是表示图15所示模块的整体的照片。
图20是将图15所示模块局部放大的照片。
图21是采用了第一实施方式的半导体装置的模块的示意性的结构图。
图22是第一或第二实施方式的半导体装置的ΔTj功率循环测试中的电流与温度的变化的示意图。
图23是第一或第二实施方式的半导体装置的热循环测试中的温度曲线例。
图24表示第一或第二实施方式的半导体装置，(a)为一对一模块(1in 1Module)的SiC MISFET的示意性的电路表达图，(b)为一对一模块的IGBT的示意性的电路表达图。
图25表示第一或第二实施方式的半导体装置，是一对一模块的SiC MISFET的详细电路表达图。
图26表示第一或第二实施方式的半导体装置，(a)为二对一模块的SiC MISFET的示意性的电路表达图，(b)为二对一模块的绝缘栅双极型晶体管(IGBT：Insulated GateBipolar Transistor)的示意性的电路表达图。
图27是应用于第一或第二实施方式的半导体装置的半导体器件的例子，(a)为SiCMISFET的示意性的剖视结构图，(b)为IGBT的示意性的剖视结构图。
图28是应用于第一或第二实施方式的半导体装置的半导体器件的例子，是包含源极焊盘电极SP、栅极焊盘电极GP的SiC MISFET的示意性的剖视结构图。
图29是应用于第一或第二实施方式的半导体装置的半导体器件的例子，是包含发射极焊盘电极EP、栅极焊盘电极GP的IGBT的示意性的剖视结构图。
图30是能够应用于第一或第二实施方式的半导体装置的半导体器件的例子，是SiC DI(Double Implanted：双注入)MISFET的示意性的剖视结构图。
图31是能够应用于第一或第二实施方式的半导体装置的半导体器件的例子，是SiC沟槽(T：Trench)MISFET的示意性的剖视结构图。
图32表示采用第一或第二实施方式的半导体装置构成的三相交流逆变器的示意性的电路结构，(a)是作为半导体器件采用SiC MISFET并在电源端子PL、接地端子NL间连接有缓冲电容器的电路结构例，(b)是作为半导体器件采用IGBT并在电源端子PL、接地端子NL间连接有缓冲电容器的电路结构例。
图33是利用作为半导体器件采用了SiC MISFET的第一或第二实施方式的半导体装置构成的三相交流逆变器的示意性的电路结构图。
图34是利用作为半导体器件采用了IGBT的第一或第二实施方式的半导体装置构成的三相交流逆变器的示意性的电路结构图。
具体实施方式
接下来，参照附图对实施方式进行说明。在以下附图的记载中，对相同或类似的部分标记相同或类似的符号。但是应注意：附图为示意性的，厚度与平面尺寸的关系、各层的厚度比率等不同于实际情况。因此，具体的厚度、尺寸应参考以下的说明来进行判断。另外，各图相互间当然也包含彼此的尺寸关系、比率不同的部分。
另外，以下所示的实施方式用于例示使技术思想具体化的装置、方法，构成部件的材质、形状、结构、配置等并不特定于下述内容。该实施方式能够基于权利要求书进行各种变更。
[比较例1]
如上所述，随着功率模块的结温Tj的上升，对于铝线的功率循环耐受容量提出了更高的要求。因此，如图1所示，在比较例1的半导体装置中，使用了铜线18将第一基板电极10B与第二基板电极20B连接。具体而言，是在第一基板电极10B上配置半导体芯片12，并向半导体芯片12上的源极焊盘电极14的预定位置18B施加超声波来接合铜线18。符号16表示栅极焊盘电极。
但是，若采用比较例1的半导体装置，则在接合铜线18时需要非常大的超声波功率，会导致器件受损。或者是需要制作用于防止破坏的焊盘结构，会导致器件结构变得复杂。
[第一实施方式]
(半导体装置)
图2是第一实施方式的半导体装置的示意性的鸟瞰图。
如图2(a)所示，第一实施方式的半导体装置具备半导体芯片12、和以覆盖半导体芯片12上的源极焊盘电极14的方式形成的高耐热性的烧成膜22。
例如，高耐热性的烧成膜22可以是银烧成膜，也可以是铜烧成膜。以下将银烧成膜称为“银烧成盖22”，将铜烧成膜称为“铜烧成盖22”。
如图2(b)所示，将半导体芯片12配置在第一基板电极10B上，利用超声波在银烧成盖22上接合铜线18的一端。并利用超声波使铜线18的另一端接合于第二基板电极20B。
此外，也可以取代铜线18而采用铝线、包覆线。就包覆线而言，中心部由Cu形成且中心部以覆盖Cu的方式接合有Al。包覆线与铝线相比具有高耐热性、低热阻性。
这里，第一基板电极10B、第二基板电极20B可以通过由金属、陶瓷、金属的接合体构成的电路基板的芯片搭载面侧的导体图案来构成，所述电路基板例如是DBC(DirectBonding Copper：直接键合铜)基板、DBA(Direct Brazed Aluminum：直接钎焊铝)基板、AMB(Active Metal Brazed：活性金属钎焊、Active Metal Bond：活性金属键合)基板等绝缘基板(电路基板)。作为绝缘基板的表面侧电极和背面侧电极的金属材料，基本上使用相同的材料。例如，若是DBC基板则能够采用Cu/Al2O3/Cu结构，如果是DBA基板则能够采用Al/AlN/Al结构，如果是AMB基板则能够采用Cu/Si3N4/Cu结构等。其中，对于表面侧电极和背面侧电极而言，作用会有所不同。表面侧电极接合芯片、电极等而分别切成图案，用作正(P)侧功率电极、负(N)侧功率电极、输出(Out)侧功率电极等。背面侧电极与冷却器接合或与散热器接合而向下传热。
如上所述，在第一实施方式的半导体装置中，采用了在半导体芯片12上的源极焊盘电极14上以高耐热烧成材料(银烧成或铜烧成)进行覆盖的结构。由此，能够缓和铜线接合时的超声波功率，防止器件因铜线接合时的大负荷而受损，因此能够使功率循环耐受容量提高。
(利用银烧成盖来防止器件受损的效果)
图3是表示第一实施方式的半导体装置的仿真模型的示意性的剖视结构图。这里，如图3所示那样，在碳化硅(SiC)基体的半导体芯片12上形成有氧化膜25并在氧化膜25上形成铝电极26，且在铝电极26上经镀敷工序形成金(Au)薄膜28并在金薄膜28上形成有银烧成盖22。
虽然在此例示了铝电极26，但是电极的材料并不限定于铝而也可以是铜(Cu)。
另外，金薄膜28用于使银烧成盖22附着。也可以代替金薄膜28而形成银薄膜或者钯(Pd)薄膜。
图4是表示图3所示的仿真模型的效果的曲线图表。横轴表示银烧成盖22的膜厚t。纵轴表示在向银烧成盖22施加位移DA时作用于氧化膜25的最大主应力比。在此将作用于无银烧成盖22的情况的氧化膜25的应力设为“1”(参照点P1)。
参见图4所示箭头P可知，在有银烧成盖22的情况下，能够大幅降低作用于氧化膜25的应力。具体而言，在银烧成盖22的膜厚t为5μm的情况下，最大主应力比约为0.4左右(参照点P2)。在银烧成盖22的膜厚t为10μm的情况下，最大主应力比约为0.2左右(参照点P3)。在银烧成盖22的膜厚t为30μm的情况下，最大主应力比约为0.1左右(参照点P4)。银烧成盖22的膜厚t并无特别限定，优选为例如约10μm～100μm左右(参照线Q)。
如上所述，在第一实施方式的半导体装置中，对于器件上的电极通过银烧成来进行覆盖。此盖结构起到缓冲材料的作用，因此能够防止铜线18受损。当然，若使用铜线18则能够实现非常强的接合，也具有使功率循环耐受容量增加的效果。
[比较例2]
如上所述，随着功率模块的结温Tj的上升，对铝线的功率循环耐受容量的要求更高。因此，在比较例2的半导体装置中，是如图5所示那样，使用导体件、电极柱等上部配线24将第一基板电极10B与第二基板电极20B连接。
在这样使用导体件、电极柱等上部配线24的情况下，作为其接合材料使用无铅类的焊料17A、17B。无铅类的焊料17A、17B是以锡(Sn)为主成分并作为添加物配合有银(Ag)、铜(Cu)、锡(Sn)等的Sn类的焊料。但是，在使用无铅类的焊料17A、17B的情况下，对于碳化硅(SiC)等具备200℃以上的耐热性的器件而言，由于熔点接近结温Tj＝200℃且ΔTj功率循环增大，因此会导致功率循环耐受容量减小。
[第二实施方式]
(半导体装置)
图6是第二实施方式的半导体装置的示意性的鸟瞰图。
如图6所示，第二实施方式的半导体装置与第一实施方式同样地具备半导体芯片12、和以覆盖半导体芯片12上的源极焊盘电极14的方式形成的高耐热性的烧成膜22。
与第一实施方式同样地，高耐热性的烧成膜22是银烧成盖22(或铜烧成盖22)。银烧成盖22的膜厚t并无特别限定，优选为例如约10μm～100μm左右。
半导体芯片12配置在第一基板电极10B上，而平板状的上部配线24的一端以焊料26A为接合材料接合在高耐热性的烧成膜22上。另外，上部配线24的另一端以焊料26B为接合材料接合于第二基板电极20B。焊料26A、26B能够与比较例2同样地采用无铅类的焊料。
如上所述，在第二实施方式的半导体装置中，在半导体芯片12上的源极焊盘电极14上以高耐热烧成材料(银烧成或铜烧成)进行覆盖并在其上使用现有的焊料。由此，能够减小作用于焊料的累积等效应变，提高功率循环耐受容量。
(对有无银烧成盖时的累积等效应变的比较)
图7是表示第二实施方式的半导体装置的仿真模型1(盖结构)的示意性的剖视结构图。如图7所示，在仿真模型1中是在银烧成盖22上使用无铅类的焊料17A。设定为焊料17A、17B的膜厚是100μm而银烧成盖22的膜厚是50μm的情况。基板电极10B的背面设定为以65℃进行冷却。
图8是表示比较例2的半导体装置的仿真模型2(焊料结构)的示意性的剖视结构图。如图8所示，在仿真模型2中仅使用无铅类的焊料17A、17B。即，银烧成盖22并未配置到半导体芯片12上而仅配置于半导体芯片12下。焊料17A、17B的膜厚设定为150μm的情况。
图9是表示仿真模型1与仿真模型2的比较结果的曲线图表。纵轴表示焊料累积等效应变，横轴表示结温Tj。累积等效应变用作推定焊料等材料的寿命时的标准。在相同材料的情况下，累积等效应变越大寿命就越短。
将点S1与点S2连结的线段S表示仿真模型2(焊料结构)中的累积等效应变的变化。观察线段S可知：在焊料结构中，随着结温Tj的上升，累积等效应变增大。
另一方面，将点C1与点C2连结的线段C+S表示仿真模型1(盖结构)中的累积等效应变的变化。观察线段C+S亦可得知：在盖结构中，由于银烧成盖22的缓冲效果，即使结温Tj发生变化，累积等效应变也基本不变。
具体而言，采用盖结构，与焊料结构相比，在结温Tj为120℃的情况下，累积等效应变减少了约32％左右(参照点C1、点S1)。而在结温Tj为200℃的情况下，累积等效应变减少了约44％左右(参照点C2、点S2)。
如上所述，采用盖结构具有如下效果：能够提高功率循环耐受容量，或者，即使ΔTj功率循环、MaxTj增大，也能够保持功率循环耐受容量。
这里，功率循环如下式所示，ΔTj是功率循环开启时的结温Tj的最大值MaxTj与功率循环关闭时的结温MinTj的差。在MaxTj为150℃而MinTj为50℃的情况下，ΔTj功率循环为100℃，在MaxTj为200℃而MinTj为50℃的情况下，ΔTj功率循环为150℃。
[式1]
ΔTj＝MaxTj-MinTj
在图10中示意性地表示了ΔTj功率循环与功率循环寿命的关系。如图10所示，通常在ΔTj功率循环较低时具有寿命延长的倾向(参照T1)，而在ΔTj功率循环较高时则具有寿命缩短的倾向(参照T2)。此外还具有以点接合的线材容易发生龟裂18C(参照图11)而以面接合的导体件寿命较长的倾向。
(焊料的寿命与累积等效应变的关系)
接下来对疲劳寿命的计算方法进行说明。反复施加引发非弹性应变(塑性应变、蠕变应变)的较大的载荷而以较少的重复次数(105次循环以下)发生疲劳破坏的情况被称为低循环疲劳。低循环疲劳的疲劳寿命可利用以下所示的曼森科芬法(Manson-Coffin)表示。
[式2]
Δεp·Njn＝C
ΔεP是塑性应变振幅[－]，Nj是塑性疲劳(疲劳寿命)[次]，C、N是材料物性值。
[式3]
Figure BDA0003751615550000091
εac＿ne(fin＿step)是第二次循环的累积等效应变，εac＿ne(ref＿step)是第一次循环的累积等效应变。如图12所示，应变量会随着时间的经过而发生饱和，因此式3取第一次循环和第二次循环之间。根据曼森科芬法，当ΔεP较小时寿命会延长。根据盖结构可知，由于累积等效应变减小，因此焊料的寿命会延长。
如上所述，在第二实施方式的半导体装置中，在银烧成盖22上使用了无铅类的焊料17A、17B。由此，利用银烧成盖22来缓冲焊料直接承受的应力，从而能够使作用于焊料的累积等效应变减少，并使功率循环耐受容量提高。
[制造方法]
以下对第一或第二实施方式的半导体装置的制造方法进行说明。
首先，如图13(a)所示那样，在半导体芯片12的上部形成金薄膜28。接下来，如图13(b)所示那样，使用刮刀30从掩模28M的开口部压入烧成膏22P，对与源极焊盘电极14对应的区域进行掩模印刷。接下来，如图13(c)所示那样，使掩模印刷了烧成膏22P的半导体芯片12在热板32上干燥。最后，如图13的(d)所示那样，使用加热板34U、34D对半导体芯片12进行烧成(热+加压)。由此，能够如图14所示那样，在半导体芯片12的上部形成银烧成盖22。
此外，在上述的工序中，也可以代替掩模印刷而采用分配法。使用分配法也能够制成品质为相同程度的烧成膜。
[模块]
以下对具备多个第一或第二实施方式的半导体装置的功率模块的结构进行说明。
图15是采用了第二实施方式的半导体装置的模块的结构图(照片)，(a)是鸟瞰图、(b)是俯视图。如图15所示那样将第一基板电极10B与第二基板电极20B利用上部配线24进行了连接。从第一基板电极10B和第二基板电极20B分别向外引出了信号电极端子G1、D1、S1、信号电极端子G4、D4、S4。当然，也可以将第一基板电极10B与第二基板电极20B以外的基板电极利用上部配线24进行连接。并在基板电极10B上连接与高电平侧的MISFETQ1的漏极D1对应的功率端子P，且在基板电极20B上连接与低电平侧的MISFETQ4的漏极D4或是与高电平侧的MISFETQ1的源极S1对应的功率端子O(输出端子)。此外，在与低电平侧的MISFETQ1的源极焊盘电极S1经由上部配线24连接的焊盘电极上连接与低电平侧的MISFETQ4的源极S4对应的功率端子N。在以上的说明中，高电平侧的MISFETQ1和低电平侧的MISFETQ4例如与图26(a)所示那样的构成二对一模块的电路的半导体器件对应。此外，也可以是图26(b)所示那样的二对一模块的IGBT Q1·Q4。以下相同。
图16是图15所示模块成型后的结构图(照片)。如图16所示那样，第一基板电极10B、第二基板电极20B由树脂M等成型。
图17及图18是将图15所示模块局部放大的照片。如图17及图18所示那样在第一基板电极10B上配置有半导体芯片12。在半导体芯片12上形成银烧成盖22并在该银烧成盖22上使用焊料26A、26B接合有上部配线24。
图19是表示图15所示模块的整体的照片。图20是将图15所示模块局部放大的照片。如图19及图20所示那样，半导体芯片12经由引线W与信号电极端子G1、D1、S1、信号电极端子G4、D4、S4进行了连接。
图21是采用了第一实施方式的半导体装置的模块的示意性的结构图。也能够如图21所示那样在一个半导体芯片12上接合多根铜线18。
[接合能量]
接下来对利用超声波进行接合时的接合能量进行说明。
接合能量如下式所示那样由接合时的摩擦系数μ、速度v、压力P被时间积分而得到。摩擦系数μ和速度v都是压力P的函数。通常，接合能量越高接合力就越强。
[式4]
接合能力＝∫μ(P)v(P)PdμdvdP
[ΔTj功率循环测试]
第一或第二实施方式的半导体装置的ΔTj功率循环测试中的电流IC和温度T的变化的示意图如图22所示。
如图22所示，ΔTj功率循环测试是使接合温度以相对较短的时间周期上升、下降的测试，例如能够对引线接合部等的寿命进行评价。
在进行功率循环试验时，如图22所示，对半导体装置模块反复进行通断电而使芯片发热。在第一或第二实施方式的半导体装置的ΔTj功率循环测试中，例如是Tj＝150℃为2s之后进行关断并在达到冷却温度为止的时间(例Tj＝50℃、关断时间＝18s)内重复进行。
[热循环测试]
在第一或第二实施方式的半导体装置中，如图23所示，表示热循环测试中的温度曲线例。热循环测试在大气环境中进行且在负40℃～正150℃的范围内实施。热循环的一个循环的周期为80分钟，其中，在负40℃下为30分钟，从负40℃到正150℃的升温时间为10分钟，在正150℃下为30分钟，从正150℃到负40℃的冷却时间为10分钟。每经过100个循环时则对顺向电压降Vf、反向耐压Vr进行测定而未见特性劣化。
通常，在热循环测试、或功率循环试验中，当接合部开始劣化时，在流通顺向等的高电流的试验中电阻增大，顺向电压Vf发生变化。
就功率循环耐受容量而言，在即使发生特性劣化其劣化进展也较为缓慢的情况下，能够评价为功率循环耐受容量较高。
根据以上的ΔTj功率循环测试和热循环测试的结果，充分地确保了第一或第二实施方式的半导体装置的铜线18或上部配线24的接合强度。
另外，在第一或第二实施方式中，是在银烧成盖22上配置铜线18或焊料26A，但是并不限定于此。例如，也可以在银烧成盖22上通过银烧成来接合上部配线24。能够通过在银烧成盖22上进行银烧成而使膜厚增加。由此，能够比焊料26A更加耐热而使可靠性提高。
[半导体装置的具体例]
在第一或第二实施方式的半导体装置20中，一对一模块的SiC MISFET的示意性的电路表达如图24(a)所示，一对一模块的IGBT的示意性的电路表达如图24(b)所示。
在图24(a)中示出了与MISFETQ反向并联连接的二极管DI。MISFETQ的主电极由漏极端子DT和源极端子ST表示。同样地，在图24(b)中示出了与IGBTQ反向并联连接的二极管DI。IGBTQ的主电极由集电极端子CT和发射极端子ET表示。作为二极管DI，也可以外装快速恢复二极管(FRD)、肖特基势垒二极管(SBD)。另外，也可以仅使用在MISFET的半导体基板中形成的二极管。
另外，在第一或第二实施方式的半导体装置20中，一对一模块的SiC MISFET的详细电路表达如图25所示。
另外，也可以在一个模块中内置多个MISFET。作为一例能够安装五个芯片(MISFET×5)，各个MISFETQ能够并联连接达五个。此外，在五个芯片中也能够将一部分作为二极管DI安装。
具体而言是如图25所示那样与MISFETQ并联地连接感测用MISFETQs。感测用MISFETQs与MISFETQ在同一芯片内作为微细晶体管形成。在图25中，SS是源极感测端子，CS是电流感测端子，G是栅极信号端子。此外，在第一或第二实施方式中也是在半导体器件Q上，感测用MISFETQs在同一芯片内作为微细晶体管形成。
另外，在第一或第二实施方式的半导体装置20T中，二对一模块的SiC MISFET的示意性的电路表达如图26(a)所示。
如图26(a)所示，与两个MISFETQ1·Q4、MISFETQ1·Q4反向并联连接的二极管D1·D4内置于一个模块。G1是MISFETQ1的栅极信号端子，S1是MISFETQ1的源极端子。G4是MISFETQ4的栅极信号端子，S4是MISFETQ4的源极端子。P是正侧电源输入端子，N是负侧电源输入端子，O是输出端子。
另外，在第一或第二实施方式的半导体装置20T中，二对一模块的IGBT的示意性的电路表达如图26(b)所示。如图26(b)所示，与两个IGBTQ1·Q4、IGBTQ1·Q4反向并联连接的二极管D1·D4内置于一个模块。G1是IGBTQ1的栅极信号端子，E1是IGBTQ1的发射极端子。G4是IGBTQ4的栅极信号端子，E4是IGBTQ4的发射极端子。P是正侧电源输入端子，N是负侧电源输入端子，O是输出端子。
(半导体器件的结构例)
作为能够适用于第一或第二实施方式的半导体器件的例子，SiC MISFET的示意性的剖面结构如图27(a)所示，IGBT的示意性的剖面结构如图27(b)所示。
作为能够适用于第一或第二实施方式的半导体器件110(Q)的例子，SiC MISFET的示意性的剖面结构如图27(a)所示那样具备：由n-高电阻层构成的半导体基板126；在半导体基板126的表面侧形成的p型区域128；在p型区域128的表面形成的源极区域130；在p型区域128间的半导体基板126的表面上配置的栅极绝缘膜132；在栅极绝缘膜132上配置的栅电极138；与源极区域130和p型区域128连接的源电极134；在与半导体基板126的表面为相反侧的背面配置的n+漏极区域124；以及与n+漏极区域124连接的漏电极136。
在图27(a)中，半导体器件110是由平面栅极型n沟道纵型SiC MISFET构成，但是也可以如后述的图31所示那样由n沟道纵型SiC TMISFET等构成。
并且，就能够适用于第一或第二实施方式的半导体器件110(Q)而言，也能够代替SiC MISFET而采用GaN类FET等。
能够适用于第一或第二实施方式的半导体器件110能够采用SiC类、GaN类中任一的功率器件。
此外，能够适用于第一或第二实施方式的半导体器件110能够采用带隙能量例如为1.1EV～8EV的所谓宽隙型的半导体。
同样地，作为能够适用于第一或第二实施方式的半导体器件110A(Q)的例子，IGBT如图27(b)所示那样具备：由n-高电阻层构成的半导体基板126；在半导体基板126的表面侧形成的p型区域128；在p型区域128的表面形成的发射极区域130E；在p型区域128间的半导体基板126的表面上配置的栅极绝缘膜132；在栅极绝缘膜132上配置的栅电极138；与发射极区域130E和p型区域128连接的发射电极134E；在与半导体基板126的表面为相反侧的背面配置的p+集电极区域124P；以及与p+集电极区域124P连接的集电极136C。
在图27(b)中，半导体器件110A是由平面栅极型的n沟道纵型IGBT构成，但是也可以由沟槽栅极型n沟道纵型IGBT等构成。
作为能够适用于第一或第二实施方式的半导体器件110的例子，包含源极焊盘电极SP、栅极焊盘电极GP的SiC MISFET的示意性的剖面结构如图28所示。栅极焊盘电极GP与在栅极绝缘膜132上配置的栅电极138连接，源极焊盘电极SP连接于与源极区域130和p型区域128连接的源电极134。
另外，栅极焊盘电极GP和源极焊盘电极SP如图28所示那样在将半导体器件110的表面覆盖的钝化用的层间绝缘膜144上配置。此外，也可以在栅极焊盘电极GP和源极焊盘电极SP的下方的半导体基板126内与图27(a)或图28的中央部同样地形成微细结构的晶体管结构。
此外，如图28所示，也可以在中央部的晶体管结构中，在钝化用的层间绝缘膜144上延伸配置有源极焊盘电极SP。
作为能够适用于第一或第二实施方式的半导体器件110A的例子，包含源极焊盘电极SP、栅极焊盘电极GP的IGBT的示意性的剖面结构如图29所示。栅极焊盘电极GP与在栅极绝缘膜132上配置的栅电极138连接，发射极焊盘电极EP连接于与发射极区域130E和p型区域128连接的发射电极134E。
并且，栅极焊盘电极GP和发射极焊盘电极EP如图29所示那样在将半导体器件110A的表面覆盖的钝化用的层间绝缘膜144上配置。此外，也可以在栅极焊盘电极GP和发射极焊盘电极EP的下方的半导体基板126内与图27(b)或图29的中央部同样地形成有微细结构的IGBT结构。
此外，如图29所示，也可以在中央部的IGBT结构中，在钝化用的层间绝缘膜144上延伸配置有发射极焊盘电极EP。
—SiC DIMISFET—
作为能够适用于第一或第二实施方式的半导体器件110的例子，SiC DIMISFET的示意性的剖面结构如图30所示。
能够适用于第一或第二实施方式的SiC DIMISFET如图30所示那样具备：由n-高电阻层构成的半导体基板126；在半导体基板126的表面侧形成的p型区域128；在p型区域128的表面形成的n+源极区域130；在p型区域128间的半导体基板126的表面上配置的栅极绝缘膜132；在栅极绝缘膜132上配置的栅电极138；与源极区域130和p型区域128连接的源电极134；在与半导体基板126的表面为相反侧的背面配置的n+漏极区域124；以及与n+漏极区域124连接的漏电极136。
在图30中，半导体器件110通过双离子注入(DI)形成p型区域128、以及在p型区域128的表面形成的n+源极区域130，源极焊盘电极SP连接于与源极区域130和p型区域128连接的源电极134。栅极焊盘电极GP(省略图示)连接于栅极绝缘膜132上配置的栅电极138。另外，源极焊盘电极SP和栅极焊盘电极GP(省略图示)如图30所示那样在将半导体器件110的表面覆盖的钝化用的层间绝缘膜144上配置。
如图30所示，SiC DIMISFET在被p型区域128夹持的由n-高电阻层构成的导体基板126内形成由虚线所示的耗尽层，因此形成伴随接合型FET(JFET)效果的沟道电阻RJFET。并且，如图30所示，在p型区域128/半导体基板126间形成体二极管BD。
—SiC TMISFET—
作为能够适用于第一或第二实施方式的半导体器件110的例子，SiC TMISFET的示意性的剖面结构如图31所示。
能够适用于第一或第二实施方式的SiC TMISFET如图31所示那样具备：由n层构成的半导体基板126N；在半导体基板126N的表面侧形成的p型区域128；在p型区域128的表面形成的n+源极区域130；贯通p型区域128并在形成到半导体基板126N的沟槽内隔着栅极绝缘层132和层间绝缘膜144U·144B形成的沟槽栅电极138TG；与源极区域130和p型区域128连接的源电极134；在与半导体基板126N的表面为相反侧的背面配置的n+漏极区域124；以及与n+漏极区域124连接的漏电极136。
在图31中，半导体器件110贯通p型区域128，在形成到半导体基板126N的沟道内形成隔着栅极绝缘层132和层间绝缘膜144U·144B形成的沟槽栅电极138TG，源极焊盘电极SP连接于与源极区域130和p型区域128连接的源电极134。栅极焊盘电极GP(图示省略)与在栅极绝缘膜132上配置的栅电极138连接。并且，源极焊盘电极SP和栅极焊盘电极GP(图示省略)如图31所示那样配置在将半导体器件110的表面覆盖的钝化用的层间绝缘膜144U上。
在SiC TMISFET中，不形成伴随SiC DIMISFET那样的接合型FET(JFET)效果的沟道电阻RJFET。并且，在p型区域128/半导体基板126N间形成体二极管BD。
在使用第一或第二实施方式的半导体装置构成的三相交流逆变器140的示意性的电路结构中，作为半导体器件采用SiC MISFET，在电源端子PL、接地端子NL间连接缓冲电容器C的电路结构例，如图32(a)所示。同样地，在使用第一或第二实施方式的半导体装置构成的三相交流逆变器140A的示意性的电路结构中，作为半导体器件采用IGBT，在电源端子PL、接地端子NL间连接缓冲电容器C的电路结构例，如图32(b)所示。
在将第一或第二实施方式的半导体装置与电源E连接时，会由于连接线具有的电感L而使SiC MISFET、IGBT的开关速度较快，因此会产生较大的浪涌电压Ldi/dt。例如，在电流变化di＝300A、伴随开关的时间变化dt＝100nsec的情况下，di/dt＝3×109(A/s)。根据电感L的值不同，浪涌电压Ldi/dt的值会发生变化，而该浪涌电压Ldi/dt会叠加于电源V。利用在电源端子PL与接地端子NL间连接的缓冲电容器C能够吸收该浪涌电压Ldi/dt。
(采用半导体装置的应用例)
接下来，参照图33来说明由作为半导体器件采用SiC MISFET的第一或第二实施方式的半导体装置构成的三相交流逆变器140。
如图33所示，三相交流逆变器140具备：栅极驱动部150、与栅极驱动部150连接的半导体装置部152、三相交流电机部154。半导体装置部152与三相交流电机部154的U相、V相、W相对应地连接U相、V相、W相的逆变器。在此，栅极驱动部150与SiC MISFETQ1·Q4、SiCMISFETQ2·Q5及SiC MISFETQ3·Q6连接。
半导体装置部152在连接蓄电池(E)146的变换器148的正端子(+)与负端子(－)间连接且具备逆变器结构的SiC MISFETQ1·Q4、Q2·Q5、和Q3·Q6。并且，在SiC MISFETQ1～Q6的源极·漏极间分别反向并联地连接有续流二极管D1～D6。
接下来，参照图34来说明由作为半导体器件采用IGBT的第一或第二实施方式的半导体装置20T构成的三相交流逆变器140A。
如图34所示，三相交流逆变器140A具备：栅极驱动部150A、与栅极驱动部150A连接的半导体装置部152A、三相交流电机部154A。半导体装置部152A与三相交流电机部154A的U相、V相、W相对应地连接U相、V相、W相的逆变器。在此，栅极驱动部150A与IGBTQ1·Q4、IGBTQ2·Q5及IGBTQ3·Q6连接。
半导体装置部152A在连接蓄电池(E)146A的转换器148A的正端子(+)与负端子(－)间连接且具备逆变器结构的IGBTQ1·Q4、Q2·Q5、和Q3·Q6。此外，在IGBTQ1～Q6的发射极·集电极间分别反向并联地连接有续流二极管D1～D6。
本实施方式的半导体装置或功率模块可以形成为一对一、二对一、四对一、六对一或是七对一型中的任意形式。
如以上说明的那样，根据本实施方式，可提供能够使功率循环耐受容量提高的半导体装置、功率模块及其制造方法。
[其它实施方式]
虽然如上所述对实施方式进行了记载，但是构成本发明的一部分的论述和附图仅为例示而非限定。本领域人员应该能够由本发明想到各种代替实施方式、实施例和运用技术。
这样，包含在此没有记载的各种实施方式等。
产业上的利用可能性
本实施方式的半导体装置和功率模块能够应用于IGBT模块、二极管模块、MOS模块(Si、SiC、GaN)等半导体模块的制作技术，并适用于面向HEV/EV的逆变器、面向产业设备的逆变器、变换器等广泛的应用领域。
符号说明
10B—第一基板电极；12—半导体芯片；14—源极焊盘电极；16—栅极焊盘电极；17A、17B、26A、26B—焊料；18—铜线；20B—第二基板电极；22—高耐热性的烧成膜(银烧成盖，铜烧成盖)；24—上部配线；25—氧化膜；26—铝电极；28—金薄膜；Tj—结温。

Claims (27)

1.一种半导体装置，其特征在于，具备：
形成在绝缘基板上的第一基板电极、第二基板电极及第三基板电极；
半导体芯片，其配置在所述第一基板电极上，并根据连接于控制电极的信号，进行第一电极和与所述第一电极电连接的第二电极之间的开关动作；
高耐热性膜，其形成在所述半导体芯片的表面侧，并与所述第一电极电连接，且覆盖所述第一电极的大部分；
平板状引线或多个第一引线，其对所述高耐热性膜与所述第二基板电极之间进行电连接；以及
第二引线，其对所述第三基板电极与所述控制电极之间进行电连接。
2.根据权利要求1所述的半导体装置，其特征在于，
还具备绝缘膜，该绝缘膜形成为覆盖所述半导体芯片的所述表面，
所述半导体芯片具备功率用晶体管，
所述第一电极设置在所述绝缘膜上，在设置所述第一电极的部位的下方形成有所述功率用晶体管，
在所述高耐热性膜上接合有引线的一端。
3.根据权利要求2所述的半导体装置，其特征在于，
所述引线包括铜线、铝线或包覆线，
所述第一引线的厚度比所述第一基板电极、所述第二基板电极及所述第三基板电极的各自的厚度厚，
所述引线的一端进行了超声波接合。
4.根据权利要求1所述的半导体装置，其特征在于，
将焊料作为接合材料而在所述高耐热性膜上接合所述平板状引线或所述多个第一引线的一端，所述平板状引线或所述多个第一引线的厚度比所述第一基板电极、所述第二基板电极及所述第三基板电极的各自的厚度厚。
5.根据权利要求1所述的半导体装置，其特征在于，
所述高耐热性膜是银烧成膜。
6.根据权利要求1所述的半导体装置，其特征在于，
所述高耐热性膜是铜烧成膜。
7.根据权利要求1至6中任一项所述的半导体装置，其特征在于，
在所述第一电极与所述高耐热性膜之间具备金薄膜、银薄膜或钯膜的任一电极表面薄膜。
8.根据权利要求1至6中任一项所述的半导体装置，其特征在于，
所述高耐热性膜的厚度处于10μm～100μm的范围。
9.根据权利要求1所述的半导体装置，其特征在于，
所述半导体芯片包括第一SIC MISFET和第二SIC MISFET，与所述第一SIC MISFET及所述第二SIC MISFET分别反向并联连接的第一二极管及第二二极管内置于一个模块内，
所述半导体芯片上的第一电极包括源极焊盘电极。
10.一种功率模块，其特征在于，
具备多个权利要求1至6中任一项所述的半导体装置。
11.根据权利要求1所述的半导体装置，其特征在于，
所述半导体芯片具备宽隙型半导体。
12.根据权利要求1所述的半导体装置，其特征在于，
所述半导体芯片具备100℃以上的ΔTj功率循环耐受容量。
13.一种半导体装置，其特征在于，具备：
绝缘基板；
配置在所述绝缘基板上的第一基板电极、第二基板电极及第三基板电极；
半导体芯片，其配置于所述第一基板电极上，并根据连接于控制电极的信号，进行第一电极和与所述第一电极电连接的第二电极之间的开关动作；
高耐热性膜，其形成在所述半导体芯片的表面侧，并与所述第一电极电连接，且覆盖所述第一电极的大部分；
平板状引线，其对所述高耐热性膜与所述第二基板电极之间进行电连接；
第二引线，其对所述半导体芯片的表面侧的没有被所述高耐热性膜覆盖的所述控制电极与所述第三基板电极之间进行连接；以及
树脂，其密封所述第一基板电极、所述第二基板电极、所述第三基板电极、所述半导体芯片、所述平板状引线以及所述第二引线。
14.根据权利要求13所述的半导体装置，其特征在于，
在所述高耐热性膜与所述平板状引线之间具有比所述高耐热性膜厚的焊料层。
15.根据权利要求13或14所述的半导体装置，其特征在于，
所述平板状引线的厚度比所述半导体芯片和所述高耐热性膜的厚度厚。
16.根据权利要求13或14所述的半导体装置，其特征在于，
形成有多个所述高耐热性膜，通过同一所述平板状引线将多个所述高耐热性膜共同连接。
17.一种半导体装置的制造方法，其特征在于，具有：
形成与半导体芯片上的第一电极电连接并覆盖所述第一电极的大部分的高耐热性的导电性膜的工序，该半导体芯片配置在第一基板电极上，并根据连接于控制电极的信号，进行所述第一电极和与所述第一电极电连接的第二电极之间的开关动作；
对所述高耐热性的导电性膜进行加热、加压而成为盖结构的高耐热性膜的工序；
通过平板状引线或多个第一引线对所述高耐热性膜和与所述第一基板电极不同的第二基板电极之间进行电连接的工序；以及
通过第二引线对与所述第一基板电极及所述第二基板电极不同的第三基板电极和所述控制电极之间进行电连接的工序。
18.根据权利要求17所述的半导体装置的制造方法，其特征在于，
在所述高耐热性的导电性膜上超声波接合第一引线即铜线或铝线的一端，所述第一引线的厚度比所述第一基板电极、所述第二基板电极及所述第三基板电极的各自的厚度厚。
19.根据权利要求17所述的半导体装置的制造方法，其特征在于，
以焊料为接合材料而在所述高耐热性膜上接合所述平板状引线的一端，所述平板状引线的厚度比所述第一基板电极、所述第二基板电极及所述第三基板电极的各自的厚度厚。
20.根据权利要求17所述的半导体装置的制造方法，其特征在于，
所述高耐热性膜包括银烧成膜或铜烧成膜。
21.根据权利要求17所述的半导体装置的制造方法，其特征在于，
通过掩模印刷或者分配法形成所述高耐热性的导电性膜。
22.根据权利要求17所述的半导体装置的制造方法，其特征在于，
通过镀敷工序在所述第一电极上形成金薄膜、银薄膜或者钯薄膜的任一薄膜，在所述薄膜上形成所述高耐热性膜。
23.根据权利要求17所述的半导体装置的制造方法，其特征在于，
所述半导体芯片包括第一SIC MISFET和第二SIC MISFET，与所述第一SIC MISFET及所述第二SIC MISFET分别反向并联连接的第一二极管及第二二极管内置于一个模块内，
所述半导体芯片上的电极包括源极焊盘电极。
24.根据权利要求17至23中任一项所述的半导体装置的制造方法，其特征在于，
所述半导体芯片由多个芯片构成，
具备并联连接所述多个芯片的工序。
25.一种半导体模块，其特征在于，具备：
分别独立地形成在第一绝缘基板上的第一基板电极、第二基板电极及第三基板电极；
第一半导体芯片，其配置在所述第一基板电极上，并根据连接于第一控制电极的信号，进行第一电极和第二电极之间的开关动作；以及
第二半导体芯片，其配置在所述第二基板电极上，并根据连接于第二控制电极的信号，进行第三电极和第四电极之间的开关动作，
所述第一电极与所述第二基板电极之间经由第一平板状引线电连接，
所述第三电极与所述第三基板电极之间经由第二平板状引线电连接，
所述第一控制电极及所述第二控制电极分别通过引线与分别配置在所述第一基板电极及所述第二基板电极上的第二绝缘基板及第三绝缘基板的第三基板电极及第四基板电极连接，所述引线比所述第一平板状引线及第二平板状引线细。
26.一种半导体装置，其特征在于，具备：
第一基板电极及第二基板电极，其形成在第一绝缘基板上；
第三基板电极，其经由第二绝缘基板配置在所述第一基板电极或/和第二基板电极上；
半导体芯片，其配置于所述第一基板电极上，并根据连接于控制电极的信号，进行表面侧的第一电极和与所述第一基板电极电连接的第二电极之间的开关动作；
平板状引线，其对所述第一电极与所述第二基板电极之间进行电连接；以及
树脂，其密封所述第一基板电极、所述第二基板电极、所述第三基板电极、所述半导体芯片以及所述平板状引线，
所述平板状引线的厚度比所述半导体芯片厚。
27.根据权利要求1所述的半导体装置，其特征在于，
还具有：形成在所述绝缘基板上的第四基板电极；以及连接于所述第一电极与所述第四基板电极之间的引线。
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