CN113423864B - 氮化硅的选择性沉积 - Google Patents

氮化硅的选择性沉积 Download PDF

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CN113423864B
CN113423864B CN202080013812.3A CN202080013812A CN113423864B CN 113423864 B CN113423864 B CN 113423864B CN 202080013812 A CN202080013812 A CN 202080013812A CN 113423864 B CN113423864 B CN 113423864B
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silicon
silicon nitride
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nitride
dioxide
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CN113423864A (zh
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王瀚
B·C·亨德里克斯
E·孔多
T·H·鲍姆
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Entegris Inc
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Abstract

本发明的某些实施例利用低温原子层沉积方法来形成含有硅和氮的材料(例如，氮化硅)。所述原子层沉积使用四碘化硅(SiI4)或六碘化二硅(Si2I6)作为一种前体并且使用例如氨的含氮材料作为另一前体。在需要氮化硅的选择性沉积于二氧化硅上方进行沉积的情形中，首先用氨等离子体处理衬底表面。

Description

氮化硅的选择性沉积
技术领域
本发明涉及用于将氮化硅选择性沉积到微电子装置上的方法。
背景技术
氮化硅通常用于集成电路的制造中。例如，其常常在制造各种例如存储单元、逻辑装置、存储阵列等的微电子装置中用作绝缘材料。传统地，氮化硅膜经沉积于整个衬底表面上方，尽管所述沉积可能仅在某些区域中需要。因此，利用额外光刻和蚀刻步骤以去除任何非所需区域。高度需要减少所涉及的光刻和蚀刻步骤的数目作为用于减少总制造成本的手段。另外，如果仅在需要氮化硅处将其选择性沉积，那么光刻中的误差不影响经涂布区域的清晰度。
发明内容
使用氮化硅的选择性沉积可通过允许氮化硅仅在所选择并且所需区域中沉积来去除常规图案化步骤。在ALD或经脉冲的CVD模式中交替使用碘化硅前体与交替的热氮源，我们可优先将氮化硅沉积于现有氮化物表面(例如，氮化硅或氮化铝)和金属氧化物表面(例如氧化铝或氧化锆)上，而极其有限地沉积于暴露的二氧化硅表面上。另外，我们已发现通过用氨等离子体预处理不同氧化物表面，可将经由四碘化硅和例如氨的氮化合物的几纳米氮化硅选择性沉积于二氧化硅表面上，同时于一些“邻近”金属氧化物表面(例如，Al2O3和ZrO2)上实现无沉积或有限沉积。因此，此预处理步骤为“选择性”氮化物生长的基础。
附图说明
图1为在200℃下于如所描绘的各种氧化物衬底上的氮化硅(SiI4/NH3)沉积的图示。相对于循环数目绘制以埃为单位的厚度。
图2为在200℃下于如所描绘的各种氧化物表面上的氮化硅(SiI4/NH3)沉积的图示，其中各氧化物表面已用铵等离子体预处理。相对于循环数目绘制以埃为单位的厚度。
具体实施方式
本发明提供一种用于将氮化硅层选择性原子层沉积(ALD)到各种微电子装置衬底上的方法。出于本发明的目的，我们将ALD定义为将各种反应物和共反应物在空间或时间上分离的化学气相沉积模式，使得将衬底可替代地暴露于一种与共反应物分离的反应物。在第一实施例中，本发明提供一种用于将氮化硅选择性沉积于具有多个不同组成的表面的微电子装置衬底上的方法，所述方法包含在原子层沉积条件下，在约150℃到约400℃的温度下并且在低于约15托的压力下，使所述衬底与依序经脉冲的四碘化硅或六碘化二硅和含氮共反应物接触。在其它实施例中，温度为约175℃到约350℃，或约200℃到约250℃。当氮化硅膜以某可制造速率沉积于一些暴露的表面上并且其它表面接受可忽略或容易去除的氮化硅量时，实现选择性沉积。
在某些实施例中，微电子装置表面中的一者将包含氮化物表面，例如氮化钛、氮化铝或氮化硅。在其它实施例中，微电子装置表面中的一者将包含例如二氧化硅、氮氧化硅、二氧化锗、SiCO的介电质表面或低k表面。在一些实施例中，介电质包括二氧化硅。在一些实施例中，介电质为多孔材料。在一些实施例中，多孔介电质含有彼此连接的孔隙，而在其它实施例中，所述孔隙并不彼此连接。在一些实施例中，介电质包含低k材料，其定义为具有低于约4.0的介电值的绝缘体。在一些实施例中，低k材料的介电值低于约3.5、低于约3.0、低于约2.5或低于约2.3。在一些实施例中，第二表面包含Si-O键。在一些实施例中，第二表面例如通过等离子体处理去活化。在一些实施例中，第二表面为非导电表面。在某些实施例中，衬底包括第一表面，其中一些为介电质并且其中一些为金属相。在一些实施例中，所述表面中的一者为具有高于二氧化硅的k的介电质，例如氧化铝、氧化铪、氧化锆、氧化钛、镧系元素氧化物或此些氧化物中的任一者或全部的混合物。
在某些实施例中，装置衬底由至少一个二氧化硅表面和至少一个氧化铝表面构成，由此将所述氮化硅选择性沉积于所述氧化铝表面上。
在某些实施例中，装置衬底由至少一个二氧化硅表面和至少一个二氧化锆表面构成，由此将所述氮化硅选择性沉积于所述至少一个二氧化锆表面上。
在某些实施例中，装置衬底由至少一个二氧化硅表面和至少一个氧化铝表面构成，装置表面用氨等离子体预处理，由此将所述氮化硅选择性沉积于所述至少一个二氧化硅表面上。
在某些实施例中，装置衬底由至少一个二氧化硅表面和至少一个氧化铪表面构成，装置表面用氨等离子体预处理，由此将氮化硅选择性沉积于所述至少一个二氧化硅表面上。
在某些实施例中，装置衬底由至少一个二氧化硅表面和至少一个二氧化锆表面构成，装置表面用氨等离子体预处理，由此将所述氮化硅选择性沉积于所述至少一个二氧化硅表面上。
在此类实施例中，术语“选择性沉积”或“选择性”打算反映氮化硅于一个表面上的沉积相较于另一表面优先。已由格拉菲尔特(Gladfelter)[材料化学(Chem.Mater.)5,1372(1993)]给出的数值定义为两个表面之间覆盖度的差异，经标准化为相同两个表面的覆盖度的总和。实际上，工艺的选择性一般取决于膜的厚度。本发明使得在时的选择性能够大于90％。在其它实施例中，氮化硅于一个表面上相较于另一表面的优先沉积在超过/>时以大于95％的发生率发生。
此ALD方法利用四碘化硅(SiI4)或六碘化二硅(Si2I6)作为一种“硅”前体，并且使用含氮材料作为共反应物或作为另一前体。含氮材料可为有机的(例如，叔丁基肼)或无机的(例如NH3)。在一些实施例中，含氮材料的混合物可用作ALD之前体，并且在其它实施例中，仅一种含氮材料可用作ALD之前体(例如，仅NH3或仅叔丁基肼)。如本文中所使用，术语“含氮材料”可用以指代纯(例如，其完全为NH3或完全为叔丁基肼)前体材料，或可指代含有“含氮材料”作为含氮材料的混合物的一部分之前体。在某些实施例中，ALD可用以形成包括硅和氮的材料。此类材料可包含氮化硅、基本上由氮化硅组成或由氮化硅组成，和/或可具有其它组成。
我们已发现，通过用氨等离子体预处理不同氧化物表面，可将经由四碘化硅和例如氨的氮化合物的几纳米氮化硅选择性沉积于二氧化硅表面上，而于一些金属氧化物表面(例如，Al2O3和ZrO2)上实现无沉积或有限沉积。在需要氮化硅沉积优先在现有氮化硅、氮化铝或金属氧化物表面上(但不在二氧化硅表面上)发生的情况下，省略用氨等离子体进行的预处理步骤。
在原子层沉积中，依序处理步骤通常被称作“脉冲”或循环。因此，ALD方法是基于前驱化学物质的受控、自限的表面反应。本发明可用完全饱和反应或(如果更可制造)仅前体和共反应物的单独脉冲来实践。通过交替并且依序使衬底与前体接触来大体上避免气相反应。此可通过将衬底从不同反应物和共反应物的区域移动或通过在静止衬底上方交替气体流动来实践。在两种情况下，例如通过在反应物脉冲之间从反应室去除过量反应物和/或反应物副产物使气相反应物在时间上和在衬底表面上彼此分离。在一些实施例中，使一或多个衬底表面交替并且依序与两种或大于两种气相前体或反应物接触。使衬底表面与气相反应物接触意谓反应物蒸气与衬底表面接触有限的时段。换句话说，可理解为将衬底表面暴露于各气相反应物有限的时段。
简言之，通常在约0.5托到15托的减压下，将包含至少第一表面和第二不同表面的衬底加热到介于150℃到400℃范围内的适合沉积温度。在其它实施例中，温度为约175℃到350℃或200℃到250℃。沉积温度通常维持低于反应物的热分解温度，但应维持于足够高的温度以避免反应物的冷凝并且为所需“选择性”表面反应提供活化能。示范性表面包括例如氮化硅、氮化钛和氮化铝的氮化物和例如二氧化硅、氧化铝、氧化铪和氧化锆的氧化物。
使衬底表面与气相第一反应物接触。在某些实施例中，将气相第一反应物的脉冲提供到含有衬底的反应空间。在其它实施例中，将衬底移动到含有气相第一反应物的反应空间。条件通常经选择以使得不超过约一单层的第一反应物以自限方式经吸附于衬底表面上。所属领域的技术人员基于特定条件、衬底和反应器构形可容易地测定合适接触时间。例如通过用惰性气体冲洗或通过去除衬底存在的第一反应物而从衬底表面中去除(如果存在)过量第一反应物和反应副产物。
冲洗意谓例如通过用真空泵抽空腔室和/或通过用例如氩气或氮气的惰性气体替换反应器内部的气体而从衬底表面去除气相前体和/或气相副产物。在某些实施例中，冲洗时间为约0.05秒到20秒、在约1秒与10秒之间或在约1秒与2秒之间。然而必要时，例如在需要跨极高纵横比结构或具有复杂表面形态的其它结构的高度保形阶梯覆盖的情况下，可采用其它冲洗时间。
使衬底表面与气相第二气态反应物接触。在某些实施例中，将第二气态反应物的脉冲提供到含有衬底的反应空间。在其它实施例中，将衬底移动到含有气相第二反应物的反应空间。从衬底表面去除(如果存在)表面反应的过量第二反应物和气态副产物。重复接触和去除的步骤直到已在衬底的第一表面上选择性形成所需厚度的薄膜为止，其中各循环留下不超过约一个分子单层。可包括包含交替并且依序使衬底的表面与其它反应物接触的额外阶段以形成更复杂的材料，例如三元材料。
各循环的各阶段一般为自限的。在各阶段中供应过量反应物前体以使易受影响的结构表面饱和。表面饱和可确保反应物占据所有可用反应性位点(受例如物理尺寸或“位阻”限制)，因此确保极佳阶梯覆盖。通常，少于一个分子层的材料经各循环沉积，然而，在一些实施例中，在循环期间沉积超过一个分子层。
去除过量反应物可包括抽空反应空间的一些内含物和/或经氦气、氮气或另一惰性气体冲洗反应空间。在某些实施例中，冲洗可包含切断反应气体的流动同时使惰性载气继续流动到反应空间。在另一实施例中，冲洗步骤可采用真空步骤以从表面去除过量反应物。
能够用以生长薄膜的反应器可用于本文中所描述的沉积。此类反应器包括装备有用于以“脉冲化”方式提供前体的合适设备和构件的ALD反应器以及CVD反应器。根据某些实施例，可使用喷头反应器。
可使用的适合反应器的实例包括市售设备以及自制反应器，并且将为CVD和/或ALD领域的技术人员所知。
本发明可通过其某些实施例的以下实例进一步说明，但除非另外具体指示，否则应理解这些实例仅出于说明的目的包括在内并且不打算限制本发明的范围。
实验部分
实例1
在此实例中，将SiN相对于衬底的第三不同表面选择性沉积于衬底的第一表面和第二表面上。在此实例中，衬底的第一表面包含通过ALD沉积的Al2O3并且衬底的第二表面包含经ALD沉积的ZrO2，并且第三不同表面包含天然氧化硅(在环境条件下生长于经抛光单晶硅表面上)。
通过ALD工艺使用四碘化硅(SiI4)作为第一前体并且使用NH3作为第二前体选择性沉积SiN膜。SiI4容纳于ProE-Vap安瓿中并且加热到100℃。N2载气在固体SiI4的表面上方流动，将SiI4蒸气带入具有衬底的加热腔室中。在200℃的温度和1.5托的反应室压力下对衬底进行各沉积循环。各沉积循环包括10秒SiI4蒸气脉冲、10秒惰性N2净化、10秒NH3脉冲和10秒惰性N2净化。参考图1，对于由100个沉积循环组成的ALD工艺，在以沉积于高k膜上时，沉积于Al2O3和ZrO2(两者均通过ALD沉积)上的SiN相对于天然氧化硅的选择性比率为90％。
实例2
在此实例中，将SiN相对于衬底的第二和第三不同表面选择性沉积于衬底的第一表面上。所述衬底的所述第一表面包含天然氧化硅。衬底的第二表面包含通过ALD沉积的Al2O3。第三表面包含通过ALD沉积的ZrO2。在SiN沉积之前，使衬底经受NH3等离子体处理工艺。
使用与实例1中所描述的相同工艺，通过ALD工艺使用四碘化硅(SiI4)作为第一前体并且使用NH3作为第二前体选择性沉积SiN膜。使用由100到200个沉积循环组成的ALD工艺沉积样品。如图2中所说明，测量沉积于第一经等离子体处理的天然氧化硅表面上的材料的厚度并且将其与沉积于第二和第三经等离子体处理的Al2O3和ZrO2表面上的材料的厚度进行比较。图2展示SiN于包含经等离子体处理的天然氧化硅的第一表面上的沉积相对于经等离子体处理的Al2O3和ZrO2表面具有极高选择性。(选择性超过95％)。

Claims (10)

1.一种在具有多个不同组成的表面的微电子装置衬底上选择性沉积氮化硅的方法，所述方法包含在原子层沉积条件下、在150℃到400℃的温度下并且在低于15托的压力下，使所述衬底与依序经脉冲化的四碘化硅或六碘化二硅和含氮共反应物接触，其中所述方法进一步包含用氨等离子体预处理所述衬底的步骤。
2.根据权利要求1所述的方法，其中所述温度为175℃到350℃。
3.根据权利要求1所述的方法，其中所述温度为200℃到250℃。
4.根据权利要求1所述的方法，其中待沉积的所述表面选自二氧化硅、二氧化锗、SiCO和低k衬底。
5.根据权利要求1所述的方法，其中所述温度为200℃到250℃，并且待沉积的所述表面不同于二氧化硅。
6.根据权利要求1所述的方法，其中所述装置衬底包含选自氮化硅、氮化钛、氮化钽和氮化铝、氧化铪、氧化锆、氧化铝以及其组合的一些表面，所述表面相比于同一衬底上选自具有抑制的氮化硅沉积的二氧化硅、二氧化锗、SiCO和低k衬底的其它表面具有增强的氮化硅沉积。
7.根据权利要求1所述的方法，其中所述装置衬底由至少一个二氧化硅表面和至少一个氧化铝表面构成，由此将所述氮化硅选择性沉积于所述至少一个氧化铝表面上。
8.根据权利要求1所述的方法，其中所述装置衬底由至少一个二氧化硅表面和至少一个二氧化锆表面构成，由此将所述氮化硅选择性沉积于所述至少一个二氧化锆表面上。
9.根据权利要求1所述的方法，其中所述含氮共反应物选自氨、二甲基肼、叔丁基肼、甲基肼或其混合物。
10.根据权利要求1所述的方法，其中将Si源在ProE-Vap中加热以用于汽化。
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