CN112038322A - 薄膜覆晶封装结构以及薄膜覆晶封装方法 - Google Patents
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Abstract
本发明提供一种薄膜覆晶封装结构以及薄膜覆晶封装方法。所述薄膜覆晶封装结构包括柔性基板以及芯片。所述柔性基板包括开设于所述柔性基板的第一表面的第一凹槽、设置于所述第一凹槽中的凸起、以及设置于所述第一凹槽的基板绑定垫。所述芯片包括开设于所述芯片的第二表面的第二凹槽、以及设置于所述第二表面与所述基板绑定垫相对应的芯片绑定垫。所述柔性基板的所述第一凹槽与所述芯片的周缘形状相配合,所述第二凹槽与所述第一凹槽的所述凸起相配合,使得所述芯片嵌合于所述柔性基板。所述芯片绑定垫与所述基板绑定垫电性连接。
Description
技术领域
本申请涉及芯片绑定技术领域,特别是涉及一种薄膜覆晶封装结构以及薄膜覆晶封装方法。
背景技术
在传统的显示屏中,其芯片(chip)是通过玻璃覆晶(chip on glass,COG)封装绑定在显示屏边框的玻璃基板上。这种方法可以有效缩小显示屏的驱动模块的体积,进而提供使用这种显示屏的电子装置的内部有更大的空间容纳其他电子零件。
随着显示技术的发展以及消费者的使用需求,具有窄边框的显示屏的需求越来越大,新的技术应运而生。薄膜覆晶(chip on film,COF)封装在窄边框显示屏中扮演重要的角色。薄膜覆晶封装是将显示屏的芯片绑定在显示屏的柔性基板上,这既拥有玻璃覆晶封装的优点,也能更进一步的缩小显示屏的边框宽度。
然而,这种设计会增加柔性基板与芯片的整体厚度,不利于电子装置的内部空间配置。同时,在柔性基板上绑定刚性的芯片的作法,将会产生芯片侧边受水汽干扰、芯片位移的风险。
因此需要一种改良薄膜覆晶封装的结构以及方法,来减低传统的薄膜覆晶封装结构的整体厚度、提升芯片与柔性基板绑定的密封性、以及加强芯片与柔性基板绑定的稳固性。
发明内容
为解决上述问题,本发明提供一种薄膜覆晶封装结构。所述薄膜覆晶封装结构包括:柔性基板,包括开设于所述柔性基板的第一表面的第一凹槽、设置于所述第一凹槽中的凸起、以及设置于所述第一凹槽的基板绑定垫;以及芯片,包括开设于所述芯片的第二表面的第二凹槽、以及设置于所述第二表面与所述基板绑定垫相对应的芯片绑定垫。所述柔性基板的所述第一凹槽与所述芯片的周缘形状相配合,所述第二凹槽与所述第一凹槽的所述凸起相配合,使得所述芯片嵌合于所述柔性基板。所述芯片绑定垫与所述基板绑定垫电性连接。
在本发明所述的薄膜覆晶封装结构中,所述第一凹槽的所述凸起为柱状或长条堤形。
在本发明所述的薄膜覆晶封装结构中,所述第一凹槽的所述凸起设置于所述第一凹槽中的角落或边缘。
在本发明所述的薄膜覆晶封装结构中,所述第一凹槽的深度在10微米至100微米之间。
在本发明所述的薄膜覆晶封装结构中,所述芯片与所述柔性基板的所述第一凹槽之间的间隙在10微米至30微米之间。
在本发明所述的薄膜覆晶封装结构中,所述芯片与所述柔性基板的所述第一凹槽之间的间隙填充有密封胶。
在本发明所述的薄膜覆晶封装结构中,所述芯片绑定垫与所述基板绑定垫通过异方性导电膜电性连接。
本发明还提供一种薄膜覆晶封装方法。所述薄膜覆晶封装方法包括以下步骤:
步骤S10:提供柔性基板以及芯片;
步骤S20:在所述柔性基板的第一表面形成第一凹槽,其中,所述第一凹槽与所述芯片的周缘形状相配合,以及所述第一凹槽中设有凸起;
步骤S30:在所述柔性基板的所述第一凹槽中设置基板绑定垫;
步骤S40:在所述芯片的第二表面形成与所述第一凹槽的所述凸起相配合的第二凹槽;
步骤S50:在所述芯片的所述第二表面设置与所述基板绑定垫相对应的芯片绑定垫;以及
步骤S60:将所述芯片嵌合于所述柔性基板,并且电性连接所述芯片绑定垫以及所述基板绑定垫。
在本发明所述的薄膜覆晶封装方法中,所述第一凹槽的所述凸起形成为柱状或长条堤形。
在本发明所述的薄膜覆晶封装方法中,还包括以下步骤:
步骤S50:在所述芯片与所述柔性基板的所述第一凹槽之间的间隙填充密封胶。
本发明所提供的所述薄膜覆晶封装结构以及所述薄膜覆晶封装方法能够减低传统的薄膜覆晶封装结构的整体厚度、提升所述芯片与所述柔性基板绑定的密封性、以及加强所述芯片与所述柔性基板绑定的稳固性。
附图说明
图1为本发明的柔性基板的结构示意图。
图2为本发明的芯片的结构示意图。
图3为图1中的A-A剖面放大图。
图4为图2中的B-B剖面放大图。
图5为本发明的薄膜覆晶封装结构的示意图。
具体实施方式
藉由以下具体实施例之详述,更加清楚描述本发明之特征与精神,而并非以所揭露的具体实施例来对本发明之范畴加以限制。相反地,其目的是希望能涵盖各种改变及具相等性的安排于本发明所欲申请之权利要求的范畴内。
在传统薄膜覆晶(chip on film,COF)封装中,显示面板与电子装置主板之间通常采用柔性基板进行连接,并且直接在所述柔性基板上绑定(bonding)芯片。本发明针对传统的薄膜覆晶封装结构的缺点做出改良。
请参照图1以及图2。图1为本发明的柔性基板100的结构示意图。图2为本发明的芯片200的结构示意图。所述柔性基板100的一个主要表面为第一表面110。所述芯片200的一个主要表面为第二表面210。
首先,通过光刻工艺蚀刻所述柔性基板100的所述第一表面110,形成一个与所述芯片200周缘形状相配合的第一凹槽120。在蚀刻所述柔性基板100的制程中,通过掩膜板的设计便可以调整所述第一凹槽120形成的形状;通过蚀刻的时间或工序便可以调整所述第一凹槽120形成的深度D。
本发明在所述第一凹槽120中设计凸起121。在本实施例中,如图1所示,以设置于所述第一凹槽120中的四个角落的四个柱状所述凸起121作为范例说明。所述凸起121的造型不限为柱状,也可以为长条堤形;并且不限制为偶数数量、或是对称设置于所述第一凹槽120的角落或边缘;也即,实际实施不以本发明实施例为限。在蚀刻所述柔性基板100的制程中,依据需求设计所述掩膜板,四个所述凸起121为所述柔性基板100不被蚀刻的区域。相对应地,本发明在所述芯片200的所述第二表面210上也通过光刻工艺蚀刻出与所述柔性基板100的所述凸起121相配合的第二凹槽221。
由于所述柔性基板100的所述第一凹槽120与所述芯片200周缘形状相配合、所述芯片200的所述第二凹槽221与所述柔性基板100的所述凸起121相配合,因此,所述芯片200得以嵌合于所述柔性基板100。
接着,为了达成所述芯片200与所述柔性基板100的绑定,所述柔性基板100的所述第一凹槽120还设置有基板绑定垫122,以及所述芯片200的所述第二表面210也设置有与所述基板绑定垫122相对应的芯片绑定垫222。所述基板绑定垫122作为所述柔性基板100中的电路引脚,用以电性连接所述芯片200的所述芯片绑定垫222。
请参照图3,其为图1的所述柔性基板100的A-A剖面放大图。在本发明中,所述柔性基板100被蚀刻出的所述第一凹槽120的所述深度D范围为10微米(μm)至100微米(μm)。经过发明人的计算与实验,在这个范围区间的所述深度D既可达到减薄所述柔性基板100的效果,又不影响所述柔性基板100的材料强度。
请参照图4,其为图2中所述芯片200的B-B剖面放大图。需要说明的是,由于所述第二凹槽221是针对所述芯片200的本体进行除料,所述第二凹槽221的设置必须依据所述芯片200内部的集成电路(图中未示)设计调整,以免影响所述芯片200的正常运作。
请参照图5,其为本发明的薄膜覆晶封装结构的示意图。当所述芯片200绑定到所述柔性基板100的所述第一凹槽120时,所述第一凹槽120的所述凸起121能起到所述芯片200的定位以及限位用途,也即,所述芯片200的所述第二凹槽221将对应地嵌入所述第一凹槽120的所述凸起121。
所述芯片200的所述芯片绑定垫222与所述柔性基板100的所述基板绑定垫122之间还贴附有异方性导电膜(anisotropic conductive film,ACF)300。通过所述异方性导电膜300,有效地绑定所述柔性基板100与所述芯片200。
另外,所述柔性基板100的所述第一凹槽120与所述芯片200的所述周缘形状相配合,两者为间隙配合。本发明将所述第一凹槽120的周缘形状设计为约略大于所述芯片200的所述周缘形状,两者之间具有间隙G。所述间隙G范围为10微米(μm)至30微米(μm)。经过发明人的计算与实验,在这个范围区间的所述间隙G既可达到所述柔性基板100可弯折的特点,又不影响所述柔性基板100与所述芯片200绑定的偏移或错位。
在所述柔性基板100与所述芯片200绑定后,所述芯片200与所述柔性基板100的所述第一凹槽120之间的所述间隙G填充密封胶400,以保护绑定的密封性。
相较于所述传统薄膜覆晶封装结构,本发明提供的所述薄膜覆晶封装结构以及薄膜覆晶封装方法能够将所述薄膜覆晶封装结构的整体厚度T大大减薄约10微米(μm)至100微米(μm)。并且通过所述柔性基板100的所述第一凹槽120的所述凸起121与所述芯片200的所述第二凹槽221的配合,能够加强所述芯片200与所述柔性基板100绑定的稳固性。同时,所述芯片200与所述柔性基板100的所述第一凹槽120之间的所述间隙G填充有所述密封胶400,能够提升所述芯片200与所述柔性基板100绑定的密封性。
虽然本发明已用优选实施例揭露如上,然其并非用以限定本发明,本发明所属技术领域中具有通常知识者,在不脱离本发明之精神和范围内,当可作各种之更动与润饰,因此本发明之保护范围当视权利要求书所界定范围为准。
Claims (10)
1.一种薄膜覆晶封装结构,其特征在于,包括:
柔性基板,包括开设于所述柔性基板的第一表面的第一凹槽、设置于所述第一凹槽中的凸起、以及设置于所述第一凹槽的基板绑定垫;以及
芯片,包括开设于所述芯片的第二表面的第二凹槽、以及设置于所述第二表面与所述基板绑定垫相对应的芯片绑定垫;
其中,所述柔性基板的所述第一凹槽与所述芯片的周缘形状相配合,所述第二凹槽与所述第一凹槽的所述凸起相配合,使得所述芯片嵌合于所述柔性基板;以及
所述芯片绑定垫与所述基板绑定垫电性连接。
2.如权利要求1所述的薄膜覆晶封装结构,其特征在于,所述第一凹槽的所述凸起为柱状或长条堤形。
3.如权利要求1所述的薄膜覆晶封装结构,其特征在于,所述第一凹槽的所述凸起设置于所述第一凹槽中的角落或边缘。
4.如权利要求1所述的薄膜覆晶封装结构,其特征在于,所述第一凹槽的深度在10微米至100微米之间。
5.如权利要求1所述的薄膜覆晶封装结构,其特征在于,所述芯片与所述柔性基板的所述第一凹槽之间的间隙在10微米至30微米之间。
6.如权利要求1所述的薄膜覆晶封装结构,其特征在于,所述芯片与所述柔性基板的所述第一凹槽之间的间隙填充有密封胶。
7.如权利要求1所述的薄膜覆晶封装结构,其特征在于,所述芯片绑定垫与所述基板绑定垫通过异方性导电膜电性连接。
8.一种薄膜覆晶封装方法,其特征在于,包括以下步骤:
步骤S10:提供柔性基板以及芯片;
步骤S20:在所述柔性基板的第一表面形成第一凹槽,其中,所述第一凹槽与所述芯片的周缘形状相配合,以及所述第一凹槽中设有凸起;
步骤S30:在所述柔性基板的所述第一凹槽中设置基板绑定垫;
步骤S40:在所述芯片的第二表面形成与所述第一凹槽的所述凸起相配合的第二凹槽;
步骤S50:在所述芯片的所述第二表面设置与所述基板绑定垫相对应的芯片绑定垫;以及
步骤S60:将所述芯片嵌合于所述柔性基板,并且电性连接所述芯片绑定垫以及所述基板绑定垫。
9.如权利要求8所述的薄膜覆晶封装方法,其特征在于,所述第一凹槽的所述凸起形成为柱状或长条堤形。
10.如权利要求8所述的薄膜覆晶封装方法,其特征在于,还包括以下步骤:
步骤S70:在所述芯片与所述柔性基板的所述第一凹槽之间的间隙填充密封胶。
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