US20140264860A1 - Rectifier diode - Google Patents
Rectifier diode Download PDFInfo
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- US20140264860A1 US20140264860A1 US13/796,489 US201313796489A US2014264860A1 US 20140264860 A1 US20140264860 A1 US 20140264860A1 US 201313796489 A US201313796489 A US 201313796489A US 2014264860 A1 US2014264860 A1 US 2014264860A1
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- chip diode
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- 239000010410 layer Substances 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 46
- 238000004519 manufacturing process Methods 0.000 claims description 36
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- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 claims description 2
- PQUCIEFHOVEZAU-UHFFFAOYSA-N Diammonium sulfite Chemical compound [NH4+].[NH4+].[O-]S([O-])=O PQUCIEFHOVEZAU-UHFFFAOYSA-N 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 claims description 2
- 239000003365 glass fiber Substances 0.000 claims description 2
- 239000005011 phenolic resin Substances 0.000 claims description 2
- 229920001568 phenolic resin Polymers 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 238000007747 plating Methods 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
A rectifier diode includes a substrate defining an even number of through holes, one or a number of bare chip diodes placed on the top surface of the substrate with even number of conducting grooves thereof respectively kept in alignment with respective through holes of the substrate, and a conducting unit including a metal interface layer coated on exposed surfaces of each bare chip diode and the substrate using, a conductive metal thin film covered over the metal interface layer and defining an electroplating space within each through hole of the substrate and the corresponding conducting groove of one bare chip diode and a conducting medium coated in each electroplating space to form an electrode pin and a bond pad.
Description
- 1. Field of the Invention
- The present invention relates to rectifier diode technology and more particularly, to such a rectifier diode, which has one or multiple bare chip diodes be directly placed on a substrate and uses a metal interface layer and a conductive metal thin film and predetermined electrode pins and bond pads to secure the bare chip diodes and the substrate tightly together and to electrically couple the bare chip diodes to the circuit in the substrate, eliminating a further packaging process, simplifying the manufacturing process and reducing the manufacturing cost.
- 2. Description of the Related Art
- With fast development of electronic technology, rectifier diodes are used intensively in different electronic devices to rectify electric current. Taiwan Patent No. 101281, Publication No. 3421841, filed on Sep. 30, 1997, discloses a semiconductor diode device and its fabrication method. According to this design, as shown in
FIG. 12 , one respective ends of the positive and negative poles of an bare chip diode A2 are bonded to a circuit unit A1 of a substrate A, an adhesive A3 is covered on the substrate A over the bare chip diode A2 and precisely ground to let the other ends of the positive and negative poles of the bare chip diode A2 be exposed to the outside, and then a conducting circuit A4 is formed on the exposed ends of the positive and negative poles of the bare chip diode A2 by printing or vacuum deposition to electrically coupled to the bare chip diode A2 to the circuit in the substrate A, and then a protective cover layer A5 is molded on the substrate A. This method needs to perform adhesive bonding, grinding and wire bonding and encapsulating procedures, complicating the fabrication. Further, the performance of the grinding step tends to result in a precision error, leading to a defective product. Further, the wiring bonding and encapsulating procedures need to use different processing tools, increasing the equipment installation cost and the product fabrication cost. - Further, flip chip rectifier diodes are most popularly used in electronic products at the present time. After fabrication of bare chip diodes, they must be packaged by IC packaging companies. As shown in
FIG. 13 , bumps B1 are provided at the bottom side of the bare chip diode B, and then tin solder B2 is bonded between the bumps B1 and a carrier plate B3 to electrically couple the bare chip diode B to the circuit at the carrier plate B3. Further, an encapsulation or underfill process is then performed to finish the fabrication. This method has the drawback of high cost. Further, during operation of the bare chip diode, waste heat can be transferred through the bumps B1 and the tin solder B2 to the carrier plate B3 for dissipation. However, due to limited heat transfer area, waste heat cannot be quickly transferred to the carrier plate B3 for dissipation. Further, the presence of the bumps B1 and the tin solder B2 greatly increase the height of the finished product, not suitable for low profile application. - In the aforesaid flip chip rectifier diode structure and its fabrication method, bumps B1 or tin coating must be made prior to the process of bonding the bumps B1 or the bare chip diode B to the carrier plate B3. If gold is used to make the bumps B1, the cost will be very high. If silver or tin is used to reduce the cost, the product reliability will be relatively lowered. In order to improve heat transfer problem, an underfill process is necessary to fill a conducting adhesive between the bare chip diode B and the carrier plate B3. However, this added underfill process complicates the manufacturing process, extends the manufacturing time, and increases the manufacturing cost.
- Therefore, it is desirable to provide a rectifier diode that eliminates the problems of the aforesaid prior art designs.
- The present invention has been accomplished under the circumstances in view. It is therefore the main object of the present invention to provide a rectifier diode, which eliminates a packaging process, simplifying the manufacturing process and reducing the manufacturing cost.
- To achieve this and other objects of the present invention, a rectifier diode comprises a substrate defining at least one pair of through holes, at least one bare chip diode positioned on the substrate to keep conducting grooves thereof in alignment with respective through holes of the substrate, and a conducting unit formed to secure the bare chip diode and the substrate tightly together and to electrically coupled the circuit of the substrate to the at least one bare chip diode. Thus, the bare chip diode(s) can be directly installed in the substrate and electrically coupled to the circuit of the substrate without any extra packaging process, such as bump bonding process, encapsulation process and/or underfill process, simplifying the manufacturing process and reducing the manufacturing cost.
- In one embodiment of the present invention, the conducting unit comprises a metal interface layer, a conductive metal thin film and predetermined electrode pins and bond pads. After positioning of the bare chip diode(s) on the substrate and formation of the conducting unit to electrically couple the bare chip diode(s) to the circuit of the substrate. Thus, waste heat produced during operation of the bare chip diode can be transferred through the electrode pins to the substrate rapidly, enhancing quick heat dissipation.
- Further, because bare chip diode(s) can be directly installed in the substrate and electrically coupled to the circuit of the substrate without bump bonding, encapsulation process or underfill, the invention matches height saving and is suitable for low profile electronic products.
- Further, the substrate can be configured to provide four pairs of through holes for the mounting of four bare chip diodes in such a manner that these adjacent bare chip diodes have an inverse polarity to each other, and a metal interface layer, a conductive metal thin film and desired electrode pins and bond pads can then be processed to make a bridge rectifier.
- Further, during fabrication of the rectifier diode, the invention uses at least one conducting medium to fill up each electroplating space and to form an electrode pin on the conductive metal thin film in each electroplating space and a bond pad at the bottom side of each electrode pin, reducing the rectifier diode manufacturing cost and enhancing the conducting effects of the rectifier diode.
- In an alternate form of the present invention, a copper coating layer is covered on the conductive metal thin film in each electroplating space and each extension space, and then a conductive adhesive layer is bonded to the copper coating layer in each electroplating space, and then a surface copper layer is plated on the copper coating layer and the conductive adhesive layer. Thus, using the copper coating layer, the conductive adhesive layer and the surface copper layer to form the desired electrode pins and bond pads greatly saves the cost. Further, the conductive adhesive layer between the copper coating layer and the surface copper layer is electrically conductive and can fill up open spaces to prevent bubble formation, maintaining high levels of electrical conductivity and reducing manufacturing cost.
-
FIG. 1 is a sectional side view of a substrate for rectifier diode in accordance with the present invention. -
FIG. 2 corresponds toFIG. 1 , illustrating an bare chip diode placed on the substrate. -
FIG. 3 corresponds toFIG. 2 , illustrating a metal interface layer coated on the exposed surfaces of the bare chip diode and the substrate. -
FIG. 4 corresponds toFIG. 3 , illustrating a conductive metal thin film coated on the metal interface layer. -
FIG. 5 corresponds toFIG. 4 , illustrating an insulating layer formed in a predetermined pattern and covered on the external surface of the conductive metal thin film. -
FIG. 6 corresponds toFIG. 5 , illustrating a copper coating layer coated on the exposed surface of the conductive metal thin film. -
FIG. 7 corresponds toFIG. 6 , illustrating the insulating layer, the conductive metal thin film and the metal interface layer removed from the substrate and the bare chip diode. -
FIG. 8 is a top plain view of an alternate form of the rectifier diode in accordance with the present invention, illustrating four bare chip diodes on the top surface of the substrate. -
FIG. 9 is a sectional side view of the alternate form of the rectifier diode in accordance with the present invention. -
FIG. 10 is a schematic drawing illustrating the fabrication flow of the alternate form of the rectifier diode in accordance with the present invention (I). -
FIG. 11 is a schematic drawing illustrating the fabrication flow of the alternate form of the rectifier diode in accordance with the present invention (II). -
FIG. 12 is a perspective view of a rectifier diode according to the prior art. -
FIG. 13 is a sectional side view of another structure of rectifier diode according to the prior art. - Referring to
FIGS. 1-7 , a rectifier diode in accordance with the present invention is shown comprising asubstrate 1, anbare chip diode 2, and a conductingunit 3. - The
substrate 1 can be made out of ceramics, glass fibers, polyimide ammonium sulfite or phenolic resin, having at least one pair of throughholes 11 extending through opposite top and bottom surfaces thereof. These throughholes 11 can be made using laser drilling, machining or ceramic green sheet punching technique. - The
bare chip diode 2 is arranged on the top surface of thesubstrate 1, defining a pair of conductinggrooves 21 in the bottom side thereof in communication with the respective throughholes 11 of thesubstrate 1. In this embodiment, the number of the throughholes 11 of thesubstrate 1 is 2; thebare chip diode 2 comprises two conductinggrooves 21 located in the bottom side thereof and respectively kept in communication with the two throughholes 11 of thesubstrate 1. Further, thebare chip diode 2 is temporarily positioned on the top surface of thesubstrate 1 using a tool or non-conductive adhesive. - The conducting
unit 3 comprises ametal interface layer 31 selected from the group of titanium, tungsten, nickel, chrome and their alloys and coated on the exposed surfaces of thebare chip diode 2 and thesubstrate 1 using a vacuum coating technique, a conductive metalthin film 32 covered over themetal interface layer 31 using vacuum copper deposition, chemical nickel plating or chemical copper plating technique and defining anelectroplating space 321 within each throughhole 11 of thesubstrate 1 and thecorresponding conducting groove 21 of thebare chip diode 2, aninsulating layer 33 of dry film or liquid photoresist formed in a predetermined pattern and covered on the external surface of the conductive metalthin film 32 using an exposure and development technique or printing technique and defining at least one pair, for example, twoextension spaces 331 at the bottom side of thesubstrate 1 opposite to thebare chip diode 2 and beyond the insulatinglayer 33 corresponding to the respectiveelectroplating spaces 321, at least one conductingmedium 342 used to make a copper coating layer on the exposed surface of the conductive metalthin film 32 and to form anelectrode pin 34 in eachelectroplating space 321 and abond pad 341 in eachextension space 331 in integration with onerespective electrode pin 34. Thereafter, theinsulating layer 33 is removed, and then an etching solution is applied to remove the conductive metalthin film 32 and themetal interface layer 31 from thesubstrate 1 and thebare chip diode 2, finishing the fabrication of the rectifier diode. - Referring to
FIGS. 5-7 again, in one preferred embodiment of the present invention where the pins of the bare chip diode are horizontally extended out at opposing left and right sides. In this embodiment, thebare chip diode 2 defines two conductinggrooves 21 in the bottom side thereof. These two conductinggrooves 21 arebump grooves 211 of thebare chip diode 2 originally made in bare chip diode factory for the mounting of respective bumps. Thebare chip diode 2 is arranged on the top surface of thesubstrate 1, keeping the two conductinggrooves 21 in alignment with the respective throughholes 11 of thesubstrate 1. The inner surface of each conductinggroove 21 of thebare chip diode 2, the inner surface of each throughhole 11 of thesubstrate 1 and a part of the bottom surface of thesubstrate 1 around each throughhole 11 are covered by themetal interface layer 31 and the conductive metalthin film 32. Further, at least one conductingmedium 342 is used to fill up eachelectroplating space 321, forming anelectrode pin 34 on the conductive metalthin film 32 in eachelectroplating space 321 and abond pad 341 at the bottom side of eachelectrode pin 34 over the surface area around each throughhole 11. - At this time, the
metal interface layer 31, the conductive metalthin film 32, the electrode pins 34 and thebond pads 341 secure thebare chip diode 2 and thesubstrate 1 tightly together. Further, a predetermined circuit can be formed in thesubstrate 1 before or after installation of thebare chip diode 2, and then electrically coupled with thebare chip diode 2 after installation of thebare chip diode 2. Thus, after fabrication of thebare chip diode 2, it can be directly installed in thesubstrate 1 and electrically coupled to the circuit of thesubstrate 1 without any extra packaging process, such as bump bonding process, encapsulation process and/or underfill process, simplifying the manufacturing process and reducing the manufacturing cost. - Referring to
FIG. 8 andFIG. 7 again, in another preferred embodiment of the present invention, thesubstrate 1 defines four pairs of throughholes 11; fourbare chip diodes 2 are arranged on the top surface of thesubstrate 1 in such a manner that these adjacentbare chip diodes 2 have an inverse polarity to each other, and each conductinggroove 21 of eachbare chip diode 2 is kept in communication with one respective throughhole 11 of thesubstrate 1. Themetal interface layer 31, the conductive metalthin film 32, the electrode pins 34 and thebond pads 341 are then formed using the same processing process. Thus, fourbare chip diodes 2 can be installed in thesubstrate 1 and electrically coupled to the circuit of thesubstrate 1 in such a manner that the electrode pins 34 of each two adjacentbare chip diodes 2 of the same polarity are electrically connected together, and theother electrode pin 34 of eachbare chip diode 2 is electrically coupled to the circuit of thesubstrate 1, forming a bridge rectifier. - The aforesaid laser drilling, machining, ceramic green sheet punching, vacuum copper deposition, chemical nickel plating, chemical copper plating, exposure and development technique or printing technique for pattern formation of insulating layer of dry film or liquid photoresist, etching technique for removal of conductive metal thin film and metal interface layer, all these techniques are of the known art and not within the scope of the invention. No further detailed description in this regard will be necessary.
- Referring to
FIG. 9 andFIG. 7 again, using at least one conductingmedium 342 to fill up eachelectroplating space 321 and to form anelectrode pin 34 on the conductive metalthin film 32 in eachelectroplating space 321 and abond pad 341 at the bottom side of eachelectrode pin 34 can be done by: employing an electroplating technique to make acopper coating layer 3421 that fills up eachelectroplating space 321 and eachextension space 331 to form the desired electrode pins 34 andbond pads 341. Using an electroplating technique to fill up eachelectroplating space 321 and eachextension space 331 with pure copper is quite expensive. In order to reduce the cost, acopper coating layer 3421 can be covered on the conductive metalthin film 32 in eachelectroplating space 321 and eachextension space 331, and then aconductive adhesive layer 3422 is bonded to thecopper coating layer 3421 in eachelectroplating space 321, and then asurface copper layer 3423 is plated on thecopper coating layer 3421 and theconductive adhesive layer 3422. Thus, using thecopper coating layer 3421, theconductive adhesive layer 3422 and thesurface copper layer 3423 to form the desired electrode pins 34 andbond pads 341 greatly saves the cost. - Because the material cost of the
conductive adhesive layer 3422 is much cheaper than the material cost of thecopper coating layer 3421, the manufacturing cost of the rectifier diode can be significantly reduced. Further, because thesurface copper layer 3423 is formed on the surface of thecopper coating layer 3421 for conducting, the conductinggrooves 21 of thebare chip diode 2 can conduct electricity by means of thecopper coating layer 3421 and thecopper layer 3423. Further, theconductive adhesive layer 3422 between thecopper coating layer 3421 and thesurface copper layer 3423 is electrically conductive and can fill up open spaces to prevent bubble formation, maintaining high levels of electrical conductivity and reducing manufacturing cost. - Referring to
FIGS. 10 and 11 , in still another alternate form of the present invention where the pins of the bare chip diode extend in vertical direction. In this embodiment, thebare chip diode 2 defines two conductinggrooves 21 in the bottom side thereof and one conductinggroove 21 in the top side thereof, wherein the two conductinggrooves 21 in the bottom side are classified as onebump groove 211 and oneplating groove 212; the conductinggroove 21 in the top side is classified as abump groove 211. After positioning of thebare chip diode 2 on the top surface of thesubstrate 1 by using a tool or non-conductive adhesive, thebump groove 211 andplating groove 212 in the bottom side of thebare chip diode 2 are respectively kept in alignment with the respective throughholes 11 of thesubstrate 1, and thereafter, alead frame 213 is mounted at thebare chip diode 2 with abase portion 2131 thereof located at the top side and suspending above thebump groove 211 in the top side of thebare chip diode 2, amiddle part 2132 thereof downwardly extended from thebase portion 2131 along one vertical lateral side of thebare chip diode 2 and anend piece 2133 thereof perpendicularly extended from the bottom side of themiddle part 2132 to theplating groove 212. Thereafter, thelead frame 213 is fixed in position using a non-conductive adhesive, and then ametal interface layer 31 is coated on the exposed surfaces of thebare chip diode 2 and thesubstrate 1 using a vacuum coating technique, and then a conductive metalthin film 32 is covered over themetal interface layer 31 using vacuum copper deposition, chemical nickel plating or chemical copper plating technique to define anelectroplating space 321 in each throughhole 11 of thesubstrate 1 and each corresponding conductinggroove 21 of thebare chip diode 2, and then an insulatinglayer 33 is formed in a predetermined pattern and covered on the external surface of the conductive metalthin film 32 using an exposure and development technique or printing technique to define twoextension spaces 331 at the bottom side of thesubstrate 1 opposite to thebare chip diode 2 and beyond the insulatinglayer 33 corresponding to therespective electroplating spaces 321. Then a conductingmedium 342 is used to make a copper coating layer on the exposed surface of the conductive metalthin film 32, forming the electrode pins 34 andbond pads 341, and this procedure can be done by employing an electroplating technique to make acopper coating layer 3421 that fills up eachelectroplating space 321 and eachextension space 331 to form the desired electrode pins 34 andbond pads 341. Thereafter, the insulatinglayer 33 and the conductive metalthin film 32 are removed, finishing the fabrication of the rectifier diode. - According to this alternate embodiment, the
bare chip diode 2 defines onebump groove 211 and oneplating groove 212 in the bottom side thereof and onebump groove 211 in the top side thereof. Thebare chip diode 2 is placed on the top surface of thesubstrate 1 to keep the bottom-sided bump groove 211 andplating groove 212 thereof in alignment with the throughholes 11 of thesubstrate 1. The inner surfaces of thebump groove 211 andplating groove 212 in the bottom side of thebare chip diode 2, the inner surfaces of the throughholes 11 of thesubstrate 1 and a part of the bottom surface of the substrate around each throughhole 11, a part of the top surface of thebare chip diode 2 around thebump groove 211 in the top side of thebare chip diode 2, the outer surfaces of thebase portion 2131 andend piece 2133 of thebare chip diode 2 are covered by themetal interface layer 31 and the conductive metalthin film 32. After formation of the conductive metalthin film 32 on themetal interface layer 31, the conductive metalthin film 32 defines anelectroplating space 321 within each throughhole 11 of thesubstrate 1 and the corresponding conductinggroove 21 of thebare chip diode 2. A conductingmedium 342 is then used to make a copper coating layer on the exposed surface of the conductive metalthin film 32 and to form anelectrode pin 34 in eachelectroplating space 321 and abond pad 341 in integration with onerespective electrode pin 34. - In this alternate form, an even number of
bump grooves 211 are provided at opposing top and bottom sides of thebare chip diode 2 and at least oneplating groove 212 is provided at the bottom side of thebare chip diode 2 corresponding to the amount of thebump groove 211 at the top side of thebare chip diode 2. - At this time, the
metal interface layer 31, the conductive metalthin film 32, the electrode pins 34 and thebond pads 341 secure thebare chip diode 2 and thesubstrate 1 tightly together, thebump groove 211 at the top side of thebare chip diode 2 is electrically connected to theelectrode pin 34 in theplating groove 212 in the bottom side of thebare chip diode 2 by therespective electrode pin 34 and thelead frame 213, and the circuit in thesubstrate 1 is electrically coupled with thebare chip diode 2. - In actual application, the rectifier diode of the present invention has advantages and features as follows:
- 1. The
bare chip diode 2 is positioned on thesubstrate 1 to keep the conductinggrooves 21 thereof in alignment with the respective throughholes 11 of thesubstrate 1, and then ametal interface layer 31 and a conductive metalthin film 32 and the desired electrode pins 34 andbond pads 341 are formed to secure thebare chip diode 2 and thesubstrate 1 tightly together, and the circuit that is formed in thesubstrate 1 before or after installation of thebare chip diode 2 is electrically coupled with thebare chip diode 2. Thus, after fabrication of thebare chip diode 2, it can be directly installed in thesubstrate 1 and electrically coupled to the circuit of thesubstrate 1 without any extra packaging process, such as bump bonding process, encapsulation process and/or underfill process, simplifying the manufacturing process and reducing the manufacturing cost. - 2. The
bare chip diode 2 is mounted on thesubstrate 1 and electrically coupled to the circuit of thesubstrate 1 by themetal interface layer 31 and the conductive metalthin film 32 and the electrode pins 34, and therefore waste heat produced during operation of thebare chip diode 2 can be transferred through the electrode pins 34 to thesubstrate 1 rapidly, enhancing quick heat dissipation. - 3. After fabrication of the
bare chip diode 2, thebare chip diode 2 can be directly installed in thesubstrate 1 and electrically coupled to the circuit of thesubstrate 1 without bump bonding, encapsulation process or underfill process, matching height saving and suitable for low profile electronic products. - 4. The
substrate 1 can be configured to provide four pairs of throughholes 11 for the mounting of fourbare chip diodes 2 in such a manner that these adjacentbare chip diodes 2 have an inverse polarity to each other, and ametal interface layer 31, a conductive metalthin film 32 and desired electrode pins 34 andbond pads 341 can then be processed to make a bridge rectifier. - 5. Using at least one conducting
medium 342 to fill up eachelectroplating space 321 and to form anelectrode pin 34 on the conductive metalthin film 32 in eachelectroplating space 321 and abond pad 341 at the bottom side of eachelectrode pin 34 can be done by: employing an electroplating technique to make acopper coating layer 3421 that fills up eachelectroplating space 321 and eachextension space 331 to form the desired electrode pins 34 andbond pads 341. - 6. In order to reduce the cost, a
copper coating layer 3421 is covered on the conductive metalthin film 32 in eachelectroplating space 321 and eachextension space 331, and then aconductive adhesive layer 3422 is bonded to thecopper coating layer 3421 in eachelectroplating space 321, and then asurface copper layer 3423 is plated on thecopper coating layer 3421 and theconductive adhesive layer 3422. Thus, using thecopper coating layer 3421, theconductive adhesive layer 3422 and thesurface copper layer 3423 to form the desired electrode pins 34 andbond pads 341 greatly saves the cost. Further, theconductive adhesive layer 3422 between thecopper coating layer 3421 and thesurface copper layer 3423 is electrically conductive and can fill up open spaces to prevent bubble formation, maintaining high levels of electrical conductivity and reducing manufacturing cost. - In conclusion, the invention is characterized by: positioning an
bare chip diode 2 on asubstrate 1 to keep conductinggrooves 21 of thebare chip diode 2 in alignment with the respective throughholes 11 of thesubstrate 1, and then forming ametal interface layer 31 and a conductive metalthin film 32 and desired electrode pins 34 andbond pads 341 to secure thebare chip diode 2 and thesubstrate 1 tightly together, and then electrically coupling the circuit of thesubstrate 1 to thebare chip diode 2. Thus, after fabrication of thebare chip diode 2, thebare chip diode 2 can be directly installed in thesubstrate 1 and electrically coupled to the circuit of thesubstrate 1 without any extra packaging process, such as bump bonding process, encapsulation process and/or underfill process, simplifying the manufacturing process and reducing the manufacturing cost. - Although particular embodiments of the invention have been described in detail for purposes of illustration, various modifications and enhancements may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims.
Claims (7)
1. A rectifier diode, comprising:
a substrate comprising at least one pair of through holes cut through opposing top and bottom surfaces thereof;
at least one bare chip diode placed on the top surface of said substrate, each said bare chip diode comprising an even number of conducting grooves respectively kept in alignment with respective through holes of said substrate; and
a conducting unit comprising a metal interface layer coated on exposed surfaces of each said bare chip diode and said substrate, a conductive metal thin film covered over said metal interface layer and defining an electroplating space within each through hole of said substrate and the corresponding conducting groove of one said bare chip diode, and at least one conducting medium coated in each said electroplating space to form an electrode pin in each said electroplating space and a bond pad at the bottom surface of said substrate in integration with one respective said electrode pin.
2. The rectifier diode as claimed in claim 1 , wherein said substrate comprises one pair of through holes cut through the opposing top and bottom surfaces thereof; said bare chip diode comprises two conducting grooves that are bump grooves located at a bottom side thereof and originally made during fabrication of said bare chip diode respectively aimed at the two through holes of said substrate.
3. The rectifier diode as claimed in claim 1 , wherein said aid substrate comprises four pairs of through holes cut through the opposing top and bottom surfaces thereof; four said bare chip diodes are placed on the top surface of said substrate adjacent to one another in such a manner that these adjacent bare chip diodes have an inverse polarity to each other, and each conducting groove of each said bare chip diode is kept in communication with one respective through hole of said substrate.
4. The rectifier diode as claimed in claim 1 , wherein said conducting unit comprises one single conducting medium of copper coated in each said electroplating space to form an electrode pin in each said electroplating space and a bond pad at the bottom surface of said substrate in integration with one respective said electrode pin using an electroplating technique.
5. The rectifier diode as claimed in claim 1 , wherein said at least one conducting medium of said conducting unit comprises a conductive metal thin film electroplated in each said electroplating space and a part of the bottom surface of said substrate around each said electroplating space, a conductive adhesive layer bonded to said copper coating layer in each said electroplating space, and a surface copper layer plated on said copper coating layer and said conductive adhesive layer to form said electrode pins and said bond pads.
6. The rectifier diode as claimed in claim 1 , wherein said substrate is selected from the group of ceramics, glass fibers, polyimide ammonium sulfite and phenolic resin.
7. The rectifier diode as claimed in claim 1 , wherein said through holes of said substrate are made using one of laser drilling, machining and ceramic green sheet punching techniques.
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Cited By (5)
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CN105789069A (en) * | 2016-03-22 | 2016-07-20 | 上海集成电路研发中心有限公司 | Method for forming stacked silicon wafers by using pressure welding point mixed type bonding process |
US20180158695A1 (en) * | 2015-05-01 | 2018-06-07 | Sony Corporation | Manufacturing method and wiring substrate with through electrode |
US20180183480A1 (en) * | 2016-12-22 | 2018-06-28 | Jae Beom Kim | Non-conductive frame coated with conductive layer transmitting electromagnetic waves or having function of heat radiation |
WO2019210651A1 (en) * | 2018-05-03 | 2019-11-07 | 扬州虹扬科技发展有限公司 | Ultra-thin micro-bridge rectifier |
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Publication number | Priority date | Publication date | Assignee | Title |
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DE19549202B4 (en) * | 1995-12-30 | 2006-05-04 | Robert Bosch Gmbh | Rectifier diode |
KR100441260B1 (en) * | 2003-10-20 | 2004-07-21 | 주식회사 케이이씨 | Rectifier diode package |
US8159072B2 (en) * | 2007-12-12 | 2012-04-17 | Wen-Huo Huang | Rectification chip terminal structure |
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2013
- 2013-03-12 US US13/796,489 patent/US8847366B1/en not_active Expired - Fee Related
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US20180158695A1 (en) * | 2015-05-01 | 2018-06-07 | Sony Corporation | Manufacturing method and wiring substrate with through electrode |
US10256117B2 (en) * | 2015-05-01 | 2019-04-09 | Sony Corporation | Manufacturing method and wiring substrate with through electrode |
CN105789069A (en) * | 2016-03-22 | 2016-07-20 | 上海集成电路研发中心有限公司 | Method for forming stacked silicon wafers by using pressure welding point mixed type bonding process |
US20180183480A1 (en) * | 2016-12-22 | 2018-06-28 | Jae Beom Kim | Non-conductive frame coated with conductive layer transmitting electromagnetic waves or having function of heat radiation |
WO2019210651A1 (en) * | 2018-05-03 | 2019-11-07 | 扬州虹扬科技发展有限公司 | Ultra-thin micro-bridge rectifier |
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