CN111969059A - 一种屏蔽栅沟槽式金属氧化物半导体场效应管 - Google Patents

一种屏蔽栅沟槽式金属氧化物半导体场效应管 Download PDF

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CN111969059A
CN111969059A CN202010757457.2A CN202010757457A CN111969059A CN 111969059 A CN111969059 A CN 111969059A CN 202010757457 A CN202010757457 A CN 202010757457A CN 111969059 A CN111969059 A CN 111969059A
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epitaxial layer
trench
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CN111969059B (zh
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Nanjing Jiangzhi Technology Co ltd
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Abstract

本发明公开了一种改进的包含多个沟槽栅的沟槽式半导体功率器件，每个沟槽栅均包括一对分裂栅电极和一个屏蔽栅电极，在相邻沟槽栅之间形成一个氧化层电荷平衡区，并在沟槽底部形成结电荷平衡区。所述沟槽式半导体功率器件还进一步包括一个超级结结构，所述超级结结构包括多个位于衬底之上的、交替排列的P区和N区，在氧化层电荷平衡区下方形成一个结电荷平衡区，本发明的结构可以有效提高击穿电压、降低导通电阻。

Description

一种屏蔽栅沟槽式金属氧化物半导体场效应管
技术领域
本发明主要涉及半导体器件，更具体地，本发明涉及SGT MOSFET(屏蔽栅沟槽式金属氧化物半导体场效应晶体管)，其氧化层电荷平衡区位于相邻的沟槽栅之间，结电荷平衡区位于沟槽底部以维持一个稳定的高击穿电压和低导通电阻。
背景技术
与传统单栅沟槽式MOSFETs相比，如图1A所示的SGT MOSFETs具有更低的栅电荷和导通电阻，这归因于漂移区氧化层电荷平衡区、以及栅极下方厚氧化层的存在。然而，早期击穿总是发生在沟槽底部。因此，击穿电压的衰退成为设计和操作的限制因素。
为了改善早期击穿问题，美国专利号8,159,021公开了一种具有双外延层的SGTMOSFET，所述双外延层具有两种不同的电阻率，如图1B所示。第一外延层(N1外延层)的电阻率大于第二外延层(N2外延层)，且沟槽底部位于第一外延层，从而提高了击穿电压。但是，由于第一外延层的电阻率大于第二外延层，双外延层结构的导通电阻相对单外延层的更高。
因此，在半导体器件的设计和制造领域，特别是SGT MOSFET的设计和制造领域，仍需要提供一种新型的单元结构、器件结构和制造方法可以解决以上所涉及的困难和限制，使得SGT MOSFET具有更稳定的击穿电压。
发明内容
本发明公开了一种新型的SGT MOSFET，其氧化层电荷平衡区位于相邻的沟槽栅之间、结电荷平衡区位于沟槽底部，以确保整个漂移区被完全耗尽，且击穿发生在相邻的沟槽栅中间、沟槽底部不会发生早期击穿。此外，击穿电压对沟槽底部氧化层的厚度以及沟槽深度的敏感性明显减弱或不受其影响，雪崩能力也得到了增强。
根据本发明的一个方面，提供了一种包含SGT MOSFET的沟槽式半导体功率器件，所述SGT MOSFET形成在位于衬底之上的、具有第一导电类型的外延层之中，其特征在于，还包括：
(a)多个沟槽栅，其被具有所述第一导电类型的源区所包围，所述源区位于具有第二导电类型的体区中，并接近所述外延层的上表面，其中，每个所述的沟槽栅都包括一对分裂栅电极和一个屏蔽栅电极；
(b)氧化层电荷平衡区，形成于每两个相邻的沟槽栅之间；
(c)超级结结构，形成于所述衬底上方且位于所述氧化层电荷平衡区下方，包括多个交替形成的P区和N区；
(d)所述屏蔽栅电极位于沟槽栅下部，其与所述外延层之间通过第一栅绝缘层相互绝缘，所述一对分裂栅电极位于沟槽栅上部，且与所述外延层之间通过第二栅绝缘层相互绝缘，所述第二绝缘层的厚度小于所述第一绝缘层的厚度，且所述屏蔽栅电极和所述一对分裂栅电极之间相互绝缘，所述一对分裂栅电极之间由第三栅绝缘层相互绝缘；并且
(e)所述体区、所述屏蔽栅电极和所述源区通过多个沟槽式接触区短接至源极金属层。
根据本发明的另一个方面，在一些优选的实施例中，所述衬底为第一导电类型，所述外延层为具有均匀掺杂浓度的单外延层结构。在另一些优选的实施例中，所述衬底为第一导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，其中R1>R2。在另一些优选的实施例中，所述衬底为第一导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，其中R1<R2。在另一些优选的实施例中，所述衬底为第一导电类型，所述外延层为具有均匀掺杂浓度的单外延层结构，其电阻率为R，所述半导体功率器件还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R>Rn。在另一些优选的实施例中，所述衬底为第二导电类型，所述外延层为具有均匀掺杂浓度的单外延层结构，其电阻率为R，所述半导体功率器件还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R>Rn。在另一些优选的实施例中，所述衬底为第二导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，所述SGT MOSFET还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R1>R2>Rn。在另一些优选的实施例中，所述衬底为第二导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，所述半导体功率器件还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R2>R1>Rn。
根据本发明的另一个方面，在一些优选的实施例中，所述超级结结构的P区主要位于所述屏蔽栅电极的底部下方，并与所述外延层的底部表面相接触。在另一些优选的实施例中，所述超级结结构的P区主要位于所述屏蔽栅电极的底部下方，但并未接触到所述外延层的底部表面。
根据本发明的另一个方面，在一些优选的实施例中，所述衬底为所述第二导电类型，所述SGT MOSFET还包括：第一导电类型的缓冲层，位于所述衬底和所述外延层之间；多个第一导电类型的重掺杂区，位于所述衬底中，形成位于衬底中的包括多个交替形成的P+区和N+区的集成反向导通二极管。
根据本发明的另一个方面，在一些优选的实施例中，所述SGT MOSFET还包括第一导电类型的电荷存储区，其位于所述外延层中并位于所述体区下方，其中所述电荷存储区的多数载流子浓度大于所述外延层。
根据本发明的另一个方面，所述第一导电类型为N型，所述第二导电类型为P型，或所述第一导电类型为P型，所述第二导电类型为N型。
根据本发明的另一个方面，提供了一种SGT MOSFET的制造方法，其中所述超级结结构可通过多外延生长法形成，所述多外延生长法通过离子注入将P型杂质注入到各外延层的特定区域，并重复该步骤。
根据本发明的另一个方面，提供了一种SGT MOSFET的制造方法，其中所述超级结结构可通过外延层P型沟槽填充法形成。
根据本发明的另一个方面，提供了一种SGT MOSFET的制造方法，其中所述超级结结构可通过对沟槽栅的底部进行具有不同注入能量的硼离子注入形成。
本发明还公开了一种SGT MOSFET的制造方法，包括以下步骤：(a)在N1外延层中形成超级结结构，可通过外延层P型沟槽填充法或多外延生长法实现。其中，多外延生长法，通过离子注入将P型杂质注入到各外延层的特定区域，并重复该步骤；(b)在超级结结构上生长另一层具有第一导电类型的N2外延层，其中，所述N2外延层的掺杂浓度低于或高于所述N1外延层；(c)在外延层的上表面形成一层硬掩模，用于定义多个栅沟槽；(d)通过刻蚀硬掩模中的开放区域，在外延层中形成多个栅沟槽，以及两相邻栅沟槽之间的台面；(e)通过热氧化生长法或氧化层沉积法，在栅沟槽的内表面形成一层厚氧化层；(f)沉积第一掺杂多晶硅层以填充栅沟槽，用作屏蔽栅电极；(g)从外延层的上表面，回刻蚀屏蔽栅电极；(h)从所述外延层的上表面和栅沟槽的上部，回刻蚀所述厚氧化层；(i)形成一层第二栅绝缘层，其至少覆盖在每个所述栅沟槽较高部分的沟槽侧壁，且所述第二栅绝缘层的厚度薄于第一栅绝缘层；(j)形成一层第三栅绝缘层，在第二栅绝缘层热氧化期间，通过将第一栅绝缘层上方的屏蔽栅电极上部完全氧化形成；(k)沉积第二掺杂多晶硅层，填充所述栅沟槽的较高部分，用作分裂栅电极；(l)采用CMP法(化学机械抛光法)或等离子体刻蚀法，回刻蚀分裂栅电极；(m)实施具有第二导电类型掺杂物的体注入和体扩散步骤，以形成体区；(n)在外延层的上表面覆盖一个源掩膜；(o)实施具有第一导电类型掺杂物的源注入和源扩散步骤，以形成源区。
通过参考以下各个附图，阅读下文对优选实施例的详细描述，本发明的上述及其他目的和优点对于本领域的普通技术人员来说无疑是显而易见的。
附图说明
图1A示出了现有技术所揭示的一种SGT MOSFET的横截面图。
图1B示出了现有技术所揭示的另一种SGT MOSFET的剖面图。
图2A示出了根据本发明的一个优选实施例的剖面图。
图2B示出了根据本发明的另一个优选实施例的剖面图。
图3示出了根据本发明的另一个优选实施例的剖面图。
图4A示出了根据本发明的另一个优选实施例的剖面图。
图4B示出了根据本发明的另一个优选实施例的剖面图。
图5示出了根据本发明的另一个优选实施例的剖面图。
图6A示出了根据本发明的另一个优选实施例的剖面图。
图6B示出了根据本发明的另一个优选实施例的剖面图。
图7A示出了根据本发明的另一个优选实施例的剖面图。
图7B示出了根据本发明的另一个优选实施例的剖面图。
图8A示出了根据本发明的另一个优选实施例的剖面图。
图8B示出了根据本发明的另一个优选实施例的剖面图。
图9A-图9F示出了一系列剖面图，显示制造图4A中SGT MOSFET的工艺步骤。
具体实施方式
下面参照附图更详细地说明本发明，其中示出了本发明的优选实施例。本发明可以，但是以不同的方式体现，但是不应该局限于在此所述的实施例。例如，这里的说明更多地引用N沟道的半导体集成电路，但是很明显其他器件也是可能的。下文是通过参考各个附图来对实践本发明的优选实施例进行详细描述。一些方向术语，例如“顶部”、“底部”、“前”、“后”、“上方”、“下方”等，是参考各个附图的方向进行描述的。由于实施例中的元件可以被放置在许多不同的方向，因此，本发明中的方向术语只是用于描述而不能被视为对本发明的限制。应该理解的是，实施例中各种结构或者逻辑上的替代和修改都应该被涵盖在本发明的真正精神和范围内。因此，以下的详细描述不能被视为对本发明的限制，本发明的涵盖范围由附后的权利要求界定。应该理解的是，本发明中所描述的各个优选实施例的发明特征可以相互结合，有特别说明的除外。
图2A所示的是本发明的一个优选实施例。所述沟槽式半导体功率器件包括一个在N外延层202上形成的N沟道SGT MOSFET，所述外延层202位于N+衬底200之上，衬底200的背面形成有Ti/Ni/Ag漏极金属层201。所述SGT MOSFET还进一步包括多个沟槽栅204，所述沟槽栅204位于有源区内、从N外延层202的上表面向下延伸入N外延层202中，其中，所述沟槽栅204的沟槽底部位于N+衬底200和N外延层202的公共界面上方。所述每个沟槽栅204内，都包括位于沟槽较低部分的一个屏蔽栅电极(SG，如图所示)206，以及位于沟槽较高部分的一对分裂栅电极208，所述屏蔽栅电极206与相邻外延层202间通过第一栅绝缘层205实现彼此间的绝缘，所述的一对分裂栅电极208与相邻外延层202间通过第二栅绝缘层207实现彼此间的绝缘，其中第二栅绝缘层207的厚度薄于第一栅绝缘层205。同时，所述的一对分裂栅电极208在第一栅绝缘层205之上，且分裂栅电极之间通过第三栅绝缘层209实现彼此间的绝缘。在每两个相邻的沟槽栅204之间，形成一个具有n+源区211的p体区210，其从N外延层202的上表面附近延伸并围绕被衬以第二栅绝缘层207的分裂栅电极对208。此外，在p体区210内，形成p+体接触掺杂区214，其位于n+源区211的下方，并至少包围沟槽式源-体接触区213的底部，以减小沟槽式源-体接触区213中接触金属插塞和p体区210之间的接触电阻。根据本发明，氧化层电荷平衡区形成于相邻的沟槽栅204之间，在沟槽栅204的底部附近，引入P区215至N外延层202的较低部分形成超级结以作为结电荷平衡区，所述结电荷平衡区包括多个位于N+衬底200之上、氧化层电荷平衡区之下的、交替排列的P区215和N区202，以确保整个漂移区被完全耗尽，击穿发生在相邻的沟槽栅中间、而不会在沟槽底部发生早期击穿。同时，击穿电压对沟槽底部氧化层的厚度以及沟槽深度的敏感性明显减弱。根据本发明，超级结结构的P区215主要位于屏蔽栅电极206的底部下方，并与外延层202的底部表面216相接触。所述P区215可通过具有不同注入能量的硼离子注入形成，所述的硼离子注入通过对所述沟槽栅204的底部进行来实现。
图2B所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件与图2A所述的发明具有相似的结构，除了在本发明中，超级结结构位于N+衬底200’之上，超级结结构的P区215’主要位于屏蔽栅电极206’的底部下方，但并未接触到外延层的底部表面216’。
图3所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件与图2A所述的发明具有相似的结构，除了在本发明的结构中，还进一步包括一个电阻率为Rn的N缓冲层320，所述缓冲层320位于N+衬底300和N外延层302之间，所述外延层302为具有均匀掺杂浓度、且电阻率为R的单一外延层，其中R>Rn。
图4A所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件与图2A所述的发明具有相似的结构，除了在本发明中，外延层包括电阻率为R1的N1下外延层402和电阻率为R2的N2上外延层403，其中，R1、R2和Rn的关系为R1>R2>Rn或者R2>R1>Rn。本发明的超级结结构包括多个交替排列的P区415和N1下外延层402，其中，P区415主要位于屏蔽栅电极406的底部下方，并与外延层的下表面416相接触。
图4B所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件与图4A所述的发明具有相似的结构，除了在本发明中，超级结结构位于N+衬底400’的上方，超级结结构的P区415’主要位于屏蔽栅电极406’的底部下方，且并未接触到外延层的底部表面416’。
图5所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件形成在N+衬底500之上，还进一步包括一个位于N+衬底500和外延层之间的、电阻率为Rn的N缓冲层520。与图4A所述发明的结构类似，本发明的外延层也包括电阻率为R1的N1下外延层502和电阻率为R2的N2上外延层503，其中，R1、R2和Rn的关系为R1>R2>Rn或者R2>R1>Rn。本发明的超级结结构包括多个交替排列的P1区515和N1下外延层502，用作结阻挡层，其中，P1区515主要位于屏蔽栅电极506的底部下方，并与外延层的下表面516相接触。
图6A所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件为IGBT(绝缘栅双极型晶体管)器件，本发明与图3所述的发明具有相似的结构，除了在本发明中，所述IGBT器件形成在P+衬底600之上，还进一步包括一个位于P+衬底600和N外延层602之间的、电阻率为Rn的N缓冲层620，所述外延层为具有均匀掺杂浓度、且电阻率为R的单一外延层，其中R>Rn。
图6B所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件为另一个IGBT器件，本发明与图6A所述的发明具有相似的结构，除了在本发明中，还进一步包括多个N型电荷存储区(n-cs)630，其位于N外延层602’的较高部分、p体区610’的底部下方，其中，所述的N型电荷存储区630的掺杂浓度高于N外延层602’。
图7A所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件为另一个IGBT器件，本发明与图6A所述的发明具有相似的结构，除了在本发明中，外延层包括电阻率为R1的N1下外延层702和电阻率为R2的N2上外延层703，其中，R1、R2和Rn的关系为R1>R2>Rn或者R2>R1>Rn。本发明的超级结结构包括多个交替排列的P区715和N1下外延层702，其中，P区715主要位于屏蔽栅电极706的底部下方，并与外延层的下表面716相接触。
图7B所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件为另一个IGBT器件，本发明与图7A所述的发明具有相似的结构，除了在本发明中，还进一步包括多个N型电荷存储区(n-cs)730，其位于N2上外延层703’的较高部分、p体区710’的底部下方，其中，所述的N型电荷存储区730的掺杂浓度高于N2上外延层703’。
图8A所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件为另一个IGBT器件，本发明与图7A所述的发明具有相似的结构，除了在本发明中，还进一步包括位于P+衬底800的多个重掺杂N+区840，用以形成多个交替排列的P+和N+区，作为集成的RC二极管。
图8B所示的是根据本发明的另一个优选实施例，所述的N沟道沟槽式半导体功率器件为另一个IGBT器件，本发明与图8A所述的发明具有相似的结构，除了在本发明中，还进一步包括多个N型电荷存储区(n-cs)830，其位于N2上外延层803’的较高部分、p体区810’的底部下方，其中，所述的N型电荷存储区830的掺杂浓度高于N2上外延层803’。
图9A～9F是一系列典型的制造步骤，用于形成本发明图4A中的SGT MOSFET。如图9A所示，首先在N+衬底900上生长N1外延层902，接着利用外延层P型沟槽填充法或多外延生长法，在N1外延层902中形成P区915，形成超级结结构。其中多外延生长法，通过离子注入将P型杂质注入到N1外延层902的特定区域，并重复该步骤直至形成一个特定的漂移层厚度，最后，利用热扩散法制备交替排列的N型和P型区域，即超级结结构。
如图9B所示，在超级结结构的上表面生长N2外延层903。
如图9C所示，首先在N2外延层903的上表面形成一层如氧化层的硬掩模(图中未显示)，用于定义多个栅沟槽区域。随后，采用干法氧化刻蚀和干法硅刻蚀形成多个栅沟槽904，所述栅沟槽904穿过硬掩模的开放区域、N2外延层903并延伸入P区915，但并未接触N+衬底900的上表面。同时，形成至少一个栅接触沟槽904’，所述栅接触沟槽904’也从N2外延层903的上表面延伸入P区915，但并未接触N+衬底900的上表面。在N2外延层903中，台面形成于每两个相邻栅沟槽904之间，以及栅沟槽904和904’之间。随后，生长一层用作牺牲层的氧化层(图中未显示)并将其去除，以消除栅沟槽904和904’形成过程中引入的等离子体损伤。移除硬掩模，并通过热氧化生长法或厚氧化层沉积法，沿栅沟槽的内表面生长一层厚氧化层作为第一栅绝缘层905。沉积第一掺杂多晶硅层于第一栅绝缘层905之上，填充栅沟槽904和栅接触沟槽904’，并从N2外延层903的上表面回刻蚀所述第一掺杂多晶硅层作为屏蔽栅电极906。随后，从外延层903的上表面、栅沟槽904和栅接触沟槽904’的上部回刻蚀第一栅绝缘层905。
如图9D所示，沿所述栅沟槽904和栅接触沟槽904’的上部内表面，生长一层薄氧化层作为第二栅绝缘层907，其覆盖第一栅绝缘层905的上表面以及屏蔽栅电极906。形成第三栅绝缘层909，在第二栅绝缘层907热氧化期间，通过完全氧化所述第一栅绝缘层905上方屏蔽栅电极906的上部实现；随后，沉积第二掺杂多晶硅层填充栅沟槽904和栅接触沟槽904’，并利用CMP法或等离子体刻蚀法回刻蚀所述第二掺杂多晶硅层，作为分裂栅电极908。分裂栅电极908位于栅沟槽904和栅接触沟槽904’中，对称地分布在屏蔽栅电极906的上部两侧，并临近沟槽侧壁。随后，实施P型掺杂物的离子注入，并进行扩散操作，在每两个相邻栅沟槽904之间、以及相邻栅沟槽904和栅接触沟槽904’之间形成p体区910。接着，覆盖一个源掩膜版(图中未显示)于外延层903的上表面，实施N型掺杂物的离子注入，并进行扩散操作，在有源区内、p体区910的上表面附近、两相邻的栅沟槽904之间形成n+源区911。
如图9E所示，沉积另一氧化层于外延层的上表面作为接触隔层919。随后，在接触隔层919上覆盖一个接触区掩膜版(图中未显示)，通过相继的干法氧刻蚀和干法硅刻蚀形成多个沟槽接触区913。所述沟槽接触区913穿过接触隔层919，分别延伸入p体区910形成沟槽式源-体接触区，或延伸入分裂栅电极908形成沟槽栅接触区。然后，实施BF2离子注入，在p体区910内形成p+体接触掺杂区914，其至少包围沟槽式源-体接触区的底部并延伸入体区910。
如图9F所示，沉积Ti/TiN或Co/TiN或Ta/TiN势垒金属层于沟槽接触区，随后沉积W金属层于所述势垒金属层之上，回刻蚀W金属层和势垒金属层，在沟槽式源-体接触区924形成接触金属插塞923，在沟槽式栅接触区926和928形成接触金属插塞925和927。沉积一Al合金金属层或Cu金属层于接触隔层919的上表面，所述Al合金金属层或Cu金属层的下方衬以Ti或Ti/TiN减阻层。随后，覆盖一个金属掩膜版(图中未显示)，刻蚀金属层形成源极金属912和栅极金属层922。
尽管在此说明了各种实施例，可以理解，在不脱离本发明的精神和范围的所附权利要求书的范围内，通过所述的指导，可以对本发明作出各种修改。例如，可以用本发明的方法形成其导电类型与文中所描述的相反的导电类型的各种半导体区域的结构。

Claims (17)

1.一种包含SGT MOSFET的沟槽式半导体功率器件，所述SGT MOSFET形成在位于衬底之上的、具有第一导电类型的外延层上，其进一步包括：
多个沟槽栅，其被具有所述第一导电类型的源区所包围，所述源区位于具有第二导电类型的体区中，并接近所述外延层的上表面，其中，每个所述的沟槽栅都包括一对分裂栅电极和一个屏蔽栅电极；
氧化层电荷平衡区，形成于每两个相邻的沟槽栅之间；
超级结结构，形成于所述衬底上方且位于所述氧化层电荷平衡区下方，包括多个交替形成的P区和N区；
所述屏蔽栅电极位于沟槽栅下部，其与所述外延层之间通过第一栅绝缘层相互绝缘，所述一对分裂栅电极位于沟槽栅上部，且与所述外延层之间通过第二栅绝缘层相互绝缘，所述第二绝缘层的厚度小于所述第一绝缘层的厚度，且所述屏蔽栅电极和所述一对分裂栅电极之间相互绝缘，所述一对分裂栅电极之间由第三栅绝缘层相互绝缘；并且
所述体区、所述屏蔽栅电极和所述源区通过多个沟槽式接触区短接至源极金属层。
2.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述衬底具有所述第一导电类型，所述外延层为具有均匀掺杂浓度的单一绝缘层。
3.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述衬底具有所述第一导电类型，所述外延层包括电阻率为R1的下外延层和电阻率为R2的上外延层，其中，R1和R2的关系为R1>R2。
4.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述衬底具有所述第一导电类型，所述外延层包括电阻率为R1的下外延层和电阻率为R2的上外延层，其中，R1和R2的关系为R1<R2。
5.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述衬底具有所述第一导电类型，所述外延层为具有均匀掺杂浓度、且电阻率为R的单一外延层，所述沟槽式半导体功率器件还进一步包括一个具有第一导电类型、且电阻率为Rn的缓冲外延层，所述缓冲外延层位于衬底和所述外延层之间，其中R>Rn。
6.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述衬底具有所述第二导电类型，所述外延层为具有均匀掺杂浓度、且电阻率为R的单一外延层，所述沟槽式半导体功率器件还进一步包括一个具有第一导电类型、且电阻率为Rn的缓冲外延层，所述缓冲外延层位于衬底和所述外延层之间，其中R>Rn。
7.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述衬底具有所述的第二导电类型，所述外延层包括电阻率为R1的下外延层和电阻率为R2的上外延层，所述屏蔽栅沟槽式MOSFET还进一步包括一个具有第一导电类型、且电阻率为Rn的缓冲外延层，所述缓冲外延层位于衬底和所述下外延层之间，其中，R1、R2和Rn的关系为R1>R2>Rn。
8.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述衬底具有所述的第二导电类型，所述外延层包括电阻率为R1的下外延层和电阻率为R2的上外延层，所述屏蔽栅沟槽式MOSFET还进一步包括一个具有第一导电类型、且电阻率为Rn的缓冲外延层，所述缓冲外延层位于衬底和所述下外延层之间，其中，R1、R2和Rn的关系为R2>R1>Rn。
9.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述超级结结构的所述P区主要位于所述屏蔽栅电极的底部下方，并与所述外延层的底部表面相接触。
10.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述超级结结构的所述P区主要位于所述屏蔽栅电极的底部下方，但并未接触到所述外延层的底部表面。
11.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述衬底具有第二导电类型，且所述沟槽式半导体功率器件还进一步包括：一个缓冲层，其为第一导电类型，且位于衬底和外延层之间；以及多个位于衬底的、具有第一导电类型的重掺杂区域，形成多个交替排列的P+区和N+区。
12.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述沟槽式半导体功率器件还进一步包括：一个具有所述第一导电类型的电荷存储区，其位于所述外延层中、所述体区的下方，其中，所述电荷存储区的掺杂浓度高于所述外延层。
13.如权利要求1所述的沟槽式半导体功率器件，其特征在于，如果所述第一导电类型为N型，则所述第二导电类型为P型。
14.如权利要求1所述的沟槽式半导体功率器件，其特征在于，如果所述第一导电类型为P型，则所述第二导电类型为N型。
15.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述超级结结构可通过多外延生长法形成，所述多外延生长法通过离子注入将P型杂质注入到各外延层的特定区域，并重复该步骤。
16.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述超级结结构可通过外延层P型沟槽填充法形成。
17.如权利要求1所述的沟槽式半导体功率器件，其特征在于，所述超级结结构可通过具有不同注入能量的硼离子注入形成，所述的硼离子注入通过所述沟槽栅的底部来实现。
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CN114023804A (zh) * 2021-07-06 2022-02-08 娜美半导体有限公司 具有多阶梯外延层结构的屏蔽栅沟槽式半导体功率器件
CN113838918A (zh) * 2021-09-23 2021-12-24 电子科技大学 具有载流子浓度增强的超结igbt器件结构及制作方法
CN113838918B (zh) * 2021-09-23 2023-10-24 电子科技大学 具有载流子浓度增强的超结igbt器件结构及制作方法
CN113782612A (zh) * 2021-09-27 2021-12-10 西安理工大学 一种超结屏蔽栅沟槽mosfet结构及制作方法
CN114582965A (zh) * 2022-05-06 2022-06-03 南京微盟电子有限公司 一种低开关损耗功率器件结构及其制造方法
CN115425083A (zh) * 2022-07-19 2022-12-02 深圳安森德半导体有限公司 具有屏蔽栅沟槽结构的超级结半导体功率器件
CN115425083B (zh) * 2022-07-19 2024-05-17 深圳安森德半导体有限公司 具有屏蔽栅沟槽结构的超级结半导体功率器件
CN117174738A (zh) * 2023-11-02 2023-12-05 苏州迈志微半导体有限公司 一种沟槽屏蔽栅mosfet器件及其制造方法和电子设备

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