CN114023804A - 具有多阶梯外延层结构的屏蔽栅沟槽式半导体功率器件 - Google Patents

具有多阶梯外延层结构的屏蔽栅沟槽式半导体功率器件 Download PDF

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CN114023804A
CN114023804A CN202111175693.4A CN202111175693A CN114023804A CN 114023804 A CN114023804 A CN 114023804A CN 202111175693 A CN202111175693 A CN 202111175693A CN 114023804 A CN114023804 A CN 114023804A
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谢福渊
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Nami Semiconductor Co ltd
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Abstract

本发明公开了一种新型的屏蔽栅沟槽式MOSFETs，其外延层具有特殊的多阶梯外延层(MSE)结构，所述多阶梯外延层的掺杂浓度自衬底至体区方向呈阶梯式递减，其中每个多阶梯外延层都具有均匀的掺杂浓度。特殊的MSE结构显著降低了器件的比导通电阻。此外，在一些优选实施例中，屏蔽栅极采用多阶梯侧壁氧化层(MSO)结构以进一步降低器件的比导通电阻、增强器件的坚固性。

Description

具有多阶梯外延层结构的屏蔽栅沟槽式半导体功率器件
技术领域
本发明主要涉及半导体功率器件，更具体地，本发明涉及屏蔽栅沟槽式(SGT)金属氧化物半导体场效应晶体管(MOSFET)，其具有多阶梯外延层(MSE)结构以获得更好的器件性能。
背景技术
图1所示为具有均匀外延层的传统SGT MOSFET，与传统的单栅沟槽式MOSFETs相比，其具有更低的栅电荷和比导通电阻，这归因于漂移区内氧化层电荷平衡区以及栅极下方厚氧化层的存在。然而，由于芯片间距的减小，器件的芯片尺寸也变小，传统的SGTMOSFETs面临雪崩能力退化的问题。典型地，在均匀的外延层中，两个电场和碰撞电离峰分别位于沟道区和沟槽底部附近，且沟道区附近的电场强度总是高于沟槽底部的电场强度，从而导致沟道区附近发生雪崩。存在于沟道区的寄生双极晶体管(n+/p/N)很容易被开启，从而导致器件在较低的雪崩能量等级时失效。
因此，仍需要提供一种新型的器件结构以解决上述所涉及的问题和限制，可通过减小沟道区附近的电场强度使得雪崩发生在沟槽底部而非沟道区，从而进一步提升器件的直流/交流(DC/AC)性能和器件的坚固性。
发明内容
本发明公开了新型的SGT MOSFETs，其外延层具有多阶梯外延层(MSE)结构，其掺杂浓度自衬底至体区方向呈阶梯式递减，其中每个多阶梯外延层都具有均匀的掺杂浓度。与传统的SGT MOSFETs相比，在任何期望的击穿电压下，本发明公开的这种具有新型MSE结构的外延层厚度更薄，漂移区的掺杂浓度更高，因此器件的比导通电阻显著降低。由于沟道区附近的掺杂浓度最低，沟道区附近的电场强度低于沟槽底部。使得雪崩发生在沟槽底部而非沟道区，从而增强了雪崩能力和器件的坚固度。
将MSE结构与多阶梯侧壁氧化层(MSO)结构相结合，可在不降低击穿电压的前提下，通过提高掺杂浓度，进一步降低比导通电阻。该MSO结构是一个围绕屏蔽栅极的场板氧化层，其具有自衬底至体区方向厚度呈阶梯式递减的多阶梯侧壁氧化层，其中每个阶梯侧壁氧化层的厚度是均匀的。
本发明的一个方面，是公开了一种SGT MOSFET，所述SGT MOSFET形成在具有第一导电类型的外延层内，所述外延层位于具有第一导电类型的衬底之上，其进一步包括：多个栅沟槽，其被具有第一导电类型的源区所包围，源区位于具有第二导电类型的体区中，并接近外延层的上表面，其中，每个栅沟槽都包括一个栅极和一个屏蔽栅极；屏蔽栅极与外延层间通过第一绝缘层实现绝缘，栅极位于屏蔽栅极的上方，且栅极与外延层间通过栅氧化层实现绝缘，屏蔽栅极与栅极间通过多晶硅间氧化层(IPO)实现绝缘，栅氧化层围绕栅极，且其厚度薄于第一绝缘层；一个氧化层电荷平衡区，位于相邻的栅沟槽之间；体区，屏蔽栅极和源区，通过多个沟槽式接触区连至源金属；外延层具有多阶梯外延层(MSE)结构，其掺杂浓度自衬底至体区方向呈阶梯式递减，其中每个多阶梯外延层都具有均匀的掺杂浓度。
根据本发明的另一个方面，在一些优选实施例中，外延层包括至少两个具有不同掺杂浓度的阶梯外延层：掺杂浓度为D1的下外延层以及位于下外延层之上、掺杂浓度为D2的上外延层，其中，D1和D2的关系为D2<D1。在另一些优选实施例中，外延层包括至少三个具有不同掺杂浓度的阶梯外延层：掺杂浓度为D1的下外延层，掺杂浓度为D2的中外延层以及掺杂浓度为D3的上外延层，其中，D1，D2和D3的关系为D3<D2<D1。
根据本发明的另一个方面，在一些优选实施例中，外延层具有位于衬底之上、栅沟槽底部之下的下外延层。
根据本发明的另一个方面，在一些优选实施例中，第一绝缘层为具有均匀厚度的单一氧化层。在另一些优选实施例中，第一绝缘层具有多阶梯侧壁氧化层结构，其厚度自衬底至体区方向呈阶梯式递减。在另一些优选实施例中，第一绝缘层具有两个阶梯侧壁氧化层结构：沿栅沟槽下部侧壁和底部的下氧化层，以及上氧化层，其中，下氧化层的厚度大于上氧化层。在另一些优选实施例中，第一绝缘层具有三个阶梯侧壁氧化层结构：沿栅沟槽下部侧壁和底部的下氧化层，中氧化层，以及上氧化层，其中，下氧化层的厚度大于中氧化层，中氧化层的厚度大于上氧化层。
根据本发明的另一个方面，在一些优选实施例中，栅沟槽的每个侧壁基本垂直于外延层的上表面，二者间的夹角范围为88°至90°。
根据本发明的另一个方面，在一些优选实施例中，如果第一导电类型为N型，则第二导电类型为P型。在另一些优选实施例中，如果第一导电类型为P型，则第二导电类型为N型。
通过参考以下各个附图，阅读下文对优选实施例的详细描述，本发明的上述及其他的目的和优点对于本领域的普通技术人员来说无疑是显而易见的。
附图说明
图1是现有技术所揭示的一种传统SGT MOSFET的横截面图。
图2A是根据本发明的一个优选实施例的横截面图，该实施例具有两个阶梯外延层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。
图2B是根据本发明的另一个优选实施例的横截面图，该实施例具有两个阶梯外延层结构以及作为第一绝缘层的两个阶梯侧壁氧化层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。
图2C是根据本发明的另一个优选实施例的横截面图，该实施例具有两个阶梯外延层结构以及作为第一绝缘层的三个阶梯侧壁氧化层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。
图3A是根据本发明的一个优选实施例的横截面图，该实施例具有改进的三个阶梯外延层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。
图3B是根据本发明的另一个优选实施例的横截面图，该实施例具有三个阶梯外延层结构以及作为第一绝缘层的两个阶梯侧壁氧化层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。
图3C是根据本发明的另一个优选实施例的横截面图，该实施例具有三个阶梯外延层结构以及作为第一绝缘层的三个阶梯侧壁氧化层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。
具体实施方式
下面参照附图更详细地说明本发明，其中示出了本发明的优选实施例。本发明可以，但是以不同的方式体现，但是不应该局限于在此所述的实施例。例如，这里的说明更多地引用N沟道的半导体集成电路，但是很明显其他器件也是可能的。下文是通过参考各个附图来对实践本发明的优选实施例进行详细描述。一些方向术语，例如“顶部”、“底部”、“前”、“后”、“上方”、“下方”等，是参考各个附图的方向进行描述的。由于实施例中的元件可以被放置在许多不同的方向，因此，本发明中的方向术语只是用于描述而不能被视为对本发明的限制。应该理解的是，实施例中各种结构或者逻辑上的替代和修改都应该被涵盖在本发明的真正精神和范围内。因此，以下的详细描述不能被视为对本发明的限制，本发明的涵盖范围由附后的权利要求界定。应该理解的是，本发明中所描述的各个优选实施例的发明特征可以相互结合，有特别说明的除外。
图2A是根据本发明的一个优选实施例的横截面图，该实施例具有两个阶梯外延层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。所述沟槽式半导体功率器件包括一个在N外延层上形成的N沟道SGT MOSFET，该外延层位于N+衬底200之上，衬底200的背面涂有Ti/Ni/Ag后金属层201用作漏金属。N外延层包括一个掺杂浓度为D1的下外延层(1st Epi，如图所示)202以及位于下外延层202之上、掺杂浓度为D2的上外延层(2nd Epi，如图所示)203，其中，D1和D2的关系为D2<D1，以提高击穿电压、降低比导通电阻。在N外延层中，形成多个栅沟槽204，所述栅沟槽204从上外延层(2nd Epi，如图所示)203的上表面向下延伸入下外延层(1st Epi，如图所示)202中，其中，栅沟槽204的沟槽底部位于N+衬底200和下外延层(1stEpi，如图所示)202的公共界面之上。每个栅沟槽204，都包括位于沟槽较低部分的一个屏蔽栅极(SG，如图所示)205，以及位于沟槽较高部分的单栅极(G，如图所示)207。屏蔽栅极205与相邻外延层间通过第一绝缘层206实现绝缘，栅极207与相邻外延层间通过栅氧化层209实现绝缘，其中栅氧化层209的厚度小于第一绝缘层206，且第一绝缘层206沿沟槽侧壁具有均匀的厚度。同时，屏蔽栅极205与栅极207间通过多晶硅间氧化层(IPO)208实现绝缘。在每两个相邻的沟槽栅204之间，形成一个具有n+源区211的P体区210，其从上外延层(2nd Epi，如图所示)203的上表面附近延伸。p体区210，n+源区211和屏蔽栅极205，通过多个沟槽式接触区213连至源金属212。多个沟槽式接触区213均填充以金属插塞和势垒层，其穿过绝缘层217延伸至体区中，每个沟槽式接触区213的底部均由位于n+源区211下方的p+体接触区214所包围。根据本发明，氧化层电荷平衡区形成于相邻的栅沟槽204之间。
图2B是根据本发明的另一个优选实施例的横截面图，该实施例具有两个阶梯外延层结构以及作为第一绝缘层的两个阶梯侧壁氧化层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。所述的N沟道沟槽式半导体功率器件与图2A所述的发明具有相似的结构，除了在本发明中，位于栅沟槽204’的第一绝缘层206’具有两个阶梯侧壁氧化层结构：沿栅沟槽204’下部侧壁和底部的、厚度均匀为Tox,l的下氧化层，以及厚度均匀为Tox,u的上氧化层，其中，Tox,l和Tox,u的关系为Tox,l>Tox,u，以在保持相同击穿电压的同时进一步降低比导通电阻。
图2C是根据本发明的另一个优选实施例的横截面图，该实施例具有两个阶梯外延层结构以及作为第一绝缘层的三个阶梯侧壁氧化层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。所述的N沟道沟槽式半导体功率器件与图2A所述的发明具有相似的结构，除了在本发明中，位于栅沟槽204”的第一绝缘层206”具有三个阶梯侧壁氧化层结构：沿栅沟槽204”下部侧壁和底部的、厚度均匀为Tox,l的下氧化层，厚度均匀为Tox,m的中氧化层，以及厚度均匀为Tox,u的上氧化层，其中，Tox,l，Tox,m和Tox,u的关系为Tox,l>Tox,m>Tox,u，以在保持相同击穿电压的同时进一步降低比导通电阻。其中，Tox,m可以是Tox,l和Tox,u的平均值。
图3A是根据本发明的一个优选实施例的横截面图，该实施例具有改进的三个阶梯外延层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。所述的N沟道沟槽式半导体功率器件与图2A所述的发明具有相似的结构，除了在本发明中，N外延层包括三个具有不同掺杂浓度的阶梯外延层：掺杂浓度为D1的下外延层(1st Epi，如图所示)302，掺杂浓度为D2的中外延层(2nd Epi，如图所示)303以及掺杂浓度为D3的上外延层(3rd，如图所示)313，其中，D1，D2和D3的关系为D3<D2<D1，以进一步降低比导通电阻。其中，D2可以是D1和D3的平均值。
图3B是根据本发明的另一个优选实施例的横截面图，该实施例具有三个阶梯外延层结构以及作为第一绝缘层的两个阶梯侧壁氧化层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。所述的N沟道沟槽式半导体功率器件与图3A所述的发明具有相似的结构，除了在本发明中，位于栅沟槽304’的第一绝缘层306’具有两个阶梯侧壁氧化层结构：沿栅沟槽304’下部侧壁和底部的、厚度均匀为Tox,l的下氧化层，以及厚度均匀为Tox,u的上氧化层，其中，Tox,l和Tox,u的关系为Tox,l>Tox,u，以在保持相同击穿电压的同时进一步降低比导通电阻。
图3C是根据本发明的另一个优选实施例的横截面图，该实施例具有三个阶梯外延层结构以及作为第一绝缘层的三个阶梯侧壁氧化层结构，并揭示了外延层掺杂浓度沿垂直方向的变化。所述的N沟道沟槽式半导体功率器件与图3A所述的发明具有相似的结构，除了在本发明中，位于沟槽304”的第一绝缘层306”具有三个阶梯侧壁氧化层结构：沿栅沟槽304”下部侧壁和底部的、厚度均匀为Tox,l的下氧化层，厚度均匀为Tox,m的中氧化层，以及厚度均匀为Tox,u的上氧化层，其中，Tox,l，Tox,m和Tox,u的关系为Tox,l>Tox,m>Tox,u，以在保持相同击穿电压的同时进一步降低比导通电阻。其中，Tox,m可以是Tox,l和Tox,u的平均值。
虽然依照优选实施例对本发明进行了描述，但应该理解的是上述公开不能被视为是对本发明的限制。上述所描述的实施例通常为N沟道器件，通过反转导电类型的极性，实施例也可应用于P沟道器件。在阅读了上述公开的内容之后，各种替代和修改对于本技术领域的技术人员无疑是显而易见的。因此，附后的权利要求应被解释为涵盖落入本发明的真正精神和范围内的所有替代和修改。

Claims (14)

1.一种屏蔽栅沟槽式(SGT)MOSFET，所述SGT MOSFET形成在具有第一导电类型的外延层内，所述外延层位于所述的具有第一导电类型的衬底之上，其进一步包括：
多个栅沟槽，其被具有所述第一导电类型的源区所包围，所述源区位于具有第二导电类型的体区中，并接近所述外延层的上表面，其中，每个所述的栅沟槽都包括一个栅极和一个屏蔽栅极；所述屏蔽栅极与所述外延层间通过第一绝缘层实现绝缘，所述栅极与所述外延层间通过栅氧化层实现绝缘，所述屏蔽栅极与所述栅极间通过多晶硅间氧化层(IPO)实现绝缘，所述栅氧化层围绕所述栅极，且所述栅氧化层的厚度小于所述第一绝缘层；
一个氧化层电荷平衡区，位于相邻的所述栅沟槽之间；
所述体区，所述屏蔽栅极和所述源区，通过多个沟槽式接触区连至源金属；
所述外延层具有多阶梯外延层(MSE)结构，其掺杂浓度自衬底至所述体区方向呈阶梯式递减，其中每个所述的多阶梯外延层都具有均匀的掺杂浓度。
2.如权利要求1所述的SGT MOSFET，其特征在于，所述栅极位于所述屏蔽栅极之上。
3.如权利要求1所述的SGT MOSFET，其特征在于，所述外延层包括至少两个具有不同掺杂浓度的阶梯外延层：掺杂浓度为D1的下外延层以及位于所述下外延层之上、掺杂浓度为D2的上外延层，其中，D1和D2的关系为D2<D1。
4.如权利要求1所述的SGT MOSFET，其特征在于，所述外延层包括至少三个具有不同掺杂浓度的阶梯外延层：掺杂浓度为D1的下外延层，掺杂浓度为D2的中外延层以及掺杂浓度为D3的上外延层，其中，D1，D2和D3的关系为D3<D2<D1。
5.如权利要求4所述的SGT MOSFET，其特征在于，所述D2为所述D1和所述D3的平均值。
6.如权利要求1所述的SGT MOSFET，其特征在于，所述多阶梯外延层具有位于所述衬底之上、所述栅沟槽底部之下的下外延层。
7.如权利要求1所述的SGT MOSFET，其特征在于，所述第一绝缘层为沿所述栅沟槽的侧壁、具有均匀厚度的单一氧化层。
8.如权利要求1所述的SGT MOSFET，其特征在于，所述第一绝缘层具有多阶梯侧壁氧化层结构，其厚度自所述衬底至所述体区方向呈阶梯式递减。
9.如权利要求8所述的SGT MOSFET，其特征在于，所述第一绝缘层具有两个阶梯侧壁氧化层结构：沿所述栅沟槽下部侧壁和底部的、厚度为Tox,l的下氧化层，以及厚度为Tox,u的上氧化层，其中，Tox,l和Tox,u的关系为Tox,l>Tox,u。
10.如权利要求8所述的SGT MOSFET，其特征在于，所述第一绝缘层具有三个阶梯侧壁氧化层结构：沿所述栅沟槽下部侧壁和底部的、厚度为Tox,l的下氧化层，厚度为Tox,m的中氧化层，以及厚度为Tox,u的上氧化层，其中，Tox,l，Tox,m和Tox,u的关系为Tox,l>Tox,m>Tox,u。
11.如权利要求10所述的SGT MOSFET，其特征在于，所述Tox,m为所述Tox,l和所述Tox,u的平均值。
12.如权利要求1所述的SGT MOSFET，其特征在于，所述栅沟槽的每个侧壁基本垂直于与所述外延层的上表面，二者间的夹角范围为88°至90°。
13.如权利要求1所述的SGT MOSFET，其特征在于，如果所述第一导电类型为N型，则所述第二导电类型为P型。
14.如权利要求1所述的SGT MOSFET，其特征在于，如果所述第一导电类型为P型，则所述第二导电类型为N型。
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