CN111509049A - 一种屏蔽栅沟槽式金属氧化物半导体场效应管 - Google Patents

一种屏蔽栅沟槽式金属氧化物半导体场效应管 Download PDF

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CN111509049A
CN111509049A CN202010229855.7A CN202010229855A CN111509049A CN 111509049 A CN111509049 A CN 111509049A CN 202010229855 A CN202010229855 A CN 202010229855A CN 111509049 A CN111509049 A CN 111509049A
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epitaxial layer
power device
gate electrode
semiconductor power
substrate
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谢福渊
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Nami Semiconductor Co ltd
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Abstract

本发明公开了一种半导体功率器件，包括多个沟槽栅，每个沟槽栅内包括一个栅电极和一个屏蔽栅电极，以形成位于每两个相邻的沟槽栅之间的氧化层电荷平衡区；根据本发明的半导体功率器件还包括一个位于衬底上方的超级结结构，其包括多个交替形成的P区和N区，以形成位于氧化层电荷平衡区下方的结电荷平衡区，用以提高击穿电压、降低导通电阻和输出电荷。

Description

一种屏蔽栅沟槽式金属氧化物半导体场效应管
技术领域
本发明涉及一种功率半导体器件的单元结构，特别涉及一种新型的屏蔽栅沟槽式金属氧化物半导体场效应管(Shielded Gate Trench Metal oxide Semiconductor FieldEffect Transistor,SGT MOSFET)的单元结构，其包括氧化层电荷平衡区和超级结(superjunction)结构，以获得更高的击穿电压、更低的导通电阻和输出电容。
背景技术
图1A、1B和1C分别示出了现有技术中三种典型的SGT MOSFET结构，与传统的具有单栅结构的沟槽式MOSFET相比，图1A～图1C中所示的三种结构由于具有位于漂移区的氧化层电荷平衡区(如图1A所示)和位于栅电极下方的厚氧化层，从而具有更低的栅电荷和导通电阻。然而，这三种结构很容易在沟槽栅的底部发生过早击穿，从而导致击穿电压的大幅下降。
为了改进过早击穿的问题，美国专利号U.S.Patent No.8，159，021揭示了一种具有双外延层结构的SGT MOSFET，如图1D所示，其中第一外延层(N1 Epi，如图1D所示)的电阻率大于第二外延层(N2 Epi)的电阻率，并且沟槽栅的底部位于第一外延层中，以防止过早击穿的发生。然而，由于沟槽栅底部的击穿电压与沟槽栅底部氧化层的厚度和沟槽的深度密切相关，该现有技术的击穿电压在整个芯片上有一个比较大的变化幅度。与此同时，由于第一外延层的电阻率大于第二外延层的电阻率，导致图1D所示的现有技术的导通电阻高于图1A～图1C所示现有技术的导通电阻。
因此，在半导体功率器件领域中，特别是对于SGT MOSFET的设计和制造，仍需要提供一种新型的单元结构、器件结构和改良的制造工艺，可以解决现有技术中的问题，以提高器件性能。
发明内容
本发明提供了一种包括氧化层电荷平衡区和结电荷平衡区的SGT MOSFET，其中，氧化层电荷平衡区位于每两个相邻的沟槽栅之间，结电荷平衡区包括一个超级结结构，其位于沟槽栅的下方，以确保漂移区全部被耗尽并且确保击穿发生在相邻的沟槽栅的中间，而不是过早发生于沟槽栅底部。同时，本发明的击穿电压对于沟槽栅底部氧化层的厚度以及沟槽栅深度的敏感度被降低，雪崩特性得以增强，并且在不增加导通电阻的同时，由于沟槽栅深度变浅使得输出电容Coss(与屏蔽栅MOS电容和台面耗尽电容相关)得以降低。
根据本发明的一个方面，提供了一种半导体功率器件，包括一个SGT MOSFET，其形成于第一导电类型的外延层中并位于一层衬底之上，其特征在于，还包括：
(a)多个沟槽栅，周围围绕有第一导电类型的源区、第二导电类型的体区和所述外延层，其中所述源区和体区靠近所述外延层的上表面且所述源区位于所述体区的上方，每个所述沟槽栅中包括一个栅电极和一个屏蔽栅电极；
(b)氧化层电荷平衡区，形成于每两个相邻的沟槽栅之间；
(c)超级结结构，形成于所述衬底上方且位于所述氧化层电荷平衡区下方，包括多个交替形成的P区和N区；
(d)所述屏蔽栅电极与所述外延层之间通过第一绝缘层相互绝缘，所述栅电极与所述外延层之间通过第二绝缘层相互绝缘，所述第二绝缘层的厚度小于所述第一绝缘层的厚度，且所述屏蔽栅电极和所述栅电极之间相互绝缘；并且
(e)所述体区、所述屏蔽栅电极和所述源区通过多个沟槽式接触区短接至源极金属层。
根据本发明的另一个方面，在一些优选的实施例中，所述衬底为第一导电类型，所述外延层为具有均匀掺杂浓度的单外延层结构。在另一些优选的实施例中，所述衬底为第一导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，其中R1>R2。在另一些优选的实施例中，所述衬底为第一导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，其中R1<R2。在另一些优选的实施例中，所述衬底为第二导电类型，所述外延层为具有均匀掺杂浓度的单外延层结构，其电阻率为R，所述半导体功率器件还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R>Rn。在另一些优选的实施例中，所述衬底为第二导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，所述半导体功率器件还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R1>R2>Rn。在另一些优选的实施例中，所述衬底为第二导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，所述半导体功率器件还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R2>R1>Rn。
根据本发明的另一个方面，在一些优选的实施例中，所述超级结结构的P区主要位于所述屏蔽栅电极的下方，并延伸至碰触所述外延层的底面。在另一些优选的实施例中，所述超级结结构的P区主要位于所述屏蔽栅电极的下方，但没有碰触所述外延层的底面。
根据本发明的另一个方面，在一些优选的实施例中，所述屏蔽栅电极位于所述沟槽栅的中央，所述栅电极围绕所述屏蔽栅电极的上部分，并且所述栅电极和所述屏蔽栅电极之间通过所述第二绝缘层相互绝缘。在另一些优选的实施例中，所述屏蔽栅电极位于所述沟槽栅的下部分，且与所述外延层之间通过所述第一绝缘层相互绝缘，所述栅电极位于所述沟槽栅的上部分，且与所述屏蔽栅电极之间通过第三绝缘层相互绝缘。更优选地，所述第一绝缘层为具有均匀厚度的单氧化层，或所述第一绝缘层为多台阶氧化层结构，且沿所述沟槽栅底部的厚度最大。
根据本发明的另一个方面，在一些优选的实施例中，所述衬底为所述第二导电类型，所述半导体功率器件还包括：第一导电类型的缓冲层，位于所述衬底和所述外延层之间；多个第一导电类型的重掺杂区，位于所述衬底中，形成位于衬底中的包括多个交替形成的P+区和N+区的集成反向导通二极管。
根据本发明的另一个方面，在一些优选的实施例中，所述半导体功率器件还包括第一导电类型的电荷储存区，其位于所述外延层中并位于所述体区下方，其中所述电荷储存区的多数载流子浓度大于所述外延层。
根据本发明的另一个方面，所述第一导电类型为N型，所述第二导电类型为P型，或所述第一导电类型为P型，所述第二导电类型为N型。
通过参考以下各个附图，阅读下文对优选实施例的详细描述，本发明的上述及其他目的和优点对于本领域的普通技术人员来说无疑是显而易见的。
附图说明
图1A示出了现有技术所揭示的一种SGT MOSFET的剖面图。
图1B示出了现有技术所揭示的另一种SGT MOSFET的剖面图。
图1C示出了现有技术所揭示的另一种SGT MOSFET的剖面图。
图1D示出了现有技术所揭示的另一种SGT MOSFET的剖面图。
图2A是根据本发明的一个优选实施例的剖面图。
图2B是根据本发明的另一个优选实施例的剖面图。
图2C是根据本发明的另一个优选实施例的剖面图。
图2D是根据本发明的另一个优选实施例的剖面图。
图3A是根据本发明的另一个优选实施例的剖面图。
图3B是根据本发明的另一个优选实施例的剖面图。
图3C是根据本发明的另一个优选实施例的剖面图。
图3D是根据本发明的另一个优选实施例的剖面图。
图4A是根据本发明的另一个优选实施例的剖面图。
图4B是根据本发明的另一个优选实施例的剖面图。
图4C是根据本发明的另一个优选实施例的剖面图。
图4D是根据本发明的另一个优选实施例的剖面图。
图5A是根据本发明的另一个优选实施例的剖面图。
图5B是根据本发明的另一个优选实施例的剖面图。
图6A是根据本发明的另一个优选实施例的剖面图。
图6B是根据本发明的另一个优选实施例的剖面图。
图7A是根据本发明的另一个优选实施例的剖面图。
图7B是根据本发明的另一个优选实施例的剖面图。
图8是根据本发明的另一个优选实施例的剖面图。
图9是根据本发明的另一个优选实施例的剖面图。
图10是根据本发明的另一个优选实施例的剖面图。
图11是根据本发明的另一个优选实施例的剖面图。
图12是根据本发明的另一个优选实施例的剖面图。
图13是根据本发明的另一个优选实施例的剖面图。
具体实施方式
下面参照附图更详细地说明本发明，其中示出了本发明的优选实施例。本发明可以，但是以不同的方式体现，但是不应该局限于在此所述的实施例。例如，这里的说明更多地引用N沟道的半导体集成电路，但是很明显其他器件也是可能的。下文是通过参考各个附图来对实践本发明的优选实施例进行详细描述。一些方向术语，例如“顶部”、“底部”、“前”、“后”、“上方”、“下方”等，是参考各个附图的方向进行描述的。由于实施例中的元件可以被放置在许多不同的方向，因此，本发明中的方向术语只是用于描述而不能被视为对本发明的限制。应该理解的是，实施例中各种结构或者逻辑上的替代和修改都应该被涵盖在本发明的真正精神和范围内。因此，以下的详细描述不能被视为对本发明的限制，本发明的涵盖范围由附后的权利要求界定。应该理解的是，本发明中所描述的各个优选实施例的发明特征可以相互结合，有特别说明的除外。
图2A所示的是根据本发明的一个优选的半导体功率器件200，其包括一个形成于N型外延层中的N沟道SGT MOSFET，其中所述N型外延层位于一层N+衬底201的上方，且进一步包括一个电阻率为R1的N1下外延层202和一个电阻率为R2的N2上外延层203，其中R1>R2(或者R1<R2)。该SGT MOSFET还包括多个沟槽栅204，这些沟槽栅204穿过所述N2上外延层203并延伸入所述N1下外延层202中。每个沟槽栅204中包括一个位于下部分的屏蔽栅电极(SG，如图2A所示)205和一个位于上部分的栅电极(G)206，其中所述屏蔽栅电极205与相邻的外延层之间由第一绝缘层207绝缘，所述栅电极206与相邻的外延层之间由第二绝缘层208绝缘，所述屏蔽栅电极205和所述栅电极206之间由第三绝缘层209绝缘，其中所述第二绝缘层208的厚度小于所述第一绝缘层207的厚度。在每两个相邻的所述沟槽栅204之间，还包括一个P型体区210和n+源区211，其中所述P型体区210靠近所述N2上外延层203的上表面，围绕所述栅电极206，且位于所述n+源区211的下方。所述P型体区210、所述n+源区211和所述屏蔽栅电极205都通过多个沟槽式接触区213短接至源极金属层212，其中所述沟槽式接触区213填充以金属插塞，穿过所述n+源区211并延伸入所述P型体区210，其位于所述P型体区210中的部分由p+掺杂区214围绕以降低接触电阻。根据本发明的SGT MOSFET结构，在每两个相邻的沟槽栅204之间会形成一个氧化层电荷平衡区，于此同时，在沟槽栅204下方的N1下外延层202中引入P区215，形成一个包括多个交替形成的P区215和N区202的超级结结构，其位于N+衬底201上方，并位于所述氧化层电荷平衡区的下方，以确保整个漂移区全部耗尽，并且击穿发生在每两个相邻的沟槽栅的中间位置，而不是在沟槽栅底部发生过早击穿。同时，超级结结构的引入，大幅度降低了击穿电压对沟槽栅底部氧化层厚度和沟槽深度的依赖性。在这个优选的实施例图2A中，所述P区215主要位于所述屏蔽栅电极205的下方，并延伸至碰触外延层的底面216。
图2B所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件230与图2A具有相似的结构，除了在图2B中，超级结结构中的P区232主要位于屏蔽栅电极233的下方，但是没有碰触外延层的底面235。
图2C所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件260与图2A具有相似的结构，除了在图2C中，外延层为单外延层结构，仅包括一个N外延层262，其位于N+衬底261上方。与图2A相似，图2C中的超级结结构包括多个交替形成的P区263和N区262，其中，P区263主要位于屏蔽栅电极264下方，并延伸至碰触所述N外延层262的底面266。
图2D所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件300与图2C具有相似的结构，除了在图2D中，超级结结构中的P区302主要位于屏蔽栅电极303的下方，但是没有碰触N外延层306的底面305。
图3A所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件330与图2A具有相似的结构，除了在图3A中，每个沟槽栅331内包括一个位于沟槽栅中央的屏蔽栅电极332和围绕所述屏蔽栅电极332上部分的栅电极333，其中所述屏蔽栅电极332与相邻的外延层之间由第一绝缘层334绝缘，所述栅电极333与相邻的外延层之间依靠第二绝缘层335绝缘，同时，所述屏蔽栅电极332和所述栅电极333之间同样依靠所述第二绝缘层335绝缘。在图3A的SGT MOSFET中，外延层具有与图2A相同的双外延层结构，超级结结构包括多个交替形成的P区336和N区337，其中所述P区336主要位于所述屏蔽栅电极332的下方，并延伸至碰触所述外延层的底面338。
图3B所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件360与图3A具有相似的结构，除了在图3B中，超级结结构中的P区362主要位于屏蔽栅电极363的下方，但是没有碰触外延层的底面365。
图3C所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件400与图3A具有相似的结构，除了在图3C中，外延层为单外延层结构，仅包括一个N外延层402，其位于N+衬底401上方。与图3A相似，图3C中的超级结结构包括多个交替形成的P区403和N区402，其中，P区403主要位于屏蔽栅电极404下方，并延伸至碰触所述N外延层402的底面406。
图3D所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件430与图3C具有相似的结构，除了在图3D中，超级结结构中的P区432主要位于屏蔽栅电极433的下方，但是没有碰触N外延层436的底面435。
图4A所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件460与图2A具有相似的结构，除了在图4A的沟槽栅461中，位于外延层和屏蔽栅电极463之间的第一绝缘层462具有多台阶氧化层结构，其沿沟槽栅461的底部具有最大的厚度。在图4A的SGT MOSFET中，外延层具有与图2A相同的双外延层结构，超级结结构包括多个交替形成的P区464和N区465，其中所述P区464主要位于所述屏蔽栅电极463的下方，并延伸至碰触所述外延层的底面466。
图4B所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件500与图4A具有相似的结构，除了在图4B中，超级结结构中的P区502主要位于屏蔽栅电极503的下方，但是没有碰触外延层的底面505。
图4C所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件530与图4A具有相似的结构，除了在图4C中，外延层为单外延层结构，仅包括一个N外延层532，其位于N+衬底531上方。与图4A相似，图4C中的超级结结构包括多个交替形成的P区533和N区532，其中，P区533主要位于屏蔽栅电极534下方，并延伸至碰触所述N外延层532的底面536。
图4D所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件560与图4C具有相似的结构，除了在图4D中，超级结结构中的P区562主要位于屏蔽栅电极563的下方，但是没有碰触N外延层566的底面565。
图5A所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件600代表了一个IGBT(Insulating Gate Bipolar Transistor)器件，其与图2A具有相似的结构，除了在图5A中，该IGBT形成于一层P+衬底601之上，并且还包括一层电阻率为Rn的N型缓冲层601’，其位于所述P+衬底601和外延层之间。与图2A相似，图5A中的外延层为双外延层结构，包括电阻率为R1的N1下外延层602和电阻率为R2的N2上外延层603，其中R1>R2>Rn(或者R2>R1>Rn)。图5A中的超级结结构包括多个交替形成的P区604和N区602，其中所述P区604主要位于屏蔽栅电极605的下方，并延伸至碰触外延层的底面607。
图5B所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件630与图5A具有相似的结构，除了在图5B中的IGBT还包括多个N型电荷储存区(N-CS，如图5B所示)631，其形成于N2上外延层632中并位于P型体区633下方，其中所述N型电荷储存区631的多数载流子掺杂浓度大于所述N2上外延层632。
图6A所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件660代表了一个IGBT器件，其与图3A具有相似的结构，除了在图6A中，该IGBT形成于一层P+衬底661之上，并且还包括一层电阻率为Rn的N型缓冲层661’，其位于所述P+衬底661和外延层之间。与图3A相似，图6A中的外延层为双外延层结构，包括电阻率为R1的N1下外延层662和电阻率为R2的N2上外延层663，其中R1>R2>Rn(或者R2>R1>Rn)。图6A中的超级结结构包括多个交替形成的P区664和N区662，其中所述P区664主要位于屏蔽栅电极665的下方，并延伸至碰触外延层的底面667。
图6B所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件700与图6A具有相似的结构，除了在图6B中的IGBT还包括多个N型电荷储存区(N-CS，如图6B所示)701，其形成于N2上外延层702中并位于P型体区703下方，其中所述N型电荷储存区701的多数载流子掺杂浓度大于所述N2上外延层702。
图7A所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件730代表了一个IGBT器件，其与图4A具有相似的结构，除了在图7A中，该IGBT形成于一层P+衬底731之上，并且还包括一层电阻率为Rn的N型缓冲层731’，其位于所述P+衬底731和外延层之间。与图4A相似，图7A中的外延层为双外延层结构，包括电阻率为R1的N1下外延层732和电阻率为R2的N2上外延层733，其中R1>R2>Rn(或者R2>R1>Rn)。图7A中的超级结结构包括多个交替形成的P区734和N区732，其中所述P区734主要位于屏蔽栅电极735的下方，并延伸至碰触外延层的底面737。
图7B所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件760与图7A具有相似的结构，除了在图7B中的IGBT还包括多个N型电荷储存区(N-CS，如图7B所示)761，其形成于N2上外延层762中并位于P型体区763下方，其中所述N型电荷储存区761的多数载流子掺杂浓度大于所述N2上外延层762。
图8所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件800与图5A具有相似的结构，除了图8中的IGBT还包括多个位于P+衬底802中的重掺杂N+区801，以构成包括多个交替形成的P+区802和N+区801的集成反向导通二极管。
图9所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件830与图6A具有相似的结构，除了图9中的IGBT还包括多个位于P+衬底832中的重掺杂N+区831，以构成包括多个交替形成的P+区832和N+区831的集成反向导通二极管。
图10所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件860与图7A具有相似的结构，除了图10中的IGBT还包括多个位于P+衬底862中的重掺杂N+区861，以构成包括多个交替形成的P+区862和N+区861的集成反向导通二极管。
图11所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件900与图8具有相似的结构，不同的是，图8中的IGBT具有双外延层结构，而图11中的IGBT具有单外延层结构，其电阻率为R的N外延层903形成于P+衬底901之上，其中所述P+衬底901中包括多个N+区902，以构成包括多个交替形成的N+区902和P+区901的集成反向导通二极管。该半导体功率器件900还包括一层电阻率为Rn的N缓冲层904，其位于所述N外延层903和所述P+衬底901之间，其中R>Rn。
图12所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件930与图9具有相似的结构，不同的是，图9中的IGBT具有双外延层结构，而图12中的IGBT具有单外延层结构，其电阻率为R的N外延层933形成于P+衬底931之上，其中所述P+衬底931中包括多个N+区932，以构成包括多个交替形成的N+区932和P+区931的集成反向导通二极管。该半导体功率器件930还包括一层电阻率为Rn的N缓冲层934，其位于所述N外延层933和所述P+衬底931之间，其中R>Rn。
图13所示的是根据本发明的另一个优选的实施例，其中N沟道的半导体功率器件960与图10具有相似的结构，不同的是，图10中的IGBT具有双外延层结构，而图13中的IGBT具有单外延层结构，其电阻率为R的N外延层963形成于P+衬底961之上，其中所述P+衬底961中包括多个N+区962，以构成包括多个交替形成的N+区962和P+区961的集成反向导通二极管。该半导体功率器件960还包括一层电阻率为Rn的N缓冲层964，其位于所述N外延层963和所述P+衬底961之间，其中R>Rn。
尽管在此说明了各种实施例，可以理解，在不脱离本发明的精神和范围的所附权利要求书的范围内，通过所述的指导，可以对本发明作出各种修改。例如，可以用本发明的方法形成其导电类型与文中所描述的相反的导电类型的各种半导体区域的结构。

Claims (17)

1.一种半导体功率器件，包括一个SGT MOSFET，其形成于第一导电类型的外延层中并位于一层衬底上方，其特征在于，还包括：
多个沟槽栅，周围围绕有第一导电类型的源区、第二导电类型的体区和所述外延层，其中所述源区和体区靠近所述外延层的上表面且所述源区位于所述体区的上方，每个所述沟槽栅中包括一个栅电极和一个屏蔽栅电极；
氧化层电荷平衡区，形成于每两个相邻的沟槽栅之间；
超级结结构，形成于所述衬底上方且位于所述氧化层电荷平衡区下方，包括多个交替形成的P区和N区；
所述屏蔽栅电极与所述外延层之间通过第一绝缘层相互绝缘，所述栅电极与所述外延层之间通过第二绝缘层相互绝缘，所述第二绝缘层的厚度小于所述第一绝缘层的厚度，且所述屏蔽栅电极和所述栅电极之间相互绝缘；并且
所述体区、所述屏蔽栅电极和所述源区通过多个沟槽式接触区短接至源极金属层。
2.根据权利要求1所述的半导体功率器件，其中所述衬底为第一导电类型，所述外延层为具有均匀掺杂浓度的单外延层结构。
3.根据权利要求1所述的半导体功率器件，其中所述衬底为第一导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，其中R1>R2。
4.根据权利要求1所述的半导体功率器件，其中所述衬底为第一导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，其中R1<R2。
5.根据权利要求1所述的半导体功率器件，其中所述衬底为第二导电类型，所述外延层为具有均匀掺杂浓度的单外延层结构，其电阻率为R，所述半导体功率器件还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R>Rn。
6.根据权利要求1所述的半导体功率器件，其中所述衬底为第二导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，所述半导体功率器件还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R1>R2>Rn。
7.根据权利要求1所述的半导体功率器件，其中所述衬底为第二导电类型，所述外延层为双外延层结构，包括电阻率为R1的下外延层和电阻率为R2的上外延层，所述半导体功率器件还包括第一导电类型的缓冲层，其电阻率为Rn且位于所述衬底和所述外延层之间，其中R2>R1>Rn。
8.根据权利要求1所述的半导体功率器件，其中所述超级结结构中的P区主要位于所述屏蔽栅电极下方且延伸至碰触所述外延层的底面。
9.根据权利要求1所述的半导体功率器件，其中所述超级结结构中的P区主要位于所述屏蔽栅电极下方且不碰触所述外延层的底面。
10.根据权利要求1所述的半导体功率器件，其中所述屏蔽栅电极位于所述沟槽栅的下部分，且与所述外延层之间通过所述第一绝缘层相互绝缘，所述栅电极位于所述沟槽栅的上部分，且与所述屏蔽栅电极之间通过第三绝缘层相互绝缘。
11.根据权利要求10所述的半导体功率器件，其中所述第一绝缘层为具有均匀厚度的单氧化层。
12.根据权利要求10所述的半导体功率器件，其中所述第一绝缘层为多台阶氧化层结构，且其沿所述沟槽栅底部的厚度最大。
13.根据权利要求1所述的半导体功率器件，其中所述屏蔽栅电极位于所述沟槽栅的中央，所述栅电极围绕所述屏蔽栅电极的上部分，并且所述栅电极和所述屏蔽栅电极之间通过所述第二绝缘层相互绝缘。
14.根据权利要求1所述的半导体功率器件，其中所述衬底为所述第二导电类型，还包括：
第一导电类型的缓冲层，位于所述衬底和所述外延层之间；
多个第一导电类型的重掺杂区，位于所述衬底中，形成衬底中的多个交替形成的P+区和N+区。
15.根据权利要求1所述的半导体功率器件，还包括第一导电类型的电荷储存区，其位于所述外延层中并位于所述体区下方，其中所述电荷储存区的多数载流子掺杂浓度大于所述外延层。
16.根据权利要求1所述的半导体功率器件，其中所述第一导电类型为N型，所述第二导电类型为P型。
17.根据权利要求1所述的半导体功率器件，其中所述第一导电类型为P型，所述第二导电类型为N型。
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