TWI769357B - 新型超級結mosfet結構 - Google Patents
新型超級結mosfet結構 Download PDFInfo
- Publication number
- TWI769357B TWI769357B TW107146857A TW107146857A TWI769357B TW I769357 B TWI769357 B TW I769357B TW 107146857 A TW107146857 A TW 107146857A TW 107146857 A TW107146857 A TW 107146857A TW I769357 B TWI769357 B TW I769357B
- Authority
- TW
- Taiwan
- Prior art keywords
- region
- doped
- conductivity type
- trenches
- oxide
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 230000005669 field effect Effects 0.000 claims abstract description 29
- 239000003989 dielectric material Substances 0.000 claims description 25
- 210000000746 body region Anatomy 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 18
- 230000015556 catabolic process Effects 0.000 description 17
- 239000002019 doping agent Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
Abstract
本發明是一種溝槽金屬-氧化物-半導體場效應電晶體(MOSFET)元件,包括屏蔽溝槽閘極結構和超級結結構的組合,在含有漂流區中交替的n-摻雜和p-摻雜立柱的外延層內。在一個示例中,閘極溝槽形成在n-摻雜立柱中和n-摻雜立柱上方,n-摻雜立柱在相應的閘極溝槽底部附近和周圍具有一個多餘的電荷區域。由於閘極溝槽中的屏蔽電極,多餘的電荷是平衡的。
Description
本發明主要有關於金屬-氧化物-半導體場效應電晶體(MOMSFET),更確切地說是一種改良的超級結元件及其製備方法。
微處理器和儲存元件等整合電路含有多個金屬-氧化物-半導體場效應電晶體(MOSFET),提供基本的開關功能,以配置邏輯門、數據儲存和功率開關等功能。功率MOSFET通常用於需要功率切換和功率放大的應用中。在一個功率MOSFET中,必須降低傳導時的元件電阻(Rds-on),並且提高其擊穿電壓(BV)。在一個電晶體中,大多數的擊穿電壓(BV)由漂流區承載,漂流區輕摻雜,以便提供較高的擊穿電壓BV。然而,輕摻雜的漂流區也會產生很高的導通電阻(Rds-on)。換言之,導通電阻(Rds-on)和擊穿電壓(BV)相互競爭博弈。事實上,導通電阻Rds-on正比於BV2.5。也就是說,對於傳統的電晶體來說,導通電阻(Rds-on)隨著擊穿電壓(BV)的增大而急劇增大。
超級結元件結構實現了獲得低導通電阻(Rds-on),同時保持很高的斷開狀態擊穿電壓(BV)的方法。超級結元件包括交替的p-型和n-型摻雜立柱,平行排布,在漂流區中相互連接起來。交替的p-型和n-型立柱在本質上是電荷平衡的。當汲極和源極之間加載反向偏壓時,這些立柱相互耗盡(即水平地)在一個相對低的電壓下,從而在垂直方向上承受很高的擊穿電壓。用於超級結元件的導通電阻(Rds-on)與擊穿電壓BV成正比地增大,比傳統的半導體結構中
增大得劇烈。因此,對於同樣高的擊穿電壓(BV),超級結元件可以比傳統的MOSFET元件的導通電阻(Rds-on)更低(或者說對於指定的導通電阻Rds-on,超級結元件比傳統的MOSFET的擊穿電壓BV更高)。
屏蔽柵溝槽(SGT)MOSFET是另一種類型的功率MOS元件。由於它們具有很低的電晶體閘極至汲極電容Cgd、很低的導通電阻Rds-on以及很高的擊穿電壓BV等優勢,因此它們比傳統的MOSFET更加適合某些特殊應用。
正是在這樣的背景下,提出了本發明的實施例。
本發明為解決上述已有技術當中存在的問題,提供以下技術特徵來實現。
一種金屬-氧化物-半導體場效應電晶體元件,包含:一個第一導電類型的漂流區,位於相同導電類型的重摻雜基板上方;一個第二導電類型的本體區,位於漂流區上方,第二導電類型與第一導電類型相反;多個溝槽,位於本體區中,並延伸到漂流區內;一個第一導電類型的重摻雜源極區,位於本體區中;以及一個超級結結構,位於漂流區中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中第二摻雜立柱的每個立柱都位於兩個相鄰的溝槽之間,其中第一摻雜立柱的每個立柱都有一個多餘的電荷濃度區,在多個溝槽中相應的一個溝槽附近和周圍,其中交替的第一摻雜立柱和第二摻雜立柱都在漂流區中處於基本的電荷平衡;其中多個溝槽中的每個溝槽都內襯電介質材料,每個溝槽的頂部都有一個閘極電極,底部都有一個屏蔽電極。
較佳地,其中多個溝槽中的每個溝槽的中心都在第一摻雜立柱的頂部,並且在兩個相鄰的第二摻雜立柱之間。
較佳地,其中多個溝槽的每個溝槽都具有一個底部,端接在多餘的電荷濃度區。
較佳地,其中多個溝槽的每個溝槽寬度都不大於相應的第一摻雜立柱的寬度。
較佳地,其中第一摻雜立柱具有在漂流區上變化的摻雜結構,其中底部區域上方和多餘的電荷濃度區域下方的區域,具有比底部區域中淨電荷濃度更低的淨電荷濃度。
較佳地,其中與第一摻雜立柱中的其他區域相比,相應的溝槽底部附近和周圍的多餘的電荷濃度區具有最大的摻雜濃度。
較佳地,其中多個溝槽中的每個溝槽都內襯電介質材料,每個溝槽的頂部都有一個閘極電極,並且電介質材料填充多個溝槽中每個溝槽的底部。
較佳地,其中多餘的電荷區域具有比第一摻雜立柱的其他部分高20%至50%的電荷濃度。
較佳地,其中閘極溝槽的寬度與超級結間距的比值約為0.175。
一種金屬-氧化物-半導體場效應電晶體元件,包括:一個第一導電類型的漂流區,位於相同導電類型的重摻雜基板上方;一個第二導電類型的本體區,位於漂流區上方,第二導電類型與第一導電類型相反;多個溝槽,位於本體區中,並延伸到漂流區內;一個第一導電類型的重摻雜源極區,位於本體區中;以及一個超級結結構,位於漂流區中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中第二摻雜立柱
的每個立柱都位於兩個相鄰的溝槽之間,其中第一摻雜立柱和第二摻雜立柱中的每個立柱在溝槽底部下方延伸,其中交替的第一摻雜立柱和第二摻雜立柱都在漂流區中處於基本的電荷平衡;其中多個溝槽中的每個溝槽都內襯電介質材料,每個溝槽的頂部都有一個閘極電極,底部都有一個屏蔽電極。
較佳地,其中多個溝槽的每個溝槽中心都在第一摻雜立柱上方,以及兩個相鄰的第二摻雜立柱之間。
較佳地,其中多個溝槽中的每個溝槽都有一個底部,端接在相應的一個摻雜立柱的頂部。
較佳地,其中多個溝槽中的每個溝槽寬度都小於第一摻雜立柱中相應的摻雜立柱的寬度。
較佳地,其中第一摻雜立柱在漂流區上具有變化的摻雜結構,其中底部區域上方和頂部區域下方的區域具有比底部區域中淨電荷濃度更低的淨電荷濃度。
較佳地,其中與第一摻雜立柱中的其他區域相比,相應的溝槽的底部附近和周圍的第一摻雜立柱的頂部區域具有最大的淨電荷摻雜濃度。
較佳地,其中內襯電介質材料的多個溝槽中的每個溝槽都在頂部具有一個閘極電極,在底部具有一個屏蔽電極。
較佳地,其中內襯電介質材料的多個溝槽中的每個溝槽都在頂部具有一個閘極電極,以及電介質材料填充多個溝槽中每個溝槽的底部。
一種超級結半導體元件,包括:一個第一導電類型的漂流區,位於相同導電類型的重摻雜基板上方;一個第二導電類型的本體區,位於漂流區上方,第二導電類型與第一導電類型相反;以及一個超級結結構,位於漂流區
中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中第一摻雜立柱在漂流區上具有不同的摻雜結構,其中底部區域上方和上部區域下方的中間區域具有的淨電荷濃度,低於底部區域和上部區域中淨電荷濃度,其中交替的第一摻雜立柱和第二摻雜立柱都在漂流區中處於基本的電荷平衡;其中多個溝槽中的每個溝槽都內襯電介質材料,每個溝槽的頂部都有一個閘極電極,底部都有一個屏蔽電極。
較佳地,其中第一摻雜立柱中每個立柱的底部區域、中間區域和上部區域都包括多個摻雜第一導電類型的外延層。
較佳地,其中摻雜第一導電類型的中間區域中多個外延層的每個外延層的劑量,都低於底部區域和上部區域中每個外延層的劑量。
較佳地,其中第一摻雜立柱中的每個摻雜立柱都包括一個在上部區域上方的頂部區域。
較佳地,其中第一摻雜立柱的每個摻雜立柱的底部區域、中間區域、上部區域和頂部區域都包括摻雜第一導電類型的多個外延層,其中摻雜頂部區域中第一導電類型的多個外延層的每個外延層的劑量,高於底部區域、中間區域和上部區域中每個外延層的劑量。
較佳地,其中第一摻雜立柱的每個立柱還包括一個在上部區域之上的頂部區域,其中摻雜頂部區域中第一導電類型的多個外延層的每個外延層劑量,都高於底部區域、中間區域和上部區域中每個外延層的劑量。
一種超級結半導體元件,包括:一個漂流區,由一個位於漂流區中的超級結結構構成,包括交替的第一導電類型的第一摻雜立柱和平行排布的第二導電類型的第二摻雜立柱,其中第一摻雜立柱包括摻雜第一導電類型的多
個外延層,在漂流區上具有變化的摻雜結構,其中底部區域上方和上部區域下方的中間區域中每個外延層的劑量,低於底部區域和上部區域中每個外延層的劑量,其中交替的第一摻雜立柱和第二摻雜立柱都在漂流區中處於基本的電荷平衡;其中多個溝槽中的每個溝槽都內襯電介質材料,每個溝槽的頂部都有一個閘極電極,底部都有一個屏蔽電極。
依據本發明的各個方面,與傳統的超級結元件相比,在超級結元件中增加SGT結構可以降低15%左右的導通電阻Rds-on。
102:基板
103:緩衝層
104:漂流區
105:汲極接頭
106:本體區
108:源極區
110、110’:閘極溝槽
112a:閘極電極
112a’:平面閘極
112b:屏蔽電極
114:電介質材料
114’:閘極氧化物
114”:閘極電介質層
116:絕緣層
118:源極金屬
120:立柱
D1、D2、D3、D4:濃度
R1、R2、R3、R4:區域
第1圖表示依據本發明的各個方面,一個超級結元件的有源晶胞部分的剖面圖。
第2圖表示依據本發明的各個方面,用於超級結元件漂流區的摻雜結構的剖面圖。
第3圖表示依據本發明的各個方面,用於屏蔽柵溝槽(SGT)超級結元件的漂流區的摻雜結構的部分剖面圖。
第4圖表示依據本發明的各個方面,一種SGT超級結元件配置示例的剖面圖。
第5圖表示依據本發明的各個方面,一種超級結元件的配置示例的剖面圖。
第6圖表示依據本發明的各個方面,另一種可選配置的平面柵超級結元件的剖面圖。
在以下詳細說明中,參照圖式,該圖式形成了本發明的一部分,並且在其中表示出了可以實施本發明的圖示特定實施例的方式。為方便起見,在特定的導電或淨雜質載流子類型(p或p)之後使用+或-,通常指的是半導體材
料中指定類型的淨雜質載流子的相對濃度。一般而言,n+材料具有比n材料更高的n型淨摻雜物(例如,電子)濃度,並且n材料具有比n材料更高的載流子濃度。與之類似,p+材料具有比p材料更高的p型淨摻雜物(例如空穴)濃度,並且p材料具有比p材料更高的濃度。要注意的是,相關的是載流子的淨濃度,而不一定是摻雜物。例如,材料可以重摻雜n-型摻雜物,但是如果材料也充分反向摻雜p-型摻雜物,那麼仍然具有相對低的淨載流子濃度。此處所用的摻雜物濃度小於1016/cm3可以認為是“輕摻雜”,摻雜物濃度大於1017/cm3可以認為是“重摻雜”。
為了盡可能地降低導通電阻Rds-on,本發明的各個方面提出了一種功率MOSFET的改良結構,在超級結元件中引入了一個屏蔽柵溝槽(SGT)結構。確切地說,SGT結構中的屏蔽電極提供了一種除了超級結結構之外額外的電荷平衡結構。這使得n立柱中的摻雜濃度較高,從而降低導通電阻Rds-on。
第1圖表示依據本發明的各個方面,超級結元件的有源晶胞的一部分的剖面圖。元件的有源晶胞包括一個適當摻雜(例如n+)的基板102,作為帶有汲極接頭105的汲極區,以及一個適當摻雜(例如n漂流)的漂流區104,位於基板102上方。結合下文所述的超級結較高,n漂流區104部分可以用作n立柱,在n漂流區104的頂面和基板102之間,具有變化的(即非均勻的)摻雜結構。元件還包括一個p-型本體區106、一個n+源極區108,形成在p本體區106中,以及一個內襯電介質材料114的閘極溝槽110。閘極溝槽110具有一個閘極電極112a和一個屏蔽電極112b。閘極電極112a位於閘極溝槽110的頂部,屏蔽電極112b位於閘極溝槽110的底部。如第1圖所示,沿著閘極溝槽底部的內表面的電介質材料114,比沿著溝槽頂部的內表面的電介質材料更厚。閘極溝槽110底部中較厚的那部分電介質材料114使屏蔽電極112b和漂流區104絕緣,閘極溝槽110頂部中較
薄的那部分電介質材料114使閘極電極112a與本體區106絕緣。閘極電極112a的底部延伸到本體區106的底部下方。要注意的是,屏蔽電極112b也與閘極電極112a絕緣,並且使閘極電極112a與漂流區104中的電場絕緣。還可選擇,用氧化物等電介質材料代替屏蔽電極112b。
元件還包括一個絕緣層116,形成在閘極溝槽110上,一個閘極電極(圖中沒有表示出)以及一個源極金屬118,形成在絕緣層116上並且連接到源極區108。
元件包括一個超級結結構,具有交替的p摻雜立柱和n摻雜立柱。如第1圖所示,p立柱120形成在漂流區104中兩個相鄰的閘極溝槽110之間,從本體區106的底部開始穿過屏蔽電極112b的整個深度,延伸到比閘極溝槽110底部更深的深處。在一個較佳實施例中,p立柱120的總深度至少是屏蔽電極112b深度的三倍。N立柱可以由n漂流區104的一部分構成,n漂流區104的一部分位於p立柱120附近。P立柱120可以觸及基板102或基板102上方的端接結構。在第2圖所示的一個可選實施例中,輕n型摻雜的緩衝層103位於基板102和n漂流區104之間,將p立柱120和基板102隔開。如第1圖和第2圖所示,p立柱120和n立柱由n漂流區104構成,實現了操作中的電荷平衡。利用閘極溝槽110中的屏蔽電極112b,n漂流區104在相鄰的p立柱120之間的頂部被閘極溝槽110的底部佔據。因此,n立柱中的n電荷濃度必須增大,以補償屏蔽電極的存在,保持漂流區中的電荷平衡。在這種情況下,n立柱具有多餘的n電荷濃度區,形成在閘極溝槽110的底部附近和周圍。為了增大n電荷濃度,n立柱中的摻雜濃度(尤其是在閘極溝槽110的底部附近和周圍)增大。因此,導通電阻Rds-on進一步降低。
要注意的是,半導體基板102、漂流區104和源極區108都是相同的導電類型(例如n-型)。本體區106和摻雜立柱120的導電類型都與基板102的導電類型相反(例如p-型)。
在一個實施例中,n和p立柱都用傳統的工藝製備(例如製備多個外延矽層,然後在通過熱激活形成立柱之前,注入一個或兩個摻雜物)。n和p立柱可以在漂流區上具有不同的摻雜結構。第3圖表示依據本發明的各個方面,用於超級結元件的n立柱的激活淨摻雜物結構。n和p立柱從上到下可以分成四個區域R1、R2、R3、R4。n和p立柱的每四個區域都包括一個或多個外延層,每個層的特點是都有一個p注入擴散物的裂片在每個外延層中。在每四個區域R1、R2、R3、R4中的n立柱都分別有淨電荷濃度D1、D2、D3、D4。如第3圖所示,閘極溝槽110在R4區域內端接。n立柱在頂部區域R4中(即p本體區106附近)的摻雜濃度D4比n立柱在基板102附近的區域R1的摻雜濃度D1更高。與n漂流區104中的其他區域相比,形成在閘極溝槽110附近和周圍的多餘的n電荷區具有最大的n-型摻雜濃度,因此有最大的淨電荷濃度。作為示例,但不作為局限,對於漂流區104的頂部來說,多餘的n電荷區可以通過提高注入劑量而形成。在一個實施例中,屏蔽電極112b附近的多餘的n電荷區比傳統的超級結元件多20-50%的電荷,n立柱具有的頂部淨電荷濃度,不少於底部的淨電荷濃度。在第3圖所示的一個較佳實施例中,頂部區域R4中的n立柱具有的電荷濃度D4比底部區域R1中的n立柱電荷濃度D1高20-50%。在另一個實施例中,靠近頂部區域R4的區域R3中的n立柱具有的電荷濃度D3,與底部區域R1中的n立柱電荷濃度D1基本相同,但是比頂部區域R4中的n立柱電荷濃度D4要小。在另一個實施例中,頂部區域R4下方的每個區域R1、R2、R3中的n立柱的電荷濃度D1、D2、D3都與頂部區域
R4中的n立柱電荷濃度D4基本相同,但比濃度D4更小。在另一個實施例中,底部區域R1上方的區域R2中的n立柱的電荷濃度D2,小於底部區域R1中n立柱的電荷濃度D1。在另一個實施例中,頂部區域R4附近的區域R3中的n立柱電荷濃度D3與底部區域R1中的n立柱電荷濃度D1基本相同,但高於底部區域R1上方的區域R2中的n立柱電荷濃度D2,小於頂部區域R4中的n立柱電荷濃度D4。底部區域R1正上方的區域R2中較低的摻雜濃度,有利於增大擊穿電壓,在傳統的超級結元件中傳統的摻雜等級體系往往造成擊穿電壓的降低。這種傳統的摻雜等級犧牲了峰值擊穿電壓,對p和n立柱中的電荷失配具有較大的容忍度,從而使製造商可以輕鬆地降低電荷注入控制的精度,增大了元件性能的不均勻性。在一些實施例中,區域R2中的n立柱電荷濃度D2可以低至區域R2上方區域R3中n立柱電荷濃度D3以及區域R2下方的底部區域R1中n立柱電荷濃度D1的60%。
第4圖表示依據本發明的各個方面,用於超級結元件的n立柱和p立柱的激活淨摻雜物結構。n和p立柱都可以從上到下分成四個區域R1、R2、R3、R4。n和p立柱的每四個區域都可以包括一個或多個外延層,每個層的特點是都有一個p注入擴散物的裂片在每個外延層中。在第4圖所示的實施例中,頂部區域R4包括兩個外延層Ln和Ln-1,但是卻含有更多或更少的外延層。每個閘極溝槽110都在區域R4內端接。靠近頂部區域R4的區域R3包括一個外延層Ln-3,但是可以包括多個外延層。底部區域R1包括一個外延層L1,但是包括多個外延層。在底部區域R1上方附近的區域R2包括兩個或多個外延層L2到Ln-3。四個區域R1、R2、R3、R4中每個外延層裡的n立柱都分別有一個淨電荷劑量Qn1、Qn2、Qn3和Qn4。四個區域R1、R2、R3、R4的外延層裡的p立柱分別具有淨電荷劑量Qp1、Qp2、Qp3和Qp4。為了獲得穩定的高擊穿電壓,Qn2最好與Qp2基本相等,
使得區域R2中每個外延層裡的n和p立柱中的電荷平衡,同時與n立柱相比,頂部區域中的p立柱具有多餘的電荷,與p立柱相比,底部區域中的n立柱具有多餘的電荷。
在第4圖所示的配置中,Qn4大於Qp4,Qn3小於Qp3。在該配置中的一個較佳實施例中,Qn4比Qp4大30%至70%,Qn3比Qp3小4%至8%。在另一個實施例中,Qn4大於Qp4,Qn1大於Qp1。在另一個實施例中,Qn4大於Qp4,Qn3小於Qp3,並且Qn1大於Qp1。
對於上述第3圖和第4圖所示的配置中,對於不同的區域,每個外延層中n立柱的劑量都可以變化。在一個較佳實施例中,n立柱在頂部區域R4中每個外延層裡的劑量Qn4,大於n立柱在底部區域R1中每個外延層裡的劑量Qn1。在另一個實施例中,n立柱在頂部區域R4附近的區域R3中的n立柱在每個外延層中具有劑量Qn3,與底部區域R1中每個外延層裡的n立柱劑量Qn1基本相等。在另一個實施例中,頂部區域R4附近的區域R3中n立柱在每個外延層中具有劑量Qn3,與底部區域R1中每個外延層裡的n立柱劑量Qn1基本相等,但小於頂部區域R4中每個外延層裡的n立柱劑量Qn4。在另一個實施例中,在頂部區域R4下方的每個區域R1、R2、R3的每個外延層中n立柱劑量Qn1、Qn2和Qn3,與頂部區域R4中每個外延層裡的n立柱劑量Qn4基本相等,但小於Qn4。在另一個實施例中,底部區域R1上方的區域R2中n立柱在每個外延層中具有劑量Qn2,小於底部區域R1中每個外延層裡的n立柱劑量Qn1。在另一個實施例中,頂部區域R4附近的區域R3中每個外延層裡的n立柱劑量Qn3,與底部區域R1中每個外延層裡的n立柱劑量Qn1基本相等,但大於底部區域R1上方的區域R2中每個外延層裡的n立柱劑量Qn2,小於頂部區域R4中每個外延層裡的n立柱劑量Qn4。底部區域R1
正上方的區域R2中較低的摻雜物濃度,有利於增大擊穿電壓,在傳統的超級結元件中傳統的摻雜等級體系往往造成擊穿電壓的降低。這種傳統的摻雜等級犧牲了峰值擊穿電壓,對p和n立柱中的電荷失配具有較大的容忍度,從而使製造商可以輕鬆地降低電荷注入控制的精度,增大了元件性能的不均勻性。在一些實施例中,區域R2中的n立柱電荷濃度Qn2可以低至區域R2上方區域R3中n立柱電荷濃度Qn3以及區域R2下方的底部區域R1中n立柱電荷濃度Qn1的60%。在所有的實施例中,Qn4可以比Qn1高70%。還可選擇,調節p立柱中的劑量,使得頂部區域R4下方的每個區域R1、R2、R3的每個外延層中p立柱劑量Qp1、Qp2和Qp3,與頂部區域R4中每個外延層裡的p立柱劑量Qp4基本相等,或者頂部區域R4附近的區域R3中每個外延層裡的p立柱劑量Qp3,與底部區域R1中每個外延層裡的p立柱劑量Qp1基本相等,但大於底部區域R1上方的區域R2中每個外延層裡p立柱劑量Qp2。依據本發明的各個方面,與傳統的超級結元件相比,在超級結元件中增加SGT結果可以降低15%的導通電阻Rds-on。為了補償屏蔽電極112b的存在,獲得增大n電荷的良好效果,可以在n立柱上方和內部(即n漂流區104)形成閘極溝槽110,屏蔽電極的底部應比多餘的n電荷區更淺。閘極溝槽110不能比n立柱更寬。作為示例,但不作為局限,閘極溝槽的寬度與超級結間距之比約為0.175。在一個實施例中,對於5-6微米深度的溝槽來說,溝槽的寬度為0.9微米。另外,為了保持漂流區中的電荷平衡,閘極溝槽110的中心應在n-立柱中,以及兩個相鄰的p立柱之間。如果閘極溝槽110偏離中心,會導致電荷平衡受損。作為示例,但不作為局限,對於具有8微米間距的超級結結構中的溝槽寬度1.4微米來說,不對準容差約為0.1至0.2微米。還可選擇,調節漂流區104中的n電荷,補償可能的不對準。
第5圖表示一種超級結元件的可選配置,在這種元件中溝槽的不對準效果可以降低。第5圖所示的元件與第4圖所示的元件基本相同,除了閘極溝槽110’比閘極溝槽110淺得多之外,以便於只有閘極電極112a形成在閘極溝槽110’中。閘極氧化物114’在閘極溝槽110’的底部較厚。由於閘極溝槽110’很淺,所以頂部區域R4只包括一個外延層Ln。閘極溝槽110’在頂部區域R4中端接。靠近頂部區域R4的區域R3包括一個外延層Ln-1,但是可以包括更多的外延層。底部區域R1包括兩個外延層L1和L2,但可以包括更少或更多的外延層。除了降低Qn4,以便降低濃度D4之外,在底部區域R1上方的區域R2包括兩個或多個外延層L3至Ln-2。P和n立柱中每個外延層的劑量都與第3圖和第4圖所示的劑量類似。在一個較佳實施例中,Qn4比Qp4大10%至30%,Qn3比Qp3小4%至8%。在另一個較佳實施例中,Qn4可以比Qn1大30%以上。
第6圖表示一種帶有平面柵結構的可選配置,其中沒有了溝槽不對準效果。除了平面閘極112a’形成在半導體上方的閘極電介質層114”上,而不是在溝槽內部之外,第6圖所示的元件與第5圖所示的元件相同。由於沒有了溝槽,所以每個p和n立柱的頂部區域R4都省略了。本體區106附近的區域R3包括兩個外延層Ln和Ln-1,但是可以包括更少或更多的外延層。底部區域R1包括兩個外延層L1和L2,但可以包括更少或更多的外延層。底部區域R1上方的中間區域R2包括兩個或多個外延層L3至Ln-2。區域R1、R2、R3中p和n立柱中每個外延層的劑量都與第3圖和第4圖所示的區域R1、R2、R3中p和n立柱中每個外延層相應的劑量接近。
依據本發明的各個方面,與傳統的超級結元件相比,在超級結元件中增加SGT結構可以降低15%左右的導通電阻Rds-on。
儘管本發明的內容已經通過上述較佳實例作了詳細介紹,但應當認識到上述的描述不應被認為是本發明的限制。在本領域技術人員閱讀了上述內容後,對於本發明的多種修改和替代都將是顯而易見的。因此,本發明的保護範圍應由所附的申請專利範圍來限定。
102:基板
104:漂流區
105:汲極接頭
106:本體區
108:源極區
110:閘極溝槽
112a:閘極電極
112b:屏蔽電極
114:電介質材料
116:絕緣層
118:源極金屬
120:立柱
Claims (24)
- 一種金屬-氧化物-半導體場效應電晶體元件,其包含:一個第一導電類型的漂流區,位於相同導電類型的重摻雜基板上方;一個第二導電類型的本體區,位於該漂流區上方,第二導電類型與第一導電類型相反;多個溝槽,位於該本體區中,並延伸到該漂流區內;一個第一導電類型的重摻雜源極區,位於該本體區中;以及一個超級結結構,位於該漂流區中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中該第二摻雜立柱的每個立柱都位於兩個相鄰的該溝槽之間,其中該第一摻雜立柱的每個立柱都有一個多餘的電荷濃度區,在多個該溝槽中相應的一個該溝槽附近和周圍,其中交替的該第一摻雜立柱和該第二摻雜立柱都在該漂流區中處於基本的電荷平衡;其中多個該溝槽中的每個該溝槽都內襯電介質材料,每個該溝槽的頂部都有一個閘極電極,底部都有一個屏蔽電極。
- 如申請專利範圍第1項所述之金屬-氧化物-半導體場效應電晶體元件,其中多個該溝槽中的每個該溝槽的中心都在該第一摻雜立柱的頂部,並且在兩個相鄰的該第二摻雜立柱之間。
- 如申請專利範圍第1項所述之金屬-氧化物-半導體場效應電晶體元件,其中多個該溝槽的每個該溝槽都具有一個底部,端接在多餘的電荷濃度區。
- 如申請專利範圍第1項所述之金屬-氧化物-半導體場效應電晶體元件,其中多個該溝槽的每個該溝槽寬度都不大於相應的該第一摻雜立柱的寬度。
- 如申請專利範圍第1項所述之金屬-氧化物-半導體場效應電晶體元件,其中該第一摻雜立柱具有在該漂流區上變化的摻雜結構,其中底部區域上方和多餘的電荷濃度區域下方的區域,具有比底部區域中淨電荷濃度更低的淨電荷濃度。
- 如申請專利範圍第1項所述之金屬-氧化物-半導體場效應電晶體元件,其中與該第一摻雜立柱中的其他區域相比,相應的該溝槽底部附近和周圍的多餘的電荷濃度區具有最大的摻雜濃度。
- 如申請專利範圍第1項所述之金屬-氧化物-半導體場效應電晶體元件,其中多個該溝槽中的每個該溝槽都內襯電介質材料,每個該溝槽的頂部都有一個閘極電極,並且電介質材料填充多個該溝槽中每個該溝槽的底部。
- 如申請專利範圍第1項所述之金屬-氧化物-半導體場效應電晶體元件,其中多餘的電荷區域具有比該第一摻雜立柱的其他部分高20%至50%的電荷濃度。
- 如申請專利範圍第1項所述之金屬-氧化物-半導體場效應電晶體元件,其中閘極溝槽的寬度與超級結間距的比值約為0.175。
- 一種金屬-氧化物-半導體場效應電晶體元件,其包括:一個第一導電類型的漂流區,位於相同導電類型的重摻雜基板上方; 一個第二導電類型的本體區,位於該漂流區上方,第二導電類型與第一導電類型相反;多個溝槽,位於該本體區中,並延伸到該漂流區內;一個第一導電類型的重摻雜源極區,位於該本體區中;以及一個超級結結構,位於該漂流區中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中該第二摻雜立柱的每個立柱都位於兩個相鄰的該溝槽之間,其中該第一摻雜立柱和該第二摻雜立柱中的每個立柱在該溝槽底部下方延伸,其中交替的該第一摻雜立柱和該第二摻雜立柱都在該漂流區中處於基本的電荷平衡;其中多個該溝槽中的每個該溝槽都內襯電介質材料,每個該溝槽的頂部都有一個閘極電極,底部都有一個屏蔽電極。
- 如申請專利範圍第10項所述之金屬-氧化物-半導體場效應電晶體元件,其中多個該溝槽的每個該溝槽中心都在該第一摻雜立柱上方,以及兩個相鄰的該第二摻雜立柱之間。
- 如申請專利範圍第11項所述之金屬-氧化物-半導體場效應電晶體元件,其中多個該溝槽中的每個該溝槽都有一個底部,端接在相應的一個摻雜立柱的頂部。
- 如申請專利範圍第10項所述之金屬-氧化物-半導體場效應電晶體元件,其中多個該溝槽中的每個該溝槽寬度都小於該第一摻雜立柱中相應的摻雜立柱的寬度。
- 如申請專利範圍第10項所述之金屬-氧化物-半導體場效應電晶體元件,其中該第一摻雜立柱在該漂流區上具有變化的摻雜結構,其中底部區域上方和頂部區域下方的區域具有比底部 區域中淨電荷濃度更低的淨電荷濃度。
- 如申請專利範圍第10項所述之金屬-氧化物-半導體場效應電晶體元件,其中與該第一摻雜立柱中的其他區域相比,相應的該溝槽的底部附近和周圍的該第一摻雜立柱的頂部區域具有最大的淨電荷摻雜濃度。
- 如申請專利範圍第10項所述之金屬-氧化物-半導體場效應電晶體元件,其中內襯電介質材料的多個該溝槽中的每個該溝槽都在頂部具有一個閘極電極,在底部具有一個屏蔽電極。
- 如申請專利範圍第10項所述之金屬-氧化物-半導體場效應電晶體元件,其中內襯電介質材料的多個該溝槽中的每個該溝槽都在頂部具有一個閘極電極,以及電介質材料填充多個該溝槽中每個該溝槽的底部。
- 一種金屬-氧化物-半導體場效應電晶體元件,其包括:一個第一導電類型的漂流區,位於相同導電類型的重摻雜基板上方;一個第二導電類型的本體區,位於該漂流區上方,第二導電類型與第一導電類型相反;以及一個超級結結構,位於該漂流區中,包括交替的第一導電類型的第一摻雜立柱以及平行排布的第二導電類型的第二摻雜立柱,其中該第一摻雜立柱在該漂流區上具有不同的摻雜結構,其中底部區域上方和上部區域下方的中間區域具有的淨電荷濃度,低於底部區域和上部區域中淨電荷濃度,其中交替的該第一摻雜立柱和該第二摻雜立柱都在該漂流區中處於基本的電荷平衡; 其中多個該溝槽中的每個該溝槽都內襯電介質材料,每個該溝槽的頂部都有一個閘極電極,底部都有一個屏蔽電極。
- 如申請專利範圍第18項所述之金屬-氧化物-半導體場效應電晶體元件,其中該第一摻雜立柱中每個立柱的底部區域、中間區域和上部區域都包括多個摻雜第一導電類型的外延層。
- 如申請專利範圍第19項所述之金屬-氧化物-半導體場效應電晶體元件,其中摻雜第一導電類型的中間區域中多個外延層的每個外延層的劑量,都低於底部區域和上部區域中每個外延層的劑量。
- 如申請專利範圍第18項所述之金屬-氧化物-半導體場效應電晶體元件,其中該第一摻雜立柱中的每個摻雜立柱都包括一個在上部區域上方的頂部區域。
- 如申請專利範圍第21項所述之金屬-氧化物-半導體場效應電晶體元件,其中該第一摻雜立柱的每個摻雜立柱的底部區域、中間區域、上部區域和頂部區域都包括摻雜第一導電類型的多個外延層,其中摻雜頂部區域中第一導電類型的多個外延層的每個外延層的劑量,高於底部區域、中間區域和上部區域中每個外延層的劑量。
- 如申請專利範圍第18項所述之金屬-氧化物-半導體場效應電晶體元件,其中該第一摻雜立柱的每個立柱還包括一個在上部區域之上的頂部區域,其中摻雜頂部區域中第一導電類型的多個外延層的每個外延層劑量,都高於底部區域、中間區域和上部區域中每個外延層的劑量。
- 一種金屬-氧化物-半導體場效應電晶體元件,其包括: 一個漂流區,由一個位於該漂流區中的超級結結構構成,包括交替的第一導電類型的第一摻雜立柱和平行排布的第二導電類型的第二摻雜立柱,其中該第一摻雜立柱包括摻雜第一導電類型的多個外延層,在該漂流區上具有變化的摻雜結構,其中底部區域上方和上部區域下方的中間區域中每個外延層的劑量,低於底部區域和上部區域中每個外延層的劑量,其中交替的該第一摻雜立柱和該第二摻雜立柱都在該漂流區中處於基本的電荷平衡;其中多個該溝槽中的每個該溝槽都內襯電介質材料,每個該溝槽的頂部都有一個閘極電極,底部都有一個屏蔽電極。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/856,828 | 2017-12-28 | ||
US15/856,828 US10644102B2 (en) | 2017-12-28 | 2017-12-28 | SGT superjunction MOSFET structure |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201931598A TW201931598A (zh) | 2019-08-01 |
TWI769357B true TWI769357B (zh) | 2022-07-01 |
Family
ID=67059925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107146857A TWI769357B (zh) | 2017-12-28 | 2018-12-24 | 新型超級結mosfet結構 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10644102B2 (zh) |
CN (2) | CN116435371A (zh) |
TW (1) | TWI769357B (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6215510B1 (ja) * | 2016-11-11 | 2017-10-18 | 新電元工業株式会社 | Mosfet及び電力変換回路 |
KR102554248B1 (ko) * | 2019-02-28 | 2023-07-11 | 주식회사 디비하이텍 | 수퍼 정션 반도체 장치 및 이의 제조 방법 |
JP7290973B2 (ja) * | 2019-03-27 | 2023-06-14 | ローム株式会社 | 半導体装置 |
CN111129152B (zh) * | 2019-12-17 | 2023-09-26 | 杭州芯迈半导体技术有限公司 | 沟槽mosfet结构及其制造方法 |
US20220069073A1 (en) * | 2020-08-28 | 2022-03-03 | Nanjing Zizhu Microelectronics Co., Ltd. | Integrated circuit system with super junction transistor mechanism and method of manufacture thereof |
US11462638B2 (en) * | 2020-10-19 | 2022-10-04 | Nami MOS CO., LTD. | SiC super junction trench MOSFET |
US11728423B2 (en) | 2021-04-22 | 2023-08-15 | Alpha And Omega Semiconductor International Lp | Integrated planar-trench gate power MOSFET |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201532281A (zh) * | 2014-02-04 | 2015-08-16 | Alpha & Omega Semiconductor | 半導體基板中的半導體元件及其製備方法 |
TW201704144A (zh) * | 2015-07-30 | 2017-02-01 | 達爾科技股份有限公司 | 多溝槽半導體裝置 |
Family Cites Families (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2089119A (en) | 1980-12-10 | 1982-06-16 | Philips Electronic Associated | High voltage semiconductor devices |
CN1019720B (zh) | 1991-03-19 | 1992-12-30 | 电子科技大学 | 半导体功率器件 |
DE4309764C2 (de) | 1993-03-25 | 1997-01-30 | Siemens Ag | Leistungs-MOSFET |
JP3291957B2 (ja) | 1995-02-17 | 2002-06-17 | 富士電機株式会社 | 縦型トレンチmisfetおよびその製造方法 |
US6097063A (en) | 1996-01-22 | 2000-08-01 | Fuji Electric Co., Ltd. | Semiconductor device having a plurality of parallel drift regions |
US6800903B2 (en) | 1996-11-05 | 2004-10-05 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
JP4765012B2 (ja) | 2000-02-09 | 2011-09-07 | 富士電機株式会社 | 半導体装置及びその製造方法 |
US6509240B2 (en) | 2000-05-15 | 2003-01-21 | International Rectifier Corporation | Angle implant process for cellular deep trench sidewall doping |
US6608350B2 (en) | 2000-12-07 | 2003-08-19 | International Rectifier Corporation | High voltage vertical conduction superjunction semiconductor device |
US6835993B2 (en) | 2002-08-27 | 2004-12-28 | International Rectifier Corporation | Bidirectional shallow trench superjunction device with resurf region |
US6979862B2 (en) | 2003-01-23 | 2005-12-27 | International Rectifier Corporation | Trench MOSFET superjunction structure and method to manufacture |
KR20070038945A (ko) | 2003-12-19 | 2007-04-11 | 써드 디멘존 세미컨덕터, 인코포레이티드 | 수퍼 접합 장치의 제조 방법 |
US7368777B2 (en) * | 2003-12-30 | 2008-05-06 | Fairchild Semiconductor Corporation | Accumulation device with charge balance structure and method of forming the same |
JP4851694B2 (ja) * | 2004-08-24 | 2012-01-11 | 株式会社東芝 | 半導体装置の製造方法 |
US7482220B2 (en) | 2005-02-15 | 2009-01-27 | Semiconductor Components Industries, L.L.C. | Semiconductor device having deep trench charge compensation regions and method |
US7176524B2 (en) | 2005-02-15 | 2007-02-13 | Semiconductor Components Industries, Llc | Semiconductor device having deep trench charge compensation regions and method |
KR101279574B1 (ko) | 2006-11-15 | 2013-06-27 | 페어차일드코리아반도체 주식회사 | 고전압 반도체 소자 및 그 제조 방법 |
DE102006061994B4 (de) * | 2006-12-21 | 2011-05-05 | Infineon Technologies Austria Ag | Ladungskompensationsbauelement mit einer Driftstrecke zwischen zwei Elektroden und Verfahren zur Herstellung desselben |
KR100827524B1 (ko) | 2007-04-06 | 2008-05-06 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US7772668B2 (en) | 2007-12-26 | 2010-08-10 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
US8558275B2 (en) | 2007-12-31 | 2013-10-15 | Alpha And Omega Semiconductor Ltd | Sawtooth electric field drift region structure for power semiconductor devices |
US7960781B2 (en) | 2008-09-08 | 2011-06-14 | Semiconductor Components Industries, Llc | Semiconductor device having vertical charge-compensated structure and sub-surface connecting layer and method |
US7943989B2 (en) | 2008-12-31 | 2011-05-17 | Alpha And Omega Semiconductor Incorporated | Nano-tube MOSFET technology and devices |
US8299494B2 (en) | 2009-06-12 | 2012-10-30 | Alpha & Omega Semiconductor, Inc. | Nanotube semiconductor devices |
US8390058B2 (en) | 2009-06-12 | 2013-03-05 | Aplha and Omega Semiconductor Incorporated | Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions |
TWI445173B (zh) | 2009-06-12 | 2014-07-11 | Alpha & Omega Semiconductor | 半導體裝置及其製備方法 |
US7910486B2 (en) | 2009-06-12 | 2011-03-22 | Alpha & Omega Semiconductor, Inc. | Method for forming nanotube semiconductor devices |
US8324053B2 (en) * | 2009-09-30 | 2012-12-04 | Alpha And Omega Semiconductor, Inc. | High voltage MOSFET diode reverse recovery by minimizing P-body charges |
US8466510B2 (en) | 2009-10-30 | 2013-06-18 | Alpha And Omega Semiconductor Incorporated | Staggered column superjunction |
US8227339B2 (en) | 2009-11-02 | 2012-07-24 | International Business Machines Corporation | Creation of vias and trenches with different depths |
US8575695B2 (en) | 2009-11-30 | 2013-11-05 | Alpha And Omega Semiconductor Incorporated | Lateral super junction device with high substrate-drain breakdown and built-in avalanche clamp diode |
US8373208B2 (en) | 2009-11-30 | 2013-02-12 | Alpha And Omega Semiconductor Incorporated | Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode |
US8067800B2 (en) | 2009-12-28 | 2011-11-29 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFET with resurf step oxide and the method to make the same |
US8476698B2 (en) | 2010-02-19 | 2013-07-02 | Alpha And Omega Semiconductor Incorporated | Corner layout for superjunction device |
US8716116B2 (en) | 2010-03-10 | 2014-05-06 | Micron Technology, Inc. | Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline |
US9431249B2 (en) | 2011-12-01 | 2016-08-30 | Vishay-Siliconix | Edge termination for super junction MOSFET devices |
CN102610643B (zh) * | 2011-12-20 | 2015-01-28 | 成都芯源系统有限公司 | 沟槽金属氧化物半导体场效应晶体管器件 |
US8866221B2 (en) | 2012-07-02 | 2014-10-21 | Infineon Technologies Austria Ag | Super junction semiconductor device comprising a cell area and an edge area |
US10256325B2 (en) | 2012-11-08 | 2019-04-09 | Infineon Technologies Austria Ag | Radiation-hardened power semiconductor devices and methods of forming them |
US9105717B2 (en) * | 2013-12-04 | 2015-08-11 | Infineon Technologies Austria Ag | Manufacturing a semiconductor device using electrochemical etching, semiconductor device and super junction semiconductor device |
JP2015133380A (ja) * | 2014-01-10 | 2015-07-23 | 株式会社東芝 | 半導体装置 |
US9293533B2 (en) | 2014-06-20 | 2016-03-22 | Infineon Technologies Austria Ag | Semiconductor switching devices with different local transconductance |
US9431495B2 (en) | 2014-08-08 | 2016-08-30 | Alpha And Omega Semiconductor Incorporated | Method of forming SGT MOSFETs with improved termination breakdown voltage |
US9171949B1 (en) | 2014-09-24 | 2015-10-27 | Alpha And Omega Semiconductor Incorporated | Semiconductor device including superjunction structure formed using angled implant process |
US9312381B1 (en) | 2015-06-23 | 2016-04-12 | Alpha And Omega Semiconductor Incorporated | Lateral super-junction MOSFET device and termination structure |
US9450045B1 (en) | 2015-06-23 | 2016-09-20 | Alpha And Omega Semiconductor Incorporated | Method for forming lateral super-junction structure |
JP6215510B1 (ja) * | 2016-11-11 | 2017-10-18 | 新電元工業株式会社 | Mosfet及び電力変換回路 |
-
2017
- 2017-12-28 US US15/856,828 patent/US10644102B2/en active Active
-
2018
- 2018-12-24 TW TW107146857A patent/TWI769357B/zh active
- 2018-12-27 CN CN202310467590.8A patent/CN116435371A/zh active Pending
- 2018-12-27 CN CN201811613050.1A patent/CN109980017A/zh active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201532281A (zh) * | 2014-02-04 | 2015-08-16 | Alpha & Omega Semiconductor | 半導體基板中的半導體元件及其製備方法 |
TW201704144A (zh) * | 2015-07-30 | 2017-02-01 | 達爾科技股份有限公司 | 多溝槽半導體裝置 |
Also Published As
Publication number | Publication date |
---|---|
CN116435371A (zh) | 2023-07-14 |
US20190206988A1 (en) | 2019-07-04 |
TW201931598A (zh) | 2019-08-01 |
CN109980017A (zh) | 2019-07-05 |
US10644102B2 (en) | 2020-05-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI769357B (zh) | 新型超級結mosfet結構 | |
US8330213B2 (en) | Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges | |
US7928505B2 (en) | Semiconductor device with vertical trench and lightly doped region | |
US7605423B2 (en) | Semiconductor device | |
TWI453919B (zh) | 用於快速開關的帶有可控注入效率的二極體結構 | |
TWI524521B (zh) | 溝槽底部氧化物屏蔽以及三維p-本體接觸區的奈米金氧半導體場效電晶體 及其製造方法 | |
US9129936B2 (en) | Devices, components and methods combining trench field plates with immobile electrostatic charge | |
US9735254B2 (en) | Trench-gate RESURF semiconductor device and manufacturing method | |
US20100025760A1 (en) | Semiconductor device | |
US9082810B2 (en) | Semiconductor device | |
JP5165995B2 (ja) | 半導体装置及びその製造方法 | |
CN111509049A (zh) | 一种屏蔽栅沟槽式金属氧化物半导体场效应管 | |
US6989567B2 (en) | LDMOS transistor | |
JP2018530922A (ja) | 横方向拡散金属酸化物半導体電界効果トランジスタ | |
US20200119142A1 (en) | Semiconductor device | |
KR101093678B1 (ko) | 전력 반도체 소자 및 그 제조 방법 | |
US10014365B2 (en) | Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges | |
US9018638B2 (en) | MOSFET device | |
US10700172B2 (en) | Semiconductor device and method for fabricating a semiconductor device | |
JP2024009372A (ja) | 超接合半導体装置 | |
CN115425083A (zh) | 具有屏蔽栅沟槽结构的超级结半导体功率器件 | |
KR101130019B1 (ko) | 전력용 반도체 디바이스 |