CN116598205B - 一种沟槽型mosfet器件及其制造方法 - Google Patents

一种沟槽型mosfet器件及其制造方法 Download PDF

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CN116598205B
CN116598205B CN202310875766.3A CN202310875766A CN116598205B CN 116598205 B CN116598205 B CN 116598205B CN 202310875766 A CN202310875766 A CN 202310875766A CN 116598205 B CN116598205 B CN 116598205B
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塞萨尔·龙思万里
李防化
胡舜涛
刘桂新
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Lingrui Semiconductor Shanghai Co ltd
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Abstract

本发明公开了一种沟槽型MOSFET器件制造方法，包括：在衬底上外延形成基层区；在基层区中形成第一沟槽；在第一沟槽内表面形成P型层；在P型层内填充多晶硅；在第一沟槽上方形成第二沟槽；在第二沟槽中形成栅结构。相应公开了一种沟槽型MOSFET器件，包括：衬底、基层区、第一沟槽和第二沟槽；基层区位于衬底上表面，第一沟槽位于第二沟槽正下方，且均设置在基层区内；第一沟槽的内表面形成有P型层，P型层中填充有多晶硅。利用超结概念获得更小的开通电阻，采用分离型沟槽多晶硅技术减少了栅极到漏极的米勒电容，可制造出结构紧凑、原胞密度大和电流密度大的沟槽型MOSFET器件，可显著的提高器件的功率密度，降低成本，提高产品的可靠性。

Description

一种沟槽型MOSFET器件及其制造方法
技术领域
本发明涉及半导体技术领域，更具体的说是涉及一种沟槽型MOSFET器件及其制造方法。
背景技术
目前，随着半导体技术的发展，功率器件作为集成电路中的重要组成部分，被广泛应用于汽车电子、通信设备等多个领域，现有技术多采用第三代半导体SiC材料的单极功率器件作为功率半导体开关器件，多采用超结概念以及分离型沟槽多晶硅技术来制作Si基器件。目前市面上SiC功率器件主要为平面型MOS，和沟槽型MOS，沟槽型MOS主要采用单沟槽或者双沟槽概念，采用双沟槽概念时栅极沟槽和源极沟槽水平分开为左右结构。
但是，现有技术中没有同时利用超结概念以及分离型沟槽多晶硅技术一起来制作SiC器件，现有沟槽型MOSFET器件结构不够紧凑，导通电阻较高，直接影响MOSFET器件性能。
因此，如何结合超结概念以及分离型沟槽多晶硅技术提供一种结构紧凑，导通电阻低的MOSFET器件制造方法是本领域技术人员亟需解决的问题。
发明内容
有鉴于此，本发明提供了一种沟槽型MOSFET器件及其制造方法，利用超结概念获得相对于传统沟槽结构更小的导通电阻，利用分离型沟槽多晶硅技术减少了栅极到漏极的米勒电容，可生产出结构紧凑，单位面积原胞密度大的沟槽型MOSFET器件。
为了实现上述目的，本发明采用如下技术方案：
一种沟槽型MOSFET器件制造方法，包括：
在衬底上外延形成基层区；
在所述基层区中形成第一沟槽；
在所述第一沟槽内表面形成P型层；
在所述P型层内填充多晶硅；
在所述第一沟槽上方形成第二沟槽；
在所述第二沟槽中形成栅结构。
优选的，所述在衬底上外延形成基层区，具体包括：
在所述衬底上积淀形成外延层；
在所述外延层上表面对应形成源极薄膜和体层薄膜，所述源极薄膜位于所述体层薄膜上表面；所述源极薄膜构成源极层，所述体层薄膜构成P型体层；
所述外延层、源极层及P型体层共同组成了基层区。
优选的，在所述第一沟槽内表面形成P型层，具体包括：
以预设角度向所述第一沟槽注入铝离子或硼离子，在所述第一沟槽的底部和侧壁上形成P型层。
优选的，在所述第一沟槽上方形成第二沟槽，具体包括：
通过光照和刻蚀分别经过所述源极层和所述P型体层在所述第一沟槽上方形成第二沟槽，所述第二沟槽相对于所述第一沟槽宽度大深度小，所述P型层中填充的多晶硅作为源极多晶硅。
优选的，在所述第二沟槽中形成栅结构，具体包括：通过牺牲氧化工艺、光刻工艺、栅氧氧化工艺、多晶硅填充工艺、多晶硅光刻工艺及刻蚀工艺形成栅结构，所述第二沟槽的侧壁和底部形成栅氧层，在所述栅氧层中形成栅极多晶硅。
优选的，还包括：在所述栅结构表面积淀形成层间介质，通过刻蚀形成接触开口，注入离子形成P+层，在所述层间介质上表面生长金属作为源极电极，所述源极电极分别连接所述源极层和所述P型体层，所述P+层位于接触开口底部所述源极电极与所述P型体层接触平面处，在所述衬底下表面减薄并进行背部金属淀积处理之后形成漏极电极。
一种沟槽型MOSFET器件，包括：衬底、基层区、第一沟槽和第二沟槽；
所述基层区位于所述衬底上表面，所述第二沟槽位于所述第一沟槽上方，且均设置在所述基层区内；
所述第一沟槽的内表面形成有P型层，所述P型层中填充有多晶硅。
优选的，所述基层区包括从上至下按顺序分布的：源极层、P型体层和外延层。
优选的，所述P型层中设置有源极多晶硅；
所述第二沟槽的侧壁和底部形成有栅氧层，在所述栅氧层中形成有栅极多晶硅。
优选的，还包括：源极电极、P+层、层间介质和漏极电极；
所述层间介质位于所述栅极多晶硅上表面，所述P+层位于接触开口底部所述源极电极与所述P型体层接触平面处，所述源极电极位于所述层间介质上表面，所述源极电极分别连接所述源极和所述P型体，所述漏极电极位于所述衬底下表面。
经由上述的技术方案可知，与现有技术相比，本发明公开提供了一种沟槽型MOSFET器件及其制造方法，通过P型层与外延层形成超结结构获得相对于传统沟槽结构更小的开通电阻，利用分离型沟槽多晶硅技术减少了栅极到漏极的米勒电容，可生产出结构紧凑、单位面积原胞密度大和电流密度大的沟槽型MOSFET器件，可显著的提高器件的功率密度，降低成本，提高产品的可靠性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1附图为本发明提供的沟槽型MOSFET器件制造方法流程图。
图2-9附图为本发明提供的沟槽型MOSFET器件制造方法各个阶段的截面图
图10附图为本发明提供的沟槽型MOSFET器件截面图。
附图标记：1—衬底、2—外延层、3—P型体层、4—源极层、5—第一硬掩模、6—第一沟槽、7—P型层、8—多晶硅、9—第二硬掩模、10—第二沟槽、11—栅极多晶硅、12—栅氧层、13—源极多晶硅、14—层间介质、15—P+层、16—源极电极、17—漏极电极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示，本发明实施例公开了一种沟槽型MOSFET器件制造方法，包括：
在衬底上外延形成基层区；
在基层区中形成第一沟槽；
在第一沟槽内表面形成P型层；
在P型层内填充多晶硅；
在第一沟槽上方形成第二沟槽；
在第二沟槽中形成栅结构。
如图2-9所示，为描述本发明提供的沟槽型MOSFET器件制造方法各个阶段。
如图2所示，在衬底1上积淀形成外延层2。
优选的，衬底1采用SiC材料，在SiC衬底生成过程中同时掺杂氮元素或磷元素从而降低电阻率。
优选的，外延层2厚度及电阻率根据器件的目标电压等级设置。
如图3所示，在外延层2上表面进行光刻和离子注入或者外延，对应形成源极薄膜和体层薄膜，源极薄膜位于体层薄膜上表面；源极薄膜构成源极层4，体层薄膜构成P型体层3；外延层2、源极层4及P型体层3共同组成了基层区。
优选的，P型体3通过注入铝离子或硼离子形成，为含有第二类传导率(P型导电)的SiC层；源极4通过注入氮离子或磷离子形成，为含有第一类传导率的SiC层。
如图4所示，在基层区上表面形成第一硬掩模5，在基层区中形成第一沟槽6。
优选的，第一硬掩模5为二氧化硅。
优选的，形成第一硬掩模5后对基层区进行刻蚀形成第一沟槽6。
优选的，第一沟槽6的深度根据器件的目标电压等级设置，电压等级越高，沟槽深度越大。
如图5所示，以预设角度向第一沟槽注入铝离子或硼离子，在第一沟槽6的底部和侧壁形成P型层7。
优选的，预设角度根据沟槽的宽度、深度以及要注入的层厚设定。
如图6所示，去除第一硬掩模5，在P型层7内填充多晶硅8，通过化学机械抛光、等离子体刻蚀或其他刻蚀手段去掉多余的多晶硅，使得多晶硅8表面和源极层4在同一水平面上。
优选的，所填充的多晶硅8为掺杂硼或其他P型掺杂元素，实现了降低电阻的目的。
如图7所示，在基层区上表面积淀形成第二硬掩模9，通过光照和刻蚀分别经过所述第二硬掩模9、源极层4和P型体层3在所述第一沟槽6上方形成第二沟槽10，第二沟槽10相对于第一沟槽6宽度大深度小，P型层7包围的沟槽内填充的多晶硅8作为源极多晶硅13，P型层7将源极多晶硅13与外延层2分隔开。
如图8所示，第二沟槽10通过牺牲氧化工艺、光刻工艺、栅氧氧化工艺，多晶硅填充工艺、多晶硅光刻工艺及刻蚀工艺形成栅结构，并去除第二硬掩模9；第二沟槽10的侧壁和底部形成栅氧层12，栅氧层12包围的沟槽中填充有栅极多晶硅11。
优选的，栅氧层12将栅极多晶硅11与源极多晶硅13分隔开。
如图9所示，在栅结构表面积淀形成层间介质14，通过刻蚀形成接触开口，注入铝离子形成P+层15，在层间介质14上表面生长金属作为源极电极16，源极电极16分别连接源极层4和P型体层3，P+层15位于接触开口底部源极电极16与P型体层3接触平面处，在衬底1下表面减薄并进行背部金属淀积处理之后形成漏极电极17。
优选的，通过P+层15保证了好的欧姆接触。
优选的，形成栅结构后，基于标准功率器件制造工艺，形成栅极接触开孔和源极接触开孔；所述源极电极16与所述源极多晶硅13连接，栅极电极与所述栅极多晶硅11连接。
如图10所示，一种沟槽型MOSFET器件，包括：衬底1、基层区、第一沟槽和第二沟槽；
基层区位于衬底1上表面，第二沟槽位于第一沟槽上方，且均设置在基层区内；
第一沟槽的内表面形成有P型层7，P型层7中填充有多晶硅8。
优选的，基层区包括从上至下按顺序分布的：源极层4、P型体层3和外延层2；
优选的，P型层7包围的沟槽内填充有源极多晶硅13，P型层7将源极多晶硅13与外延层2分隔开；
第二沟槽的侧壁和底部形成有栅氧层12，栅氧层12包围的沟槽中填充有栅极多晶硅11。
优选的，还包括：源极电极16、P+层15、层间介质14和漏极电极17；
层间介质14位于栅结构上表面，P+层15位于接触开口底部源极电极16与P型体层3接触平面处，源极电极16位于层间介质14上表面，源极电极16分别连接源极层4和P型体层3，漏极电极17位于衬底1下表面。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (6)

1.一种沟槽型MOSFET器件制造方法，其特征在于，包括：
在衬底上外延形成基层区；
所述在衬底上外延形成基层区，具体包括：
在所述衬底上积淀形成外延层；
在所述外延层上表面对应形成源极薄膜和体层薄膜，所述源极薄膜位于所述体层薄膜上表面；所述源极薄膜构成源极层，所述体层薄膜构成P型体层；
所述外延层、源极层及P型体层共同组成了基层区；
在所述基层区中形成第一沟槽；
在所述第一沟槽内表面形成P型层；
在所述P型层内填充多晶硅；所述P型层中填充的多晶硅作为源极多晶硅；
在所述第一沟槽上方形成第二沟槽；
在所述第二沟槽中形成栅结构；
在所述第二沟槽中形成栅结构，具体包括：通过牺牲氧化工艺、光刻工艺、栅氧氧化工艺、多晶硅填充工艺、多晶硅光刻工艺及刻蚀工艺形成栅结构，所述第二沟槽的侧壁和底部形成栅氧层，在所述栅氧层中形成栅极多晶硅；栅氧层将栅极多晶硅与源极多晶硅分隔开。
2.根据权利要求1所述的一种沟槽型MOSFET器件制造方法，其特征在于，在所述第一沟槽内表面形成P型层，具体包括：
以预设角度向所述第一沟槽注入铝离子或硼离子，在所述第一沟槽的底部和侧壁上形成P型层。
3.根据权利要求2所述的一种沟槽型MOSFET器件制造方法，其特征在于，在所述第一沟槽上方形成第二沟槽，具体包括：
通过光照和刻蚀分别经过所述源极层和所述P型体层在所述第一沟槽上方形成第二沟槽，所述第二沟槽相对于所述第一沟槽宽度大深度小。
4.根据权利要求1所述的一种沟槽型MOSFET器件制造方法，其特征在于，还包括：在所述栅结构表面积淀形成层间介质，通过刻蚀形成接触开口，注入离子形成P+层，在所述层间介质上表面生长金属作为源极电极，所述源极电极分别连接所述源极层和所述P型体层，所述P+层位于接触开口底部所述源极电极与所述P型体层接触平面处，在所述衬底下表面减薄并进行背部金属淀积处理之后形成漏极电极。
5.一种沟槽型MOSFET器件，其特征在于，包括：衬底、基层区、第一沟槽和第二沟槽；
所述基层区位于所述衬底上表面，所述第二沟槽位于所述第一沟槽上方，且均设置在所述基层区内；
所述第一沟槽的内表面形成有P型层，所述P型层中填充有多晶硅；
所述基层区包括从上至下按顺序分布的：源极层、P型体层和外延层；
所述P型层中设置有源极多晶硅；
所述第二沟槽的侧壁和底部形成有栅氧层，在所述栅氧层中形成有栅极多晶硅。
6.根据权利要求5所述的一种沟槽型MOSFET器件，其特征在于，还包括：源极电极、P+层、层间介质和漏极电极；
所述层间介质位于所述栅极多晶硅上表面，所述P+层位于接触开口底部所述源极电极与所述P型体层接触平面处，所述源极电极位于所述层间介质上表面，所述源极电极分别连接所述源极和所述P型体层，所述漏极电极位于所述衬底下表面。
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