CN1118091C - 集成电路及其制造方法 - Google Patents
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Abstract
一种填充半导体结构的相邻栅电极之间的间隙的方法，包括以下步骤：在此结构上方沉积自平面化材料，该材料的第一部分在栅电极之间流动以填充其间的间隙，该材料的第二部分沉积在栅电极顶部和所填间隙的上方，形成基本上为平面的表面层；在自平面化材料的第二部分中提供磷掺杂剂。
Description
本发明一般地涉及集成电路及其制造方法，更具体地涉及到具有改进平面性与碱离子吸杂特性的结构及方法。
从现有技术中可知，在应用光刻技术的半导体工艺中形成小的线路宽度几何图形时，需要为用在如上工艺中的各种光刻掩模提供高度平面化的表面。此外在动态随机存取存储器(DRAM)的制造中，形成的多个栅电极互相之间间隔很小的分隔，也就是说它们的每一个相邻对之间的间隙都是相当小的。这样就需要用适宜的材料来填充这些间隙的宽度，这些材料最好还应有低的介电常数以防止相邻电极之间的耦合，以及提供后续的光刻所需的平面表面。
在生产过程中，当形成栅电极后，在其表面上就化学气相沉积(CVD)一层氮化硅的介电层，这种CVD氮化硅是一种保形沉淀，所以仍保留有相邻栅电极结构之间的间隙。在沉积了氮化硅层后的栅电极结构之间的间隙宽度约是1200埃的数量级。其次，在整个结构上方再化学气相沉积一层硼磷掺杂玻璃(BPSG)以填入这些间隙中。CVD BPSG的厚度不仅足以填平这些间隙，而且还复盖在CVD氮化硅层顶部的上方和已填平的间隙的上方，其厚度约为4000埃-5000埃的数量级。
从已有技术中还可知，污染物诸如钠离子或其它碱离子有可能与外层BPSG层接触。因而BPSG层内的磷元素就作为吸杂材料中和了碱离子污染物的效应。所得结构然后加热，以形成更平面化的表面。因为，由于下一步光刻工艺处理所要求的高的平面度，例如处理金属层，以构图成导电线路，需要用相当昂贵的化学机械抛光(CMP)来形成所要求的平面度的表面。
本发明涉及间隙的填充，这些间隙诸如在半导体结构中的相邻栅电极之间的间隙。在一个实施例中，一种自平面化材料沉积在结构的上方。这种材料的第一部分在栅电极之间流动以填充这些间隙，而其第二部分则成为沉积在栅电极顶部上方和间隙的上方以形成一层大致平面的表面。而在该自平面化材料的第二部分中也形成了诸如磷的掺杂剂。
根据本发明，为了下一步光刻的需要，用具有很好的平面性的表面层来有效地填充相当小的间隙。此外磷掺杂剂还可提供吸杂以消除进入间隙填充材料中的碱污染物离子的负面效应。再一点，填充间隙的材料，也就是间隙填充材料的第一部分，其基本上不含污染物，它还具有相当小的介电常数，从而减小相邻电极之间的电耦合。
根据本发明的一个特征，自平面化材料是可流动的材料。磷掺杂剂例如可由如下过程提供：在自平面化材料的第二部分中注入磷离子，加热此材料以使这引起材料固化并又激活磷离子；在自平面化材料层的上方沉积一层磷掺杂层，把此结构加热以使磷掺杂剂扩散到自平面化材料的第二部分中去，并有选择地去除沉积层；或在磷化氢(phosphine)氛围中固化旋涂的自平面化材料。
本发明的其它特征，以及发明本身通过以下详尽阐述以及附图，可以更明显易懂，附图中：
图1-4是根据本发明制造的半导体集成电路结构的纵剖面图；图1显示的是沉积在半导体基片上的多个栅电极；图2显示的是图1结构在其表面上方用自平面化材料旋涂后的情况，材料的第一部分在栅电极之间流动以填充间隙，材料的第二部分沉积在栅电极顶部上方和间隙上方形成了一层相当平的平面表面；图3A显示的是根据本发明的一个实施例中，磷离子的离子植入自平面化材料的第二部分；
图3B显示的是根据本发明的另一实施例中，由磷掺杂剂沉积在自平面化层上形成的掺杂层；以及图4显示的是在自平面化材料的第二部分中形成的磷掺杂剂，它是由根据图3A在其中植入磷离子后退火形成，或是在图3B的磷掺杂层中掺杂剂外扩散后形成，或是根据本发明的第三实施例在磷化氢氛围中固化自平面化材料后形成。
参阅图1，例如硅的半导体基片10，在其表面上方已形成多个MOS晶体管12。每一个晶体管12都有其源区和漏区(图中未画)，每一个区都相应于这些栅电极14中的一个栅电极，栅电极设置在每一个源区和漏区之间。再详细地说，每一个栅电极14包括：例如包括热生长二氧化硅的底层16，低压化学气相沉积(LP CVD)多晶硅在二氧化硅层16上形成的层18，在多晶硅层18上化学气相沉积硅化钨层20以及顶层氮化硅层21。栅叠层(也就是16，18，20与21所有四层)的高度H′大约是4000埃到5000埃。在组成栅叠层后，在此结构的上方化学气相沉积一层氮化硅衬垫22。氮化硅衬垫的厚度大约300埃。此外，栅电极14的长度(L)(也就是氮化硅衬垫22外壁之间的距离)大约是1800埃的数量级，相邻栅电极之间的间隔(S)(也就是相邻氮化硅衬垫22外壁之间的距离大约是1200埃的数量级)。
如图1所示在构图栅电极14之后，应用传统的光刻工艺，将自平面化材料24旋涂在此结构表面上方，如图2所示。材料24是可流动的氧化物。在一个实施例中可流动的氧化物例如是氢化倍半氧化硅(hydrogensilsegquioxane)玻璃(可流动氧化物材料)，由美国密西西比州Midland市Dow-Corning公司生产与销售。当这种可流动的氧化物材料24-经旋涂，它就可以自成平面，材料24的第一部分，即下面部分26就在栅电极14之间流动且填充相邻栅电极14之间的间隙，材料24的第二部分，即上面部分28就在栅电极14的顶端以及相邻栅电极14之间已填充的间隙的上方形成具有大致平的平面表面32的沉积层30，如图2所示。自平面化材料的厚度(T)足以提供栅极和在自平面化材料上方的导电层(图中未画)之间的绝缘。在一个实施例中，T约是6000埃的数量级。由于栅叠层厚约4000埃，因此自成平面材料在区域28上的厚度约为2000埃。
参阅图4，碱离子吸杂掺杂剂36，诸如磷设置在自平面化材料14的第二部分即上面部分28中。
图3A显示了一种在自平面化材料的第二部分，即上面部分28中提供磷掺杂剂36′的工艺。磷离子36′被植入自平面化材料24的第二部分，即上面部分28中。剂量与能量级的选择以使离子36′能植入第二部分，即上面部分一定深度(D)。在一个实施例中，从自平面化材料24的平面表面上表面32起，D约为1000埃，掺杂浓度约为材料24重量的2％到6％，更好地掺杂浓度是材料24重量的2％到5％，最好是材料24重量的2％到4％。
在一个实施例中，离子植(注)入是在自平面化材料24固化之前进行的。植入的离子需要由相当高的温度退火来激活。通常自平面化材料24是在氮气中，在400℃到900℃温度中经过60分钟固化。这样在固化之前先植入离子，可以有效地利用固化工艺达到两个目的，即固化材料及激活离子。
图3B显示了在自平面化材料24的第二部分，即上面部分28中提供磷掺杂剂的另一种替代工艺，如图所示，在自平面化材料24的表面32上方化学气相沉积具有磷离子36的多晶硅(poly)层40。掺杂多晶硅层40其掺杂浓度足以提供在自平面化材料上面部分所需要的掺杂剂浓度。在一个实施例中，多晶硅的掺杂浓度至少约每立方厘米1020原子数。
掺杂多晶硅层40先于自平面化材料24固化而沉积于该材料上是为了利用固化过程以激活掺杂剂。材料固化后就是以使得在多晶硅层40中的磷掺杂剂26向外扩散进入自平面化材料24的第二部分，即上面部分28中去。如图所示，掺杂剂的峰值浓度处在自平面化材料24表面下约500埃到1000埃处。在一个实施例中，材料是经在氮气中或在真空中，在大约900℃温度下历经一小时对所得构件烘焙而固化的，然后掺杂的多晶硅层40再由选择性反应离子腐蚀(RIE)去除。
另一种在自平面化材料24的第二部分，即上面部分28中提供形成磷掺杂剂36的工艺技术是在磷化氢气氛中固化自平面化材料24。当在结构表面上方旋涂自平面化材料24以后，此结构被放入充以磷化氢气氛的烘箱中。此结构在烘箱中在400℃到900℃的温度下经过60分钟左右的烘焙。在磷化氢气体中的磷就扩散到自平面化材料24的第二部分，即上面部分28中去。掺杂剂浓度的峰值浓度可达大约在自平面化材料的表面之下500埃到1000埃处。
这样，根据如上所述的本发明，当污染物，诸如钠离子或其它碱性材料可能进入并与固化后的自平面化材料24的第二部分，即上面部分28接触后，在自平面化材料24的第二部分，即上面部分28中的磷掺杂剂36就作为吸杂材料中和碱离子污染物的效应。此外，图4所示的结构还满足后续光刻处理所需的高度平面性，此后续处理用于例如形成上面的金属层，或者导电的互连线路(图中未画)。这样，本发明有效地填充了诸如相邻栅电极之间的相对小的间隙，并形成了一层为后续光刻所需要的非常平的平面。此外，磷掺杂剂还提供吸杂以去除进入间隙填充物料中的碱离子污染物离子的负面效应。而且，填充间隙的材料，也就是间隙填充材料24的第一部分，即下面部分26，其基本上不含此种污染物，其具有相当小的介电常数(也就是说约在3.6到4.0范围内)，这样就减少了相邻栅电极之间的电耦合。
其它实施体，也都包括在后附权利要求的精神与范围内。例如其它一些可流动的材料也可以旋涂在如图1所示的结构上。所以，尽管上面采用了氢化倍半氧化硅玻璃(例如FOx材料)，但是其它具有低密度的自平面化的和阻温的氧化硅膜例如旋涂氧化硅气凝胶等也可应用。此外自平面化层也可以用气体沉积工艺(gaseous deposition)来形成，其与上述旋涂玻璃材料具有类似的流动特性，其可代替旋涂沉积工艺。这样一种可以用作气体沉积的产品可由加利福尼亚州，Chatsworth市PMT电子技术公司出售的Flowfill材料来得到。
Claims (9)
1.一种填充半导体结构的相邻栅电极之间的间隙的方法，包括以下步骤：
在此结构上方沉积自平面化材料，该材料的第一部分在栅电极之间流动以填充其间的间隙，该材料的第二部分沉积在栅电极顶部和所填间隙的上方，形成平面表面层；
在自平面化材料的第二部分中提供磷掺杂剂。
2.根据权利要求1所述的方法，其中，自平面化材料是可流动材料。
3.根据权利要求2所述的方法，其中，可流动材料是氧化物。
4.根据权利要求1、2或3所述的方法，其中，可流动材料旋涂在所述结构上方。
5.根据权利要求1、2或3所述的方法，其中，可流动材料用气体沉积法沉积在结构上方。
6.根据权利要求4所述的方法，其中，可流动材料是氢化半倍氧化硅玻璃。
7.根据权利要求3所述的方法，其中磷掺杂剂提供包括在自平面化材料层第二部分中植入磷离子以及加热材料使之固化并激活磷离子的步骤。
8.根据权利要求3所述的方法，其中磷掺杂剂提供步骤包括在自平面化材料层的上方沉积磷掺杂层，加热此结构，使磷掺杂剂向外扩散到自平面化材料第二部分中并固化自平面化材料，以及有选择地去除沉积层的步骤。
9.根据权利要求3所述的方法，其中磷掺杂剂提供步骤包括在磷化氢气氛中固化旋涂的自平面化材料的步骤。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US846,925 | 1997-04-30 | ||
| US08/846,925 US6492282B1 (en) | 1997-04-30 | 1997-04-30 | Integrated circuits and manufacturing methods |
| US846925 | 1997-04-30 |
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| Publication Number | Publication Date |
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| CN1208956A CN1208956A (zh) | 1999-02-24 |
| CN1118091C true CN1118091C (zh) | 2003-08-13 |
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| EP (1) | EP0875929A3 (zh) |
| JP (1) | JP4047447B2 (zh) |
| KR (1) | KR100515723B1 (zh) |
| CN (1) | CN1118091C (zh) |
| TW (1) | TW406307B (zh) |
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| US6348706B1 (en) * | 2000-03-20 | 2002-02-19 | Micron Technology, Inc. | Method to form etch and/or CMP stop layers |
| US7265066B2 (en) * | 2005-03-29 | 2007-09-04 | Tokyo Electron, Ltd. | Method and system for increasing tensile stress in a thin film using collimated electromagnetic radiation |
| US7981483B2 (en) * | 2007-09-27 | 2011-07-19 | Tel Epion Inc. | Method to improve electrical leakage performance and to minimize electromigration in semiconductor devices |
| US8192805B2 (en) | 2007-09-27 | 2012-06-05 | Tel Epion Inc. | Method to improve electrical leakage performance and to minimize electromigration in semiconductor devices |
| CN101834224B (zh) * | 2010-03-26 | 2011-06-15 | 浙江大学 | 一种用于太阳电池制造的硅片快速热处理磷扩散吸杂工艺 |
| US9231067B2 (en) | 2014-02-26 | 2016-01-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabricating method thereof |
| US9293459B1 (en) | 2014-09-30 | 2016-03-22 | International Business Machines Corporation | Method and structure for improving finFET with epitaxy source/drain |
| CN107706181A (zh) * | 2017-10-27 | 2018-02-16 | 睿力集成电路有限公司 | 高深宽比结构、电容器结构、半导体存储器件及制备方法 |
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| JP2575545B2 (ja) * | 1990-07-05 | 1997-01-29 | 株式会社東芝 | 半導体装置の製造方法 |
| US5268333A (en) * | 1990-12-19 | 1993-12-07 | Samsung Electronics Co., Ltd. | Method of reflowing a semiconductor device |
| JP2538722B2 (ja) * | 1991-06-20 | 1996-10-02 | 株式会社半導体プロセス研究所 | 半導体装置の製造方法 |
| JPH05243223A (ja) * | 1992-02-28 | 1993-09-21 | Fujitsu Ltd | 集積回路装置の製造方法 |
| EP0560617A3 (en) * | 1992-03-13 | 1993-11-24 | Kawasaki Steel Co | Method of manufacturing insulating film on semiconductor device and apparatus for carrying out the same |
| US5455205A (en) * | 1992-03-25 | 1995-10-03 | Matsushita Electric Industrial Co., Ltd. | Method of producing semiconductor device |
| JP3214186B2 (ja) * | 1993-10-07 | 2001-10-02 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US5478758A (en) * | 1994-06-03 | 1995-12-26 | At&T Corp. | Method of making a getterer for multi-layer wafers |
| US5656555A (en) * | 1995-02-17 | 1997-08-12 | Texas Instruments Incorporated | Modified hydrogen silsesquioxane spin-on glass |
| US5496776A (en) | 1995-04-27 | 1996-03-05 | United Microelectronics Corporation | Spin-on-glass planarization process with ion implantation |
| US5616513A (en) * | 1995-06-01 | 1997-04-01 | International Business Machines Corporation | Shallow trench isolation with self aligned PSG layer |
| JPH09167765A (ja) * | 1995-08-01 | 1997-06-24 | Texas Instr Inc <Ti> | 絶縁層およびこれを形成する方法 |
| US5795820A (en) * | 1996-07-01 | 1998-08-18 | Advanced Micro Devices | Method for simplifying the manufacture of an interlayer dielectric stack |
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- 1998-04-29 CN CN98107766A patent/CN1118091C/zh not_active Expired - Fee Related
- 1998-04-30 JP JP12090398A patent/JP4047447B2/ja not_active Expired - Fee Related
- 1998-04-30 KR KR10-1998-0015450A patent/KR100515723B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW406307B (en) | 2000-09-21 |
| KR100515723B1 (ko) | 2005-12-08 |
| KR19980081850A (ko) | 1998-11-25 |
| JPH10335323A (ja) | 1998-12-18 |
| EP0875929A3 (en) | 2000-08-02 |
| CN1208956A (zh) | 1999-02-24 |
| EP0875929A2 (en) | 1998-11-04 |
| JP4047447B2 (ja) | 2008-02-13 |
| US6492282B1 (en) | 2002-12-10 |
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