TW468223B - Method for improving the planarization of inter layer dielectric layer - Google Patents

Abstract

The present invention provides a method for manufacturing E-DRAM on a semiconductor chip. There are a memory area and a logic circuit area on the surface of the semiconductor chip. The method includes the following steps: forming an AP oxide layer on the surface of the semiconductor chip for covering on the memory area and the logic circuit area; next, forming a conductive layer on the AP oxide layer; subsequently, using a lithography process and an etching process to form at least one a dummy pattern and a plurality of bottom storage electrodes respectively in the conductive layer above the logic circuit area and the memory cell area; using a back etching process to make the dummy pattern have a sharp structure; then forming an insulation layer and a top electrode on the surface of the bottom storage electrode; finally, forming a dielectric layer on the surface of the semiconductor chip to fully cover on the top electrode and the dummy pattern, wherein the dielectric layer fills up the space between the dummy patterns.

Description

Vi4 6 82 2 3-V. Description of Invention (l) | Field of Invention, i

I: j ^ j The present invention provides a process method for dynamic random access memory (dyna in ic random access memory, DR AM), especially an embedded DRAM (E-DRAM). of

I 丨 process i7 is a method for improving the planarization of the inter layer dielectric layer (| • j | ILD layer).丨 j i Background note! Dynamic random access memory (DRAM) is composed of a large number of memory cells 1: (m e m 0 r y c e 1 1). Each memory cell contains a 1-pass transistor, usually a metal-oxide-semiconductor field-effect (transistor, MOSFET), and a storage capacitor (storage | capacitor). With the continuous increase of process accumulation, the trend of making semi-conducting volume circuits is to carry out DRAM memory cell arrays and high-speed logic circuit elements (e 1 ements). Integrated and manufactured on a chip at the same time, forming an embedded dynamic random access memory (E-DRAM) that combines a memory array and logic circuits (1 og ic circuits) at the same time to save a lot of area And speed up the signal processing speed "However, the conventional process of making E-DRAM will encounter an interlayer dielectric layer 46 8223. ..... ··-·· _______________________________-—- · .— + 5. Description of the invention (2) The problem that (inter layer dielectric layer, ILD layer) is not easy to planarize. To be more specific, it is also caused by the logic region on the E-dram, or the peripheral area, and the step height difference between the delta memory regions problem. Please refer to FIG. 1 to FIG. 8. FIG. 1 to FIG. 8 are schematic diagrams of a conventional method for fabricating an E-DRAM on a semiconductor wafer 50. As shown in FIG. 1, the semiconductor wafer 50 includes a siiicorL substrate 52. A memory area 10 and a logic circuit area 12 have been previously defined on the surface of the Shi Xi substrate 52. The memory area 10 includes a plurality of capacitor structures 18a, 1❿, and a gate structure 14; and the logic circuit area 12 includes a plurality of gate structures 15. In the delta memory region 10, the capacitor structures 18a and 18b are formed on an approximately flat AP0XIDE (aΐmosphericpressureCVDoχi (ie) layer 22), and the gate structure 14 is formed on the surface of the silicon substrate 52. It is covered with a PSG (phosphosilicate glass) layer 20. Through the conductive plugs (p 1 ug) 16 formed in the Ap qx ^ de layer 22 and the PSG layer 20, the capacitor structure 1 8 a can communicate with Shi Xi An electrode or source (not shown in the figure) on the surface of the substrate 52 is used to form an electrical connection. A conventional method for making E-DRAM is to form a layer of BPSG (borophosphosilicate glass) 24 on the surface of the semiconductor wafer 50. In order to cover the memory area 10 and the logic circuit area 12 at the same time, it is used as a buffer layer. Because the height of the capacitor structures 18a and 18b is about d6 8223 _____________ 'a'… r · five 'invention description ( 3) i 丨 to 9 0 0 0 angstroms (angstroms), so deposit i on the surface of the semiconductor wafer 5 0

丨 After the BPSG layer 24, a great height difference will be generated between the memory area 10 and the 1 logic circuit area 12 on the surface of the semiconductor wafer 50. The difference in height is approximately: 6 0 0 to 9 0 0 Angstroms. As shown in FIG. 2, a non-isotropic dry etching process is performed: the BPS G layer 2 4 is etched down to the surface of the AP OXIDE layer 2 2, and a sidewall 2 6 is formed at the edge of the memory area 10. 'To buffer the stress on the surface of the semiconductor wafer 50 table I i. A PSG layer 32 having a thickness of about 300 to 7000 Å is deposited on the surface of the semiconductor wafer 50, and a thermal re-flow process is used to initially reduce the memory area 10 and The height difference between the 12 logic circuit areas. ;

: As shown in FIG. 3, a photoresist Gj: layer 42 is formed on the surface of the semiconductor wafer 50, and the photoresist layer 42 above the memory area 10 is removed by I using a yellow light process. Subsequently, an etching process is performed on the surface of the semiconductor wafer 50 to remove a BPSG layer 32 that is not covered by the photoresist layer 42 by a predetermined depth, so that the thickness of the BPSG layer 32 above the memory area 10 is about 100. 〇Around. Then, as shown in FIG. 4, a photoresist removal and cleaning and drying process is performed to completely remove the photoresist layer 42. i! As shown in Figure 5, a chemical mechanical polishing (chemical; 1116 (: 11 & 1 ^ 〇310〇11511111 Dan, 〇 ^)) process is then performed to planarize the 3? 36 layer 3 2 丨: Then, as shown in FIG. 6, a PSG layer 44 having a thickness of about 1,000 angstroms is deposited on the surface of the semiconductor wafer > 50 so that the surface of the semiconductor wafer 50 has a flatter surface.

Page 6 46 8223 V. Description of the invention (4) ------------ One_ As shown in Fig.7, the traditional yellow light process and dry money engraving process are used to make contact. A contact plug 46 is formed on the logic circuit area 12; it penetrates the PSG layer 44, PSG layer 32, AP OXIDE layer 22, and PSG layer 2 to the drain or source of the silicon substrate 5 2 surface. (Not shown in the figure) is used to electrically connect the components on the surface of the silicon substrate 52 and the upper metal wire layer. Finally, as shown in FIG. 8 ', a metal wire layer 48 is formed on the surface of the PSG layer 4 4 to complete the conventional method for manufacturing E-DRAM. To sum up, the conventional method for manufacturing E-DRAM can be summarized as follows: (1) BPSG layer 24 'needs to be deposited to form sidewalls 26, thereby reducing the stress on the surface of the semiconductor wafer 50. (2) In the process of forming the side wall member 26, a melting and engraving process is required. (3) A thicker PSG layer 32 needs to be deposited. (4) A heat flow process is required to obtain a flatter psG layer 32 surface. (5) f Perform a yellow light process and an etching process to remove—a predetermined thickness of the PSG layer 32 above the memory area 10. (6) t Perform an additional CMP process. Therefore, the conventional method of making E-DR AM is both time-consuming and costly.

Summary of invention

The main object of the present invention is to provide a more economical method of manufacturing E_DRAM.

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J 468223 5. Description of the invention (5) Another object of the present invention is to provide an E-DRAM manufacturing method to solve the problem of the height difference between the memory area and the logic circuit area. In the embodiment of the manufacturing method of the present invention, it is performed on a semiconductor wafer having a memory area and a logic circuit area defined on its surface. In this method, an AP OX ID layer is formed on the surface of the semiconductor wafer, covering the memory area and the logic circuit area, and then forming a conductive layer on the AP OXIDE layer. Subsequently, a yellow light process and an etching process are used to form at least a dummy pattern and a plurality of lower storage electrodes in the conductive layer above the logic circuit region and the memory cell region, respectively, and an etching process is used. So that the dummy pattern has a sharp structure, and then an insulating layer and an upper electrode are formed on the surface of the lower storage electrode. Finally, a dielectric layer is formed on the surface of the semiconductor wafer to completely cover the upper electrode and the dummy pattern, and the dielectric layer completely fills the space between the dummy patterns. An advantage of the present invention is that a dummy pattern is formed over the logic circuit area while defining the storage electrodes above and below the memory area. Therefore, there is no need to form additional sidewalls or perform an additional CMP process. In a preferred embodiment of the present invention, the width of the space between the dummy patterns is less than half the thickness of the dielectric layer to complete the process of the lower storage electrode. In addition, in order to reduce the dummy pattern and the gold formed in subsequent processes 468223 V. Description of the invention (6) j-The parasitic capacitance between the conductive wire layers, the method of the present invention can also be used to form the dummy j

After the S pattern, another etching process is performed to make the dummy pattern have a sharp structure and reduce parasitic capacitance. !, | Detailed description of the invention i | >

I Please refer to FIGS. 9 to 13. FIGS. 9 to 13 are schematic diagrams of a method for fabricating an E-DR A Μ on a half of a conductor wafer 100 according to the present invention. As shown in FIG. 9, the semiconductor wafer 100 includes a substrate 102, and a memory region 104 and a logic circuit region 106 have been previously defined on the surface of the substrate 102. Be careful; the area 104 contains a plurality of gate structures 103, and the logic circuit area 0 contains a plurality of gate structures 105. The gate structure 10, 3, and 105 are formed on the surface of the substrate 102, and are covered by a thickness of about $ 300 to about 700. The PSG layer 108 is formed by a chemical vapor deposition method. After the PSG layer 108 is formed, a CMP process can be used to obtain a relatively flat surface. The surface of the PSG layer 108 is covered by an APX I D E layer 1 10. In FIG. 9, the present invention first uses a traditional yellow light (Πth 〇graphy) process and a money-engraving process to form a plurality of contacts in the PSG layer 108 and the AP OXIDE layer 110 which are located above the memory area 1 4 ^ ; (Contact hole) 114a. Next on the surface of the semiconductor wafer 10 0 __ 丨 〇 polycrystalline stone (ρ ο 1 ysi 1 ic ο η) layer or doped polycrystalline stone (d ο ped 丨 polysilicon) layer (not shown in the figure) And fill up the contact, and use a traditional chemical vapor deposition process, yellow light process and # 刻, and so on.

j 468223 5. Description of the invention (7) Process to remove contact holes 4 & polycrystalline silicon layer on the periphery to form a polycrystalline silicon contact plug or contact electrode 114b, and simultaneously on each contact electrode 1 1 A landing pad 116 is formed above 4 b. The contact electrodes 1 4b and the transfer pads 1 16 can also be formed by using the chemical vapor deposition process, the yellow light process, and the etching process. Next, a low pressure chemical vapor deposition (LPCVD) process is performed. The main reaction gases are sintering (s Π ane, Si Η 4) and phosphine (PH 3). A conductive layer 112 composed of amorphous silicon (a-Si) and phosphorus or us is formed on the surface of the semiconductor wafer 100. The thickness of the conductive layer 111 is about 60 to 800 angstroms. In other embodiments, the conductive layer Π 2 may be composed of a doped polycrystalline silicon or an amorphous silicon. Next, a traditional yellow light process is performed, and a photoresist layer 1 1 8 is used to define the lower storage electrode 1 2 on the conductive layer 11 2 above the § self-remembering area 104 and the logic circuit area 1 06. And the positions of the dummy patterns 1 2 2. As shown in FIG. 10, a dry etching process is performed, and the photoresist layer 1 1 8 is used as a hard mask to remove the conductive layer 1 1 § that is not covered by the photoresist layer 1 1 up to the AP 〇XIDE layer 11 〇. In order to form a lower layer storage electrode 120 and a dummy pattern 122 on the surface of the semiconductor wafer 100 at the same time. The lower storage electrode 12 is about the same height as the dummy pattern 12 2. In order to increase the surface area of the lower storage electrode 120,

4, 6 82 2 3 V. Description of the invention (8) ......... Ί An ultra-high vacuum chemical vapor deposition (UHV CVD) process, which is below ground- The pressure of the tor (torr) and the temperature between 550 and 800 degrees Celsius uniformly formed a herai-spherical grain with hemispherical I-shaped grains on the exposed surface of the lower storage electrode 120. HSG) structure (not shown in the figure) to increase the surface area of the underlying storage electrode 120. Then, i, an annealing process is performed to store the lower layer in an inert environment; the electrode 12 is uniformly diffused into the η s G polycrystalline silicon layer, and the lower storage electrode 12 〇 Amorphous silicon is converted into polycrystalline silicon. As shown in FIG. 11, a silicon oxide-silicon nitride-oxide-containing silicide: 0 (oxidized-silicon nitride-silicon oxUe, 0N0) process is then performed. First, a native 0xide layer with a thickness of about 10 to 50 angstroms is formed on the surface of the underlying storage electrode 120, and then a plasma-enhanced CVD (PECVD) process or an LPCVD process is performed. A silicon nitride layer with a thickness of about 45 Angstroms was deposited on the surface of a natural oxide layer using dihydrogen si une (SiH2Ci2) and ammonia (ammonia, dragon 3) as a reactive gas. Finally, the semiconductor wafer 100 is subjected to a high-temperature healing process for about 30 minutes in a high f | oxygen-containing environment at about 800 degrees Celsius to form a thickness of about 400 Å on the surface of the silicon nitride layer!

§80 silicon oxide (siiicon). The shape Q is formed on the surface of the storage electrode 120. The natural oxide layer, silicon nitride layer, and oxygen-containing silicide layer form the capacitor insulating layer 127. Among these, Oxy-containing silicide | The layer is mainly used to fill the defects of the silicon nitride layer on the surface of the natural oxide layer

6 82 2.3 ____ 'i V. Description of the invention (9) 丨 (defect) to reduce the leakage current. Subsequently, a CVD process is performed to form a polycrystalline silicon layer 125 on the capacitor insulating layer 1 2 7 and a yellow light process is performed to form a photoresist layer 1 7 0 on the surface of the semiconductor wafer 100 to cover the memory region 1 0 4. As shown in FIG. 12, an upper electrode etchback process is performed to make the dummy pattern 1 2 2 have a sharp structure 1 2 3 at the upper end to reduce the dummy pattern 1 2 2 and subsequent formation of an upper layer. The parasitic capacitance between the metal wire layers defines the upper electrode 125 at the same time. Then, the photoresist layer 170 is removed. As shown in FIG. 13, a BPSG layer 124 of a predetermined thickness is formed on the surface of the semiconductor wafer 100 next. In order for the BPSG layer 1 24 to completely fill the space between the dummy patterns 1 22, the predetermined thickness of the BPSG layer 12 4 is preferably larger than half the width i between the dummy patterns 12 2. At this time, since the dummy pattern 1 2 2 is approximately the same height as the capacitor structure 1 2 9, i is thus deposited on the logic circuit region 10 6 and the BPSG layer above the memory region 104; 1 2 4 will no longer have a significant height difference. . A dielectric layer 126 is then formed on the BPSG layer 124. Dielectric layer material system: It contains sulphur dioxide, phosilicate glass (PSG), borosilicate glass (BPSG), gas-containing sulphur oxide (BPSG) Hu〇rinated siHcori dioxide,: F XS i 0 y), parylene polymer (pary 1 ene), Teflon i (Teflon), or 1 carbon compound (am〇rph〇us carbon, a_C: F ).丨 Next, use a dry-etching process, a CVD process, and a CMP process to logically edit the dielectric layer 126, BPSG layer 124, and AP OXIDE layer above $ @ 10 6 > ^ G 82 2 3; V. Invention Note (11) and the contact plug 128 is formed in the PSG layer 108. Finally, a metal deposition process is used to form an upper metal wire layer 13 on the PSG layer 1 2 6. Please refer to FIG. 14, which is a top view of the dummy pattern 122 located above the logic circuit area 106. As shown in FIG. 14, the dummy pattern 1 2 2 can be designed using CAD (compiit: er assisted design) on the same mask as the layer storage electrode 120. The top view pattern can be a long strip 1 5 2. Square 1 5 4 and rectangular 1 5 6 or above. It should be noted that the dummy patterns 1 2 2 must avoid the positions of the contact plugs 15 8 formed in the logic circuit area 106, and the width of the space between the dummy patterns 12 2 must be less than half the thickness of the BPSG layer 124. In this way, the BPSG layer 124 can completely fill the space between the dummy patterns 1 2 2. In addition, the dummy pattern 1 2 2 can be set not only above the logic circuit area 106 but also in any other non-memory area 104. Because the method of the present invention is to form the lower layer storage electrode 120, a dummy pattern is formed on the logic circuit area 106 or other non-memory area: 1222. Therefore, the dummy pattern 1 2 2 is approximately the same height as the capacitor structure 1 2 9, so that the BPSG that is deposited above the logic circuit area 106 and the memory area 104 is no longer a significant height difference. Compared with the conventional method for manufacturing E-DRAM, the manufacturing method of E-DRAM of the present invention has the following advantages: (1) No need to form a sidewall to reduce the surface of the semiconductor wafer. 468223 ·· * ·-·. ···. _? —— * -— · _-. ——Π. „. .Η .......... —- '--5. Description of the invention (1U force. (2) No need to deposit a thicker PSG layer. (3) No yellow light process and etching process are needed to remove a PSG layer with a predetermined thickness above the memory area. (4) No additional CMP process is needed to flatten In summary, the method of manufacturing the E-DRAM of the present invention is more economical than the conventional method: there are many steps, so the method of the present invention is an economical and efficient process. The above is only a comparison of the present invention In the preferred embodiment, all equal changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

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Page 14 4. 6 B2 2 3 Brief description of the diagrams Brief description of the diagrams Figures 1 to 8 are not intended for the conventional method of making an E-DRAM on a semiconductor wafer. FIG. 9 to FIG. 13 are schematic diagrams of an E-DRAM manufacturing method according to the present invention. FIG. 14 is an illustration of symbols on the top view of a dummy pattern located above a logic circuit area of the present invention

1 0 Memory area 12 Logic circuit area 14, 15 Gate structure 16 Contact lower electrode 18a 'b Capacitor structure 20 PSG layer 22 AP OXIDE layer 24 BPSG layer 26 Side wall 32 PSG layer 42 Photoresistance layer 44 PSG layer 46 Contact plug 48 metal wire layer 50 semiconductor wafer 52 dream substrate 100 semiconductor wafer 102 substrate 103, 105 gate structure 104 memory area 106 logic circuit area 108 PSG layer 110 AP OXIDE layer 112 amorphous silicon layer 114a contact hole 114b contact electrode -46 8223 Figure Brief description of the formula 116 transfer pad 118 photoresist layer 120 lower storage electrode 121 edge structure 122 dummy pattern 123 sharp structure 124 BPSG layer 125 upper electrode 126 PSG layer 127 capacitor insulation layer 128 contact plug 129 capacitor structure 130 metal wire layer 152 long Bar-shaped dummy pattern 154 Box-shaped dummy pattern 156 Rectangle dummy pattern 158 Contact plug position

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Claims (1)

46 8223 VI. Scope of Patent Application 1. A method for improving the planarization of an interlayer dielectric (i LD) includes the following steps: A semiconductor wafer is provided, and a memory is defined on the surface of the semiconductor wafer A memory area and a logic circuit area; forming a first dielectric layer on the surface of the semiconductor wafer, covering the memory area and the logic circuit area; forming a conductive layer on the first dielectric layer At the same time, forming at least a dummy pattern and a plurality of lower storage electrodes in the logic circuit area and the conductive layer above the memory area; j formed on the surface of the lower storage electrode An insulating layer and a top electrode; and forming a second dielectric layer on the surface of the semiconductor wafer to cover the upper electrode and the dummy pattern. ^ 2. The method according to item 1 of the scope of patent application, wherein after the dummy pattern is formed, the method further includes an e tch back process to make the dummy pattern have a sharp structure, and meanwhile The upper electrode is defined. 3. If the method of claim 1 is applied, after the second dielectric layer is formed, the method further includes the following steps: 丨 forming a third dielectric layer on the second dielectric layer; and 46 8223, 'Sixth, the scope of patent application: a thermal flow process is performed to make the surface of the third dielectric layer a substantially flat surface. 4. The method according to item 3 of the scope of patent application, wherein the third dielectric layer material comprises stone dioxide, phosphosilicate glass (PSG), and borophosphosi 1 icate glass. , BPSG), fluorinated silicon dioxide (FxSiOy), parylene, Teflon, or amorphous carbon (aC: F). 5. The method according to item 1 of the scope of patent application, wherein the thickness of the conductive layer is about 600 to 800 angstroms. Ί 6 The method according to item 1 of the scope of patent application, wherein the lower storage electrode is approximately the same height as the dummy pattern. 7. The method of claim 1 in which the first dielectric layer is an AP 0 乂 10 £ layer. 8. The method of claim 1, wherein the second dielectric layer is composed of B P S G. 9. The method according to item 1 of the application, wherein the conductive layer is a doped polysilicon layer or an amorphous stone layer Page 18 468223 6. Application of patent scope (amorphous silicon layer) 0 J 1 0. For the method of patent application scope item 1, wherein the width of the space between the dummy patterns must be less than half the thickness of the second dielectric layer, The second dielectric layer can completely fill the space between the dummy patterns. 1 1. The method of claim 1 in which the dummy pattern and the plurality of lower storage electrodes are formed using a yellow light process and an etching process. 1 2. A method for improving the planarization of an interlayer dielectric layer includes the following steps: A semiconductor wafer is provided, and a memory region and a galvanic circuit region have been defined on the surface of the semiconductor wafer, and an AP is formed on the surface of the semiconductor wafer. The OXIDE layer covers the upper road of the record _-t Electric X ο Series P Logic A and the upper ED layer conductance of the memory area-Chengdan single series memory logic = β = 口 于 于 别 分 分 ' According to the plan, the design process is to create a virtual engraved one, melt one less, and form a middle layer of light silicon yellow. This one enters the upper area of the road and conducts the pole electricity; the upper pole and the electricity are stored at the edge of the reservoir. A number of electrodes are formed in a complex shape in the surface table. The electrode storage layer below the layer should be sharp at the top of the area structure. 1 There is a plan to set it up, and the process is to make electrode erosion. When you go back, you will have the same electricity when you go to the fixed layer. 46. Applying for a patent scope 1 Form a first dielectric layer on the surface of the semiconductor wafer to completely cover the upper electrode and the dummy pattern. The first dielectric Completely filled The dummy space between the case;: wherein the width of the space between the dummy patterns must be less than half the thickness of the first dielectric layer. 13. The method according to item 12 of the scope of patent application, wherein after forming the dielectric layer I, the method further comprises the following steps: forming a second dielectric layer on the dielectric layer; and A heat flow process is performed to form a substantially flat surface on the surface of the second dielectric layer. : 1 4. The method according to item 13 of the scope of patent application, which makes the material of the second dielectric layer include silicon dioxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and fluorine-containing dioxide Silicon (FxSiOy). 15. The method according to item 12 of the patent application, wherein the thickness of the conductive layer is about 60 to 800 angstroms. 16. The method according to item 12 of the scope of patent application, wherein the lower storage electrode i is approximately the same height as the dummy pattern. 17. The method according to item 12 of the patent application, wherein the conductive layer is a doped polycrystalline silicon layer or an amorphous silicon layer. Page 20 J 468223 6. Scope of Patent Application 1 8. The method of item i 2 of the scope of patent application, wherein the dielectric layer is composed of BPSG. Page 21