TW200415704A - Integrated circuits with air gaps and method of making the same - Google Patents

Abstract

An integrated circuits with air gaps is disclosed. An underlayer is formed on a substrate. A first metal pattern is formed on the underlayer. A dielectric layer is deposited on the underlayer and the first metal pattern. A second metal pattern is formed on the dielectric layer. Utilizing the first metal pattern and the second metal pattern as masks, an isotropic etch process is performed on the dielectric layer and the underlayer. A plurality of holes is formed in the dielectric layer and the remaining dielectric layer serves as supports under the second metal pattern. A chemical vapor deposition process is performed to deposit a cap layer on the second metal pattern and to seal the holes.

Description

200415704 V. Description of the invention (1) [Technical Field] The board of the present invention provides a high performance integrated circuit (1C) structure, especially an integrated circuit structure with an air gap. And how to make it. The present invention is particularly suitable for the field of logic that requires high operating performance and high integration degree (or integrated IC (such as a system integrated chip (SyStem-on-chip)). The present invention forms a product with air gaps. The circuit structure method provides a complete solution for semi-V body manufacturers that can reach mass production scale. ^ ^ ^ ^ ^ ^ ^ '[Previous technology] $$ half, the progress of body manufacturing technology, The design size of the half-V component fabricated on a semiconductor wafer has also been shrinking, and has evolved into female generations. However, the continuous increase in the density of integrated circuits has resulted in a time delay (RC between metal wires) The effect of the delay) problem on the performance of the mine road is becoming increasingly significant, especially when the process line width (Hne ta Ϊ π Γϊ I α Τ? ^ ^ ° · 13 ^ ^ ^ ^ ^ ^ ^ The effect of operating efficiency is even clearer. The time delay between i i Ϊ and 用 can be expressed by the product of the resistance of the metal wire (the product of the parasitic capacitance 斑 between the 10 metal wires. The current value is (3

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The gold line of the conductor chip: the first is to reduce the transmission speed of the connection. The internal connection time is lower. The resistance value of each metal wire is lower while reducing the electrical delay. The parasitic capacitance of the main metal material, Can consume. The metal wires are moved toward the two sides to increase the internal metal known practice. The parasitics between the metal wires is reduced. Materials such as FSG, HSQ, FLAREKt% Siu, and low-intermediate m Ai) are mainly used. The characteristics of these low dielectric constant materials need to include low dielectric constant, low surface conductivity (surface. 括 surfac ^ resistivity > 1〇1Ώ), low stress (coas' tensile > 30MPa), excellent Mechanical strength and thermal stability of chemical fish, low water absorption and process compatibility (pr〇cess c ^ p ^ ibi 1 ity). However, many low dielectric constant materials have serious reliabilities and problems with integration with metals. Therefore, before the new generation of low-dielectric-constant materials are available, how to overcome the problem of reduced operating efficiency caused by time delay with process technology has become a subject worthy of discussion and improvement. Since the ideal dielectric constant of air is close to 丨, the use of air (Mr), which is an insulating material for metal wiring, is also one of the solutions to reduce the parasitic capacitance between metal wires. Although many low dielectric constant applications that use air The technology of integrated circuits has been announced, but most of the ρ parts have no property value. For example, in US Patent No. 4 922 06 39, Lan Y. K. Yee disclosed a method of making air Spaced product circuit

200415704 V. Description of the invention (3) The method is to use photoresist as a temporary dielectric layer between the metal interconnects. After the metal interconnects are completed, some or even all of the light is removed by using a solvent. Resistance, and a large amount of air space is formed between the metal interconnects. This method will cause the metal interconnects to be almost completely overhead, and failing to obtain sufficient support ’will easily cause the integrated circuit to be damaged by mechanical forces. In addition, U.S. Patent No. 6 1 3 0 1 51 discloses a method of forming a silicon oxide layer with air spaced between metal interconnects. The method is to first form a silicon oxide layer and a silicon nitrogen layer on the metal layer. Then, a plurality of openings are defined on the nitrogen stone layer through a photolithography (photo 1 thogr aphy) process, and then an etching process is performed to sequentially etch the oxygen cutting layer and the nitrogen silicon layer or the silicon oxide only along the foregoing openings. Layer to form an air space within the silicon oxide layer. U.S. Patent No. 5,949,43 discloses a method for forming an air gap between metal interconnects. The method is to first form a double damascene metal link in a dielectric layer, and then deposit an etch stop layer (etchst ο p 1 ayer) on the Jinzhan connection and the dielectric layer, exposing a part of the dielectric layer, and finally performing an etching process to completely remove the dielectric layer not covered by the etching stopper layer for each metal connection An air gap is formed between the etch stop layers. Other methods, such as U.S. Patent Nos. 5 3 24683, 6 077767, 6 08 382 1 and 54 0 786 0, also disclose various methods for forming an air gap between metal interconnects, which are not described in detail here.

Page 9 200415704 V. Description of the invention (4) However, in addition to the above-mentioned conventional technologies, which are too complicated and difficult to integrate, they also face some reliability issues, such as the inability of metal interconnects to obtain sufficient support. The present invention can provide a complete solution to solve the bottleneck that the conventional technology cannot break through and reach a mass production scale. [Content] The main object of the present invention is to provide a high-efficiency integrated circuit structure and a manufacturing method thereof. Another object of the present invention is to provide an integrated circuit structure having an air gap and sufficient support and a manufacturing method thereof, so as to produce a large amount of air gaps between metal interconnects, thereby achieving the effect of reducing the time delay of the metal interconnects. . In accordance with the purpose of the present invention, a high-performance integrated circuit structure having both a large amount of air separation and sufficient support for the interconnected metal lines is first exposed. The integrated circuit structure includes a first layer of metal wire pattern formed on a bottom layer; a second layer of metal wire pattern formed on the first layer of metal wire pattern; a support structure formed on the first layer of metal Between the wire pattern and the second layer of metal wire pattern is used to support the second layer of metal wire pattern, wherein the supporting structure includes a dielectric layer subjected to anisotropic etching; and a cover layer

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Formed between the plurality of air spaces formed by the second layer of metal wire pattern. The invention also discloses a manufacturing method. In the preferred embodiment of the present invention, a bottom layer is formed on the bottom layer, and a first layer of metal wire pattern is formed on the bottom layer to form a second layer of metal wire pattern on the 4 dielectric layer. And a plurality of grooves of the second mask 'non-isotropic engraved part, while supporting the remaining line pattern support structure. The final process is to describe the method of a high-performance integrated circuit by covering each groove surface and a cover layer and covering each groove. The method first forms a first layer of metal wire patterns on a substrate. A dielectric layer is formed on the bottom layer, and a metal wire pattern is formed. The second metal wire pattern is then used to engrav the dielectric layer and the bottom layer, and a second metal layer is formed with a dielectric layer of < and a second metal wire pattern made of chemical vapor deposition (Cvd) is formed. Shen Chen formed a number of air gaps. _ As the present invention uses the metal layer pattern or the photoresist layer used to define the metal layer pattern as an etch mask, the dielectric layer under the metal layer pattern can be escaped by an isotropic coin and an anisotropy Neodymium engraving, in order to form a plurality of radon air spaces between the metal interconnected with the green, thereby achieving the effect of reducing the time delay of the metal interconnect. In addition, the integrated circuit structure formed by using the method of the present invention has a dielectric layer structure with sufficient support for metal interconnects or the like, which can improve the reliability of the integrated circuit. 【method of execution】

200415704

Structure of the present invention Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view of a integrated circuit structure having an air gap (a i r g a ρ) or an air suspension (a i r b r d g e) in a preferred embodiment of the present invention. As shown in FIG. 1, the semiconductor wafer 10 includes a substrate 11, which may be a single crystal silicon substrate or other semiconductor substrates. The surface of the substrate i 丄 may include semiconductor devices that have been fabricated, such as memory cells, MOS transistors, resistors, or capacitors. Since these elements are not the focus of the invention, they are not shown in the illustration. The bottom layer 12 is formed on the substrate, and the bottom layer 2 may be formed of a single dielectric layer, or may be formed of a plurality of dielectric layers. Three metal pattern layers (Ml, M2, and M3), metal plugs 24a and 26a, and dielectric layers 24, 26, and 28 are formed on the bottom layer 12 to form a stacked metal inner speed line structure. . Here, the 'metal pattern layer (M1, µ2, and M3) is a gold-alloy wire pattern defined in the same layer. The metal wire patterns (M1, M2, and M3) and metal plugs 2 4 a and 2 6 a can be defined by traditional metal sputtering and etching techniques, and the dielectric layers 2 4, 2 6, and 2 8 can be obtained by using < Normally formed by chemical vapor deposition or spin coating. In FIG. 1, air gaps 22a and 22b are formed between the metal pattern layer M2, and extend downward to the dielectric layer 24, and even extend downward to the bottom layer 12. The air gaps 23 a and 23 b are formed between the metal pattern layers M3 and extend downward to the dielectric layer 26. The air gaps 22a and 2 2b are formed by covering the dielectric layer 26, and a protrusion is formed on the top of the air gap 2 2b.

Page 12 200415704 V. Description of the invention (7) ---- Overhang # p Yue, · _ Acoustic 28 Solu 5 closed structure. The air gaps 23a and 23b are made of a dielectric dual energy, ^ 彳 f >. The air gap 22a is in communication with the air gap 23a. In the process of forming the air gap 2 3 a, the anisotropic name ^ ^ > The air gap 2 2 a covered with the dielectric layer 2 6. In the eighth example of the present invention, the air gap 2 2 a which has been cut through can be closed again with the dielectric layer 28 to form two independent air gaps 22 a and 2 3 a. This can be achieved by adjusting the degree of step coverage when the dielectric layer 28 is deposited. Embodiment 1 Please refer to FIGS. 2 to 6. FIGS. 2 to 6 are schematic diagrams of a method for fabricating an integrated circuit structure with an air gap according to the present invention. As shown in FIG. 2, the wafer 100 includes a substrate and a bottom layer j 2 on the substrate j k. The first layer of gold pattern 13 may be formed on the bottom layer 12 by sputtering, lithography, and etching processes. Next, a dielectric layer 14 is deposited on the first layer of metal pattern 3 and the bottom layer 12, and then a metal plug is formed in the dielectric layer 14 through processes such as photolithography, etching, deposition, and chemical mechanical polishing (CMP). 13a. Subsequently, a metal layer 15 is formed on the dielectric layer 14 and the metal plug 13a, and a defined photoresist layer 16 is formed on the surface of the metal layer 15. The photoresist layer 16 defines a second metal pattern on the metal layer 15. Next, as shown in FIG. 3, the photoresist layer 16 is used as an etching mask to etch the metal layer 丄 5 to form a second metal pattern 17 on the dielectric layer 14 and the metal plug 1 3a. , And use the metal plug 1 3 a as the contact plug (via

Page 13 200415704 V. Description of the invention (8) plug) is electrically connected to the first layer of metal pattern 13. The photoresist layer 16 is subsequently removed. The first metal layer pattern 13 and the second metal pattern 17 may be made of aluminum metal, aluminum copper alloy, or copper metal. The metal plug 13a may be composed of tungsten (W), titanium / titanium nitride (T i / T i N). The composition of the dielectric layer 14 can be silicon dioxide, fluorinated silicate glass (FSG), or other plasma-enhanced chemical vapor deposition (PECVD) or high-density A dielectric layer formed by high-density plasma chemical vapor deposition (HDPCVD). It should be emphasized that the integrated circuit structure with air separation of the present invention can also be applied to copper metal interconnect structure. At this time, the above-mentioned first layer metal pattern 1 3, metal plug 13a and second layer metal pattern 17 may also be formed in the dielectric layer by a dual damascene (d u a 1 d a m a s c ene) process. The double inlay funeral process is a technique well known to those skilled in the art, so it will not be repeated here. Those skilled in the art should refer to the present invention and easily apply the present invention to the copper process. As shown in FIG. 4 ', the second layer of metal pattern 17 is used as a mask for money engraving, and an isotropic etching process is performed, and a pre-sphericity is not removed. The dielectric layer 14 covered by 7 forms a plurality of grooves 18 within the dielectric layer 14. Among them, by controlling the time-mode of etching, the depth of the groove extending into the bottom layer 2 can be appropriately adjusted, but the depth of this groove is not to affect the electrical performance of the device.

200415704

Then, as shown in FIG. 5, the dielectric layer 丨 4 in the groove 丨 8 is subjected to an isotropic dry etching or wet etching process to further expand the area of the concave sample 18. An undercut profile is under the first metal pattern 17. It should be noted that the aforementioned isotropic etching process is an optional step, that is, the isotropic etching process may be omitted and not performed. On the other hand, the main purpose of performing the isotropic etching process is However, the area of the grooves 18 is selectively enlarged, so the dielectric layer 14 under the second metal pattern 17 is only partially removed. The supporting structure for supporting the second metal pattern 17 includes a dielectric layer 14 and a metal plug 13a. As shown in FIG. 5 and FIG. 6, a chemical vapor deposition (CVD) process is then performed, and a cap layer 19 is deposited on the surface of the groove 18 and the second metal wire pattern 17, and then capped. The grooves 18 are held to form a plurality of air gaps 18a. It is worth noting that, when the cover layer 19 is deposited, it is necessary to make the cover layer 19 overhang at the corner portion of the second layer metal wire pattern 17 by adjusting the process parameters of chemical vapor deposition as much as possible. Quickly cover the groove 18, thereby reducing the deposition of the cover layer 19 into the groove 18. Embodiment 2 Please refer to FIG. 7 and FIG. 8. FIG. 7 and FIG. 8 show another embodiment of the present invention. Schematic of the process method. Among them, Figure 7 is a continuation of the steps shown in Figure 2.

200415704 V. Description of the invention (10) Step: After exposure, development, and etching processes, a second metal pattern 17 is formed on the dielectric layer 14 and the metal plug 13a, and the second layer is not removed to define the second layer. Photoresist layer 16 of metal pattern 17. As shown in FIG. 8, the method of the present invention can sequentially perform the anisotropic etching and isotropic etching processes shown in FIG. 4 and FIG. 5 using the photoresist layer 16 as a mask of the last name. After the metal layer 15 is etched, Then, a plurality of grooves 1 g are formed in the dielectric layer 14, and the groove 18 forms an undercut profile under the second layer metal pattern 17. That is, after the second metal pattern 7 is completed, the composition of the etching gas is then adjusted to etch the dielectric layer 14 in-situ at the same time. Finally, the photoresist layer 16 is removed, and a chemical vapor deposition (CVD) process shown in FIG. 6 is performed, and a cap layer (cap 1 ay er) 19 is deposited on the surface of the groove 18 and the second metal wire pattern 17 , Cover the groove 18 and open a plurality of air intervals 18a. Embodiment 3 According to the present invention, the manufacturing method of the air gap ISa shown in FIGS. 4, 5 and 8 can be implemented in any two layers of the multi-metal interconnection process. It is a pattern layer or each layer of metal. Pattern layer. Please refer to FIG. 9, after three consecutive metal pattern layers (MV, M2, and M3) and each metal plug 13a are successively made, the uppermost metal pattern layer M3 is used as an etching mask, which belongs to the f-case layer M2. And the metal pattern layer M1 is used as a stop layer for non-specificity to carry out non-specificity | insect engraving, and a large 1 two-air groove 18 is made between the multiple metal interconnects. In addition, as shown in FIG. 10, in the present invention, a barrier layer (s t op 1 ay er) 1 2a can be added to the bottom layer 12 so that it can be avoided.

200415704 V. Description of the invention (π) Excessive etching will damage the components under the bottom layer 12. Embodiment 4 In order to prevent the gap between the wires in the second layer metal pattern 17 shown in FIG. In this case, the volume of the air gap 18a decreases, and a dummy pattern can be formed in a region with a large gap between the metal wires. Please refer to Fig. 11 to Fig. 14. Fig. 11 to Fig. 14 are schematic diagrams for making air gaps on metal inner wires with excessively large gaps between the wires. Firstly, as shown in FIG. 11, when the space between the wires of the second metal pattern 17 is too large, the present invention can appropriately add a dummy pattern 14 to the dielectric layer 14 in the space between the wires that is too large. on. Wherein, the method of forming the dummy pattern 17 a can add a plurality of dummy patterns to the layout of the mask of the second layer of the metal pattern 17, so that the second layer of the gold pattern 17 and the dummy pattern 17 a form a dielectric at the same time ^ Dielectric Above the layer 14, the space and gap between the wires of the second metal pattern 17 are reduced. Then sequentially perform the anisotropic engraving, isotropic coin engraving, and Beixue vapor deposition processes shown in Figs. 4 to 6 in order to form a plurality of air spaces 1 8a in the dielectric layer] 4 as shown in the figure. Twelve. As shown in FIG. 13, when the space between the wires of the second metal pattern 7 is large, the method of the present invention can also deposit a thin film layer (not shown) on the first layer after forming the second metal pattern 17. On top of the two-layer metal pattern 丨 7, an etching process is used to form a sidewall on the side of the second-layer metal pattern 丨 7

Page 17 200415704 V. Description of the invention (12) Spacer 17b. Among them, the method of forming the side wall i7b is well-known to those skilled in the art ', so it will not be described again. Due to the formation of the side walls 17b, the space between the leads is reduced. Then, the anisotropic last name engraving, isotropic etching, and chemical vapor deposition processes shown in FIGS. 3 to 5 are sequentially performed to form a plurality of air gaps i8a in the dielectric layer 14. As shown in the figure, the second layer of metal and metal is carried forward. Fourteen copies of the pattern metal pattern are removed by light. As shown in the figure, 17-17 are used. Electricity, when the first method is also on the photoresist layer, or using the 20 cover layer 20 shown in the shape of the 17 space, two metal patterns in the layer 14 can be formed after the 20th cover is formed on the wire, and only the photoresist layer of the wire is exposed. 2 0 in the dielectric layer 14 forming at least one virtual non-specific money and performing a plurality of voids 17 between the wires formed in FIG. 6 through the two-layer metal pattern 17 The second pattern with a small gap between the two layers of the second ^ leads is too large. Then, the engraved and specific surnames are engraved in order to form a plurality of troughs 18. The CVD gas-making interval 18a is shown. Compared with the conventional method, the present invention is characterized by directly using the metal wire pattern or the photoresist layer for defining the metal wire pattern as an etching mask to perform an isotropic treatment of the dielectric layer under the metal wire pattern. Anisotropic etching and an anisotropic etching are used to form a plurality of air spaces between the metal interconnects, thereby achieving the effect of reducing the time delay of the metal interconnects. There is an interlayer dielectric (i nt 1 ay er dielectric) directly underneath each metal wire, so that the metal interconnects have sufficient support. Method of the invention

Page 18 200415704 V. Description of the invention (13) The air gap formed can be made at the same time as the definition of each layer of metal wire pattern, or after several layers of metal wire pattern are completed, the metal wire pattern of each layer is used as an etching mask once. Etching to form a large number of air gaps in the integrated circuit, and at the same time, sufficient support of the dielectric layer can be obtained under each layer of metal wire pattern. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the patent of the present invention. End of chapter

Page 19 200415704 Simple illustration of the drawing Simple illustration of the drawing Large gap of the product. . The air gap in the graph is empty. The air of mind, mind, and air, or the space of the figure, shows the space between the lines of the law, the square, and the air plane. The medium-range distance is separated from the air shape by the air-conditioning system. The knot is good. For example, there are two examples: the road is compared with the plan, the intention is to implement electricity, the entity is expressly stated that the system of air quality and accumulation is issued for this purpose. Make eighty graphs • 1 This graph of Γ is perfect. For the road to the road, the first and second tiers are shown in the diagram. Figures, diagrams, diagrams, diagrams, and symbols in the diagrams. 10 semiconductor wafers 11 substrates 12 bottom layers 13 first layers of gold 13a metal plugs 14 dielectric layers 15 Second layer of metal 16 Photoresist layer 17 Second layer of metal pattern 17a Dummy pattern 17b Side wall 18 Pore 18a Air gap 19 Cover layer 20 Photoresist layer 22a Air gap 2 2 b Air gap 23a Air gap 23b Air gap 24 Electrical layer

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Claims (1)

200415704 VI. Scope of patent application 1. An integrated circuit structure with an air gap, comprising: a substrate having a bottom layer thereon; a first layer of metal wire pattern formed on the bottom layer; a second layer of metal wire A pattern formed on the first layer of metal wire pattern; a support structure formed between the first layer of metal wire pattern and the second layer of metal wire pattern to support the second layer of metal wire pattern, wherein the The support structure includes a dielectric layer subjected to isotropic etching; and a plurality of air gaps formed by a capping layer, formed between the second metal wire patterns. 2. For the integrated circuit structure of item 1 in the scope of patent application, wherein the substrate is a shixi substrate. 3. For the integrated circuit structure of item 1 of the patent application scope, wherein the first layer of metal wire pattern and the second layer of metal wire pattern are made of copper. 4. For example, the integrated circuit structure of the first scope of the patent application, wherein the first layer of metal wire pattern and the second layer of metal wire pattern both include metal. 5. If the integrated circuit structure of item 1 of the patent application scope, wherein the supporting junction Page 22 200415704 6. Scope of patent application The structure further includes at least one contact plug (v i a p 1 ug) electrically connecting the first layer of metal wire pattern and the second layer of metal wire pattern. 6 · The integrated circuit structure according to item 1 of the patent application scope, wherein the capping layer is formed by plasma-enhanced CVD (PECVD) or high-density plasma chemical vapor deposition (h igh) dens i ty p 1 asma CVD (HDPCVD). 7. The integrated circuit structure according to item 1 of the patent application scope, wherein the support structure of the second layer of metal wire pattern has an undercut profile. 8 · -Integrated electric junction with air gap ^ A first layer of metal wire pattern is formed on a bottom layer; a second layer of metal wire pattern is formed on the first layer of metal wire pattern: a square support A structure formed between the first and second metal wire patterns to support the second metal wire pattern; and V is formed by a plurality of air gaps formed by a cover layer on the second A metal wire pattern between. 9. The integrated circuit structure according to item 8 of the scope of patent application, wherein the support structure includes at least one contact plug (V i a p ug) electrically connected to the first layer of gold metal layer and the second layer of metal wire pattern. Page 23 200415704 VI. Scope of patent application 10. For example, the integrated circuit structure of item 8 of the scope of patent application, wherein the support structure includes a dielectric layer that has been subjected to isotropic #etching. 1 1. The integrated circuit structure according to item 8 of the scope of patent application, wherein the second layer of metal wire patterns includes a dummy pattern to reduce the gap between the metal wires of the second layer of metal wire patterns. 12. The integrated circuit structure according to item 8 of the scope of patent application, wherein the second-layer metal wire pattern includes a sidewall formed on each side wall of the second-layer metal wire pattern. 1 3. The integrated circuit structure according to item 8 of the patent application scope, wherein the cap layer is formed by plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD). 14. A manufacturing method of an integrated circuit with air gaps, the manufacturing method comprising: providing a substrate having a bottom layer thereon; forming a first layer of metal wire pattern on the bottom layer; and forming the first layer of metal wire on the bottom layer Forming a dielectric layer on the pattern and the bottom layer; forming a second metal wire pattern on the dielectric layer; using the second metal wire pattern and using the second metal wire pattern as an etch mask, etc. The dielectric layer is etched to form a plurality Page 24 200415704 6. Apply for a patent for a groove, and at the same time make the remaining dielectric layer constitute the supporting structure of the second metal wire pattern; and perform a chemical vapor deposition (CVD) process for the groove A cover layer is deposited on the surface and the second metal wire pattern to cover the groove and form a plurality of air spaces. For the base method of the base method = °, the method made by the French party 4 IX Fan Fan special application, such as the foundation silicon Fan Fan special application, such as in the inlay system diagram line gold guide layer The system of Lo Γ ® of item 4 is called the bottom 4 and the first fan is requested to apply for the gold layer in the inlay system. The second method is to make the upper layer. Please refer to the application and guideline of the plan drawing. 8 IX 0 ^^ Gold-Layer I Item 4 of its legal system. The copper structure of the structure is the guideline of the plan guideline gold layer. Li is requested to apply as directed and guide to the plan. 9 1 Items that are made by the French party 4 Items that are made of gold and aluminum, including gold and aluminum, which are included in the case series, are drawn by the gold layer, and items that are made by the French party 4 11 Please apply as ο 2 Page 25 200415704 6. The scope of the patent application includes anisotropic etching of the second layer of metal wire pattern after the dielectric layer and the bottom layer to form an undercut pattern. Enlarge the area of the groove. 2 1. A method for manufacturing an integrated circuit with an air gap, comprising: providing a substrate having a bottom layer thereon; forming a dielectric layer on the bottom layer; forming a metal wire pattern on the dielectric layer And using the metal wire pattern as an etching mask to etch the dielectric layer to a predetermined depth so as to form a plurality of grooves in the dielectric layer, while making the remaining dielectric layer constitute the metal wire pattern. supporting structure. 2 2. The production method according to item 21 of the scope of patent application, wherein the metal wire pattern forms a plurality of interl ine space gaps on the dielectric layer, and the plurality of grooves are formed in the dielectric layer. In the dielectric layer in the space between the plurality of wires. 2 3. The manufacturing method according to item 21 of the patent application scope, wherein the method of etching the dielectric layer uses an anisotropic lasting technique. 24. The method of claim 21, wherein the metal wire pattern is embedded on the dielectric layer. 25. The manufacturing method according to item 21 of the scope of patent application, wherein the manufacturing method Page 26 200415704 6. The scope of applying for a patent after etching the dielectric layer further includes the following steps: Isotropic (is 〇tr ο pic) money engraving the support #structure of the metal wire pattern to form an undercut wheel Undercut profile, expanding the area of the groove; and performing a chemical vapor deposition (CVD) process to deposit a cap layer (cap 1 ayer) on the groove surface and the metal wire pattern At the same time, the groove is covered to form a plurality of air gaps. Page 27