CN102891100B - Shallow-trench isolation structure and formation method thereof - Google Patents
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- CN102891100B CN102891100B CN201110207818.7A CN201110207818A CN102891100B CN 102891100 B CN102891100 B CN 102891100B CN 201110207818 A CN201110207818 A CN 201110207818A CN 102891100 B CN102891100 B CN 102891100B
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Abstract
The invention provides a shallow-trench isolation structure and a formation method thereof. The formation method comprises the following steps of: forming a corrosion barrier layer on a semiconductor substrate; etching the corrosion barrier layer and the semiconductor substrate to form a groove; and forming protective layers on the surface of the corrosion barrier layer, and the side wall and the bottom of the groove; filling medium materials in the groove with the protective layer to form medium layers; forming a molecular sieve on the medium layers; introducing reaction gas to the medium layers through the molecular sieve to move all the medium layers so as to form an air gap in the groove; and forming an insulating medium layer on the molecular sieve. A manufacturing method of the shallow-trench isolation structure disclosed by the technical scheme has a simple process and a lower cost.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly a kind of shallow groove isolation structure and forming method thereof.
Background technology
In process for fabrication of semiconductor device, device isolation is an important research topic.Shallow-trench isolation technology has been widely used in the integrated circuit technology of below 0.25 nanometer, and shallow groove isolation structure compares carrying out local oxide isolation structure, has and occupies the less advantage of silicon area, thus improves the integrated level of device on unit silicon chip.
The method of usual formation shallow groove isolation structure is as follows: be formed with the surface of silicon formation photoresist layer of oxide layer, polysilicon layer, silicon nitride layer successively, the pattern of described photoresist layer is corresponding with shallow trench; With described photoresist layer for mask, etch nitride silicon layer, polysilicon layer, oxide layer and silicon substrate, form groove in silicon substrate successively; Adopt high-density plasma equipment to fill dielectric in described groove and form dielectric layer on described silicon nitride layer surface; With dielectric layer described in chemical mechanical polishing method (Chemical Mechanical Polishing, CMP) planarization until expose silicon nitride layer surface, thus form shallow groove isolation structure.
But, in actual process, directly acquired a certain degree of difficulty by high-density plasma growth method (HDP) filling groove tool, common way first in groove, forms one deck polysilicon (Poly) layer groove is shoaled, and then form oxide layer on the polysilicon layer by high-density plasma growth method.Further, also directly oxide layer can be formed in groove by high-aspect-ratio growth method (HARP).
Also disclosing a kind of method by forming airspace in groove in prior art and make shallow groove isolation structure, with reference to figure 1, is a kind of schematic flow sheet forming the specific implementation method of shallow groove isolation structure in prior art.Particularly, described technological process comprises the steps, step S1: provide Semiconductor substrate, in Semiconductor substrate, form groove; Step S2: form the first oxide layer in the bottom of semiconductor substrate surface and groove and sidewall; Step S3: form dielectric layer in groove, the material of described dielectric layer is can ashing material; Step S4: form the second oxide layer on dielectric layer; Etch the second oxide layer to form side wall; Step S5: pass into reacting gas to remove dielectric layer through side wall; Step S6: form the 3rd oxide layer by non-conformal chemical vapour deposition technique around semiconductor substrate surface and side wall.
But the technological process of said method is complicated, and along with the continuous reduction of dimensions of semiconductor devices, dielectric layer forms method very difficult control in actual process of side wall.Meanwhile, in formation oxide layer process, in order to avoid the residue on side wall falls in groove, need around semiconductor substrate surface and side wall, to form oxide layer, complex manufacturing technology by non-conformal chemical vapour deposition technique.
More technical schemes about formation shallow groove isolation structure can be the patent application document of 200910196128.9 with reference to Chinese Patent Application No..
Summary of the invention
The problem that the present invention solves is to provide a kind of simple process and forms shallow groove isolation structure.
For solving the problem, the invention provides a kind of formation method of shallow groove isolation structure, comprising the steps: to form corrosion barrier layer on a semiconductor substrate; Etch described corrosion barrier layer and Semiconductor substrate, form groove; Protective layer is formed in the sidewall of the surface of described corrosion barrier layer and groove, bottom; Filled media material in the described groove being formed with protective layer, forms dielectric layer; Described dielectric layer forms molecular sieve; Pass into reacting gas through described molecular sieve to described dielectric layer, to remove whole dielectric layer, thus form airspace in described groove; Described molecular sieve forms insulating medium layer.
Alternatively, the method described dielectric layer forming molecular sieve comprises: spin coating reaction material on described dielectric layer; Heat to separate out molecular sieve crystal to the reaction material of described spin coating; Clean the reaction material after described heating, form molecular sieve.
Alternatively, described reaction material comprises silicon-containing compound, aluminum contained compound, alkali and water.
Alternatively, described dielectric material is one or more the dielectric material in carbon containing, nitrogen, hydrogen.
Alternatively, be oxygen through molecular sieve to the reacting gas that dielectric layer passes into.
Alternatively, the material of described molecular sieve is silicate or the alumino-silicate of crystalline state.
Alternatively, the described corrosion barrier layer of described etching and Semiconductor substrate, the method forming groove is dry etching.
Alternatively, the parameter of described dry etching is as follows: reacting gas comprises HBr, NF
3and O
2, wherein HBr and NF
3ratio be 1: 1, reaction pressure is 50-100mTorr, power is 500W-1500W.
Alternatively, the material of described protective layer comprises oxygenatedchemicals.
Alternatively, the method described molecular sieve being formed insulating medium layer is chemical vapour deposition technique.
Alternatively, the material of described corrosion barrier layer is silicon nitride.
Present invention also offers a kind of shallow groove isolation structure, comprising: Semiconductor substrate; Be positioned at the corrosion barrier layer in described Semiconductor substrate; Be positioned at the groove of described Semiconductor substrate and corrosion barrier layer, there is filling part groove to form the molecular sieve of airspace in groove in described groove; Be positioned at the insulating medium layer on described molecular sieve.
Alternatively, the material of described molecular sieve is silicate or the alumino-silicate of crystalline state.
Alternatively, the material of described corrosion barrier layer is silicon nitride.
Alternatively, also protective layer is formed with in the sidewall of the surface of described corrosion barrier layer and described groove, bottom.
Compared with prior art, the technical program has the following advantages: first in Semiconductor substrate, form groove, then filled media material in described groove, forms dielectric layer; Described dielectric layer forms molecular sieve; Pass into reacting gas through described molecular sieve to described dielectric layer, remove whole dielectric layer, form airspace; Finally, described molecular sieve forms insulating medium layer.Form shallow groove isolation structure by technical scheme of the present invention, manufacture craft is simple, and the technics comparing forming molecular sieve on dielectric layer easily controls, and passes into reacting gas removal dielectric layer through molecular sieve, and the effect forming airspace in groove is better.
Further, the method forming molecular sieve on dielectric layer is adopted to instead of the method forming side wall in prior art on dielectric layer, therefore, during the follow-up insulating medium layer of formation over a molecular sieve, only need just can be realized by common chemical vapour deposition technique, and do not need to form oxide layer by non-conformal chemical vapour deposition technique, manufacture craft is simple.
Accompanying drawing explanation
Fig. 1 is a kind of schematic flow sheet forming the specific implementation method of shallow groove isolation structure in prior art;
Fig. 2 is a kind of schematic flow sheet forming the specific implementation method of shallow groove isolation structure provided by the invention;
Fig. 3 to Fig. 9 is the cross-sectional view that the present invention forms the specific embodiment of shallow groove isolation structure.
Embodiment
Inventor finds in the prior art, forms the technique of shallow groove isolation structure more complicated, and constantly reduces along with the size of semiconductor device, and dielectric layer is formed method very difficult control in actual process of side wall.Meanwhile, in formation oxide layer process, in order to avoid the residue on side wall falls in groove, need around semiconductor substrate surface and side wall, to form oxide layer, complex manufacturing technology by non-conformal chemical vapour deposition technique.For the problems referred to above, inventor is through research, and provide a kind of shallow groove isolation structure and forming method thereof, its manufacture craft is simple.
In order to make those skilled in the art can better understand the present invention, describe shallow groove isolation structure of the present invention and forming method thereof in detail below in conjunction with accompanying drawing and specific embodiment.
Fig. 2 is a kind of schematic flow sheet forming the specific implementation method of shallow groove isolation structure provided by the invention.With reference to figure 2, the method for the formation shallow groove isolation structure of the specific embodiment of the invention comprises:
Step S11: form corrosion barrier layer on a semiconductor substrate;
Step S12: etch described corrosion barrier layer and Semiconductor substrate, forms groove;
Step S13: form protective layer in the sidewall of the surface of described corrosion barrier layer and groove, bottom;
Step S14: filled media material in the described groove being formed with protective layer, forms dielectric layer;
Step S15: form molecular sieve on described dielectric layer;
Step S16: pass into reacting gas to described dielectric layer through described molecular sieve, to remove whole dielectric layer, thus forms airspace in described groove;
Step S17: form insulating medium layer on described molecular sieve.
Further, be the cross-sectional view of the specific embodiment of formation shallow groove isolation structure of the present invention as Fig. 3 to Fig. 9, in conjunction with the method for formation shallow groove isolation structure describing the specific embodiment of the invention with reference to figure 2 and Fig. 3 to Fig. 9 in detail.
In conjunction with referring to figs. 2 and 3, perform step S11, Semiconductor substrate 20 is formed corrosion barrier layer 21.In embodiments of the present invention, the material of described Semiconductor substrate 20 can be the III-V such as monocrystalline silicon, germanium silicon, silicon-on-insulator or GaAs.The material of described corrosion barrier layer 21 is silicon nitrides, but is not limited to silicon nitride in practical application.
Alternatively, the method that Semiconductor substrate 20 is formed corrosion barrier layer 21 is chemical vapour deposition technique or physical vaporous deposition, but is not limited to said method.The effect of described corrosion barrier layer 21 is as etching stop layer in subsequent technique, is not damaged to protect Semiconductor substrate 20.Such as, when the protective layer of continuous formation after etching or insulating medium layer, can using described corrosion barrier layer 21 as etching stop layer.
In conjunction with reference to figure 2 and Fig. 4, perform step S12, etch described corrosion barrier layer 21 and Semiconductor substrate 20, form groove 22.In embodiments of the present invention, adopt dry etching method to etch described corrosion barrier layer 21 and Semiconductor substrate 20, form groove 22.Wherein, the parameter of described dry etching is as follows: reacting gas comprises HBr, NF
3and O
2, wherein HBr and NF
3ratio be 1: 1, reaction pressure is 50-100mTorr (millitorr), power is 500-1500W (watt).
The concrete technology forming groove 22 is as follows: on described corrosion barrier layer 21, apply photoresist layer (not shown), through photoetching process, photoresist layer defines groove figure; With described photoresist layer for mask, etch described corrosion barrier layer 21 and Semiconductor substrate 20 along groove figure, form groove 22.Alternatively, the width of the described groove formed is 65nm (nanometer), the degree of depth is 1.8 μm (microns), but be not limited to above-mentioned width and the degree of depth, according to different technological requirements, those skilled in the art can form the groove of different in width and the degree of depth by the technological parameter changing dry etching.
In conjunction with referring to figs. 2 and 5, perform step S13, form protective layer 23 in the sidewall of described corrosion barrier layer 21 surface and groove 22, bottom.In embodiments of the present invention, the effect of described protective layer 23 makes follow-up formation in described groove 22 in the process of airspace, and the reacting gas passed into can not react with described Semiconductor substrate 20.Alternatively, the material of described protective layer 23 comprises oxygenatedchemicals, but is not limited to above-mentioned material.
In conjunction with referring to figs. 2 and 6, perform step S14, filled media material in described groove 22, formed dielectric layer 24.Because described dielectric layer 24 needs to be entirely removed in subsequent step, usually select the material easily removed, in embodiments of the present invention, described dielectric material is one or more the dielectric material in carbon containing, nitrogen, hydrogen.Particularly, such as, described dielectric layer 24 is amorphous carbon, diamond-like-carbon (Diamond-like carbon, DLC) etc., but is not limited to above-mentioned material.
The method forming described dielectric layer 24 can be chemical vapour deposition technique or physical vaporous deposition, but is not limited to above-mentioned two kinds of methods in actual process.
In conjunction with reference to figs. 2 and 7, perform step S15, described dielectric layer 24 forms molecular sieve 25.In the present embodiment, described molecular sieve 25 is silicate or the alumino-silicate of crystalline state.
Particularly, the step forming molecular sieve 25 comprises: first, spin coating reaction material on described dielectric layer 24, described reaction material comprises: silicon-containing compound (waterglass, Ludox etc.), aluminum contained compound (hydrated alumina, aluminium salt etc.), alkali (NaOH, potassium hydroxide etc.) and water; Heat to separate out molecular sieve crystal to the reaction material of described spin coating, i.e. the silicate of crystalline state or alumino-silicate; Finally clean the reaction material after described heating, wash away other reactants, form molecular sieve 25.It should be noted that, in actual applications, the method forming molecular sieve 25 is not limited thereto.
In conjunction with reference to figure 2 and Fig. 8, perform step S16, pass into reacting gas through described molecular sieve 25 to described dielectric layer 24, to remove whole dielectric layer 24, thus form airspace 24 ' in described groove 22.In embodiments of the present invention, be oxygen through molecular sieve 25 to the reacting gas that dielectric layer 24 passes into.
Material due to described dielectric layer 24 comprises one or more the dielectric material in carbon, nitrogen, hydrogen, correspondingly, these materials above-mentioned and oxygen reaction can form gas (such as carbon dioxide, nitrogen dioxide, steam etc.), easy removal, thus in the formation airspace, space 24 ' that described dielectric layer 24 occupies originally.Particularly, because molecular sieve 25 has micropore usually, high-octane oxygen gas plasma is passed into dielectric layer 24 through described molecular sieve 25, described high-octane oxygen gas plasma is by the micropore in molecular sieve 25, arrive face, described dielectric layer 24 place, and react with described dielectric layer 24, remove whole dielectric layer 24.Meanwhile, owing to being formed with protective layer 23 in the bottom of groove and sidewall, and oxygen gas plasma and described protective layer 23 do not react, and are so originally positioned at the formation air gap, position 24 ' of the dielectric layer 24 of groove.
In conjunction with referring to figs. 2 and 9, perform step S17, described molecular sieve 25 forms insulating medium layer 26.In embodiments of the present invention, the method described molecular sieve 25 forming insulating medium layer 26 is chemical vapour deposition technique.Compared with prior art, owing to instead of side wall by molecular sieve 25, when therefore forming insulating medium layer 26 on described molecular sieve 25, only need by common chemical vapour deposition technique, manufacture craft is simple.Alternatively, the material of described insulating medium layer 26 comprises oxide, nitride, but is not limited to above-mentioned material.
Continue with reference to figure 9, define a kind of shallow groove isolation structure of the embodiment of the present invention according to above-mentioned process, comprising: Semiconductor substrate 20; Be positioned at the corrosion barrier layer 21 in described Semiconductor substrate 20, the material of wherein said corrosion barrier layer 21 can be silicon nitride, but is not limited to described material; Be positioned at the groove of described Semiconductor substrate 20 and corrosion barrier layer 21, have filling part groove in described groove to form the molecular sieve 25 of airspace 24 ' in groove, the material of wherein said molecular sieve 25 is silicate or the alumino-silicate of crystalline state; Be positioned at the insulating medium layer 26 on described molecular sieve 25.
Further, protective layer 23 is also formed with in the sidewall of the surface of described corrosion barrier layer 21 and groove, bottom.Alternatively, the material of described protective layer is oxygenatedchemicals, but is not limited to above-mentioned material.The effect of described protective layer 23 is when forming airspace 24 ' in groove, and the reacting gas and the Semiconductor substrate 20 that prevent from passing into groove react.
The shallow groove isolation structure that the embodiment of the present invention provides, manufacture craft is simple, and the technics comparing forming molecular sieve on dielectric layer easily controls, and passes into reacting gas removal dielectric layer through molecular sieve, and the effect forming airspace in groove is better.Meanwhile, by using molecular sieve to instead of existing side wall, when therefore forming insulating medium layer over a molecular sieve, only need common chemical vapour deposition technique just can realize, manufacture craft is simple.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (13)
1. a formation method for shallow groove isolation structure, is characterized in that, comprise the steps:
Form corrosion barrier layer on a semiconductor substrate;
Etch described corrosion barrier layer and Semiconductor substrate, form groove;
Protective layer is formed in the sidewall of the surface of described corrosion barrier layer and groove, bottom;
Filled media material in the described groove being formed with protective layer, forms dielectric layer;
Described dielectric layer forms molecular sieve;
Pass into reacting gas through described molecular sieve to described dielectric layer, to remove whole dielectric layer, thus form airspace in described groove;
Described molecular sieve forms insulating medium layer,
Wherein, the material of described protective layer comprises oxygenatedchemicals, and described protective layer does not react with described reacting gas for the protection of described Semiconductor substrate.
2. the formation method of shallow groove isolation structure according to claim 1, is characterized in that, the method that described dielectric layer is formed molecular sieve comprises:
Spin coating reaction material on described dielectric layer;
Heat to separate out molecular sieve crystal to the reaction material of described spin coating;
Clean the reaction material after described heating, form molecular sieve.
3. the formation method of shallow groove isolation structure according to claim 2, is characterized in that, described reaction material comprises silicon-containing compound, aluminum contained compound, alkali and water.
4. the formation method of shallow groove isolation structure according to claim 1, is characterized in that, described dielectric material comprise in carbon, nitrogen, hydrogen one or more.
5. the formation method of shallow groove isolation structure according to claim 1, is characterized in that, is oxygen through molecular sieve to the reacting gas that dielectric layer passes into.
6. the formation method of shallow groove isolation structure according to claim 1, is characterized in that, the material of described molecular sieve is the silicate of crystalline state or the alumino-silicate of crystalline state.
7. the formation method of shallow groove isolation structure according to claim 1, is characterized in that, the described corrosion barrier layer of described etching and Semiconductor substrate, and the method forming groove is dry etching.
8. the formation method of shallow groove isolation structure according to claim 7, is characterized in that, the parameter of described dry etching is as follows: reacting gas comprises HBr, NF
3and O
2, wherein HBr and NF
3ratio be 1:1, reaction pressure is 50-100mTorr, power is 500-1500W.
9. the formation method of shallow groove isolation structure according to claim 1, is characterized in that, the method that described molecular sieve is formed insulating medium layer is chemical vapour deposition technique.
10. the formation method of shallow groove isolation structure according to claim 1, is characterized in that, the material of described corrosion barrier layer is silicon nitride.
11. 1 kinds of shallow groove isolation structures, is characterized in that, comprising: Semiconductor substrate; Be positioned at the corrosion barrier layer in described Semiconductor substrate; Be positioned at the groove of described Semiconductor substrate and corrosion barrier layer, there is filling part groove to form the molecular sieve of airspace in groove in described groove; Be positioned at the insulating medium layer on described molecular sieve; also protective layer is formed with in the sidewall of the surface of described corrosion barrier layer and described groove, bottom; the material of described protective layer is oxygenatedchemicals, and described protective layer is injury-free when forming airspace for the protection of described Semiconductor substrate.
12. shallow groove isolation structures according to claim 11, is characterized in that, the material of described molecular sieve is the silicate of crystalline state or the alumino-silicate of crystalline state.
13. shallow groove isolation structures according to claim 11, is characterized in that, the material of described corrosion barrier layer is silicon nitride.
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| CN111009497B (en) * | 2019-12-31 | 2021-07-06 | 长春理工大学 | High-thermal-conductivity semiconductor substrate and preparation method and application thereof |
| CN112736026B (en) * | 2021-01-12 | 2022-05-06 | 度亘激光技术（苏州）有限公司 | Method for forming semiconductor structure |
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| US5461003A (en) * | 1994-05-27 | 1995-10-24 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
| US6677209B2 (en) * | 2000-02-14 | 2004-01-13 | Micron Technology, Inc. | Low dielectric constant STI with SOI devices |
| US6287979B1 (en) * | 2000-04-17 | 2001-09-11 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer |
| US6265321B1 (en) * | 2000-04-17 | 2001-07-24 | Chartered Semiconductor Manufacturing Ltd. | Air bridge process for forming air gaps |
| TWI227043B (en) * | 2000-09-01 | 2005-01-21 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device |
| US6380106B1 (en) * | 2000-11-27 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures |
| CN100372113C (en) * | 2002-11-15 | 2008-02-27 | 联华电子股份有限公司 | Integrated circuit structure with air gap and manufacturing method thereof |
| US6924222B2 (en) * | 2002-11-21 | 2005-08-02 | Intel Corporation | Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide |
| US6930034B2 (en) * | 2002-12-27 | 2005-08-16 | International Business Machines Corporation | Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence |
| US7361991B2 (en) * | 2003-09-19 | 2008-04-22 | International Business Machines Corporation | Closed air gap interconnect structure |
| US7629225B2 (en) * | 2005-06-13 | 2009-12-08 | Infineon Technologies Ag | Methods of manufacturing semiconductor devices and structures thereof |
| CN100539069C (en) * | 2007-05-23 | 2009-09-09 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation from manufacture method |
| KR100976792B1 (en) * | 2007-12-21 | 2010-08-19 | 주식회사 동부하이텍 | Method for manufacturing semiconductor device having porous low-k material |
| US8461015B2 (en) * | 2009-07-08 | 2013-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI structure and method of forming bottom void in same |
| CN101673703A (en) * | 2009-09-22 | 2010-03-17 | 上海宏力半导体制造有限公司 | Fabricating method of shallow trench isolation structure |
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