TWI232496B - Integrated circuits with air gaps and method of making same - Google Patents

Abstract

An integrated circuits with air gaps is disclosed. An underlayer is formed on a substrate. A first metal pattern is formed on the underlayer. A dielectric layer is deposited on the underlayer and the first metal pattern. A second metal pattern is formed on the dielectric layer. Utilizing the first metal pattern and the second metal pattern as masks, an isotropic etch process is performed on the dielectric layer and the underlayer. A plurality of holes is formed in the dielectric layer and the remaining dielectric layer serves as supports under the second metal pattern. A chemical vapor deposition process is performed to deposit a cap layer on the second metal pattern and to seal the holes.

Description

1232496 Case No. 92131566 Amended on May 5, V. Description of the Invention (1) [Technical Field] The present invention provides a high-performance integrated circuit (1C) structure, especially an air gap ) Integrated circuit structure and manufacturing method thereof. The invention is particularly applicable to the field of logic IC or integrated IC (such as system integrated chip (s y s t e in-ο η-c h i p, S 0 C)) which requires high operation performance and high accumulation degree. The method for forming an integrated circuit structure with an air gap provided by the present invention provides a complete solution for a semiconductor manufacturer to reach a mass production scale. [Prior art

With the advancement of semiconductor manufacturing technology, the design size of semiconductor elements fabricated on a semiconductor wafer has continued to shrink, and has evolved to the deep sub-micron generation. However, as a result of the increasing density of integrated circuits, the problem of the RC delay between the metal wires has a significant impact on the operating performance of integrated circuits, especially when the process line width (1 inewidth) drops to When the semiconductor process is below 0.1 micron, and even below 0.1 micron, the effect of time delay on the operation performance of the element is more obvious. OK} Time delay (C time delay capacity line is electrically connected to the time between the host and the gold wire in the connection between the on-chip crystal genus of the metal gold and the two directions and semi-advance R) less RC to 1 ( Minus 1 square resistance r

1232496 _Case No. 92131566a Amendment _ V. Description of the invention (2) OK. The first is to use a metal material with a lower resistance value as the metal wire, and the second is to reduce the parasitic capacitance between the metal wires. Increasing the transmission speed of metal interconnects while reducing power consumption. In the conventional practice, the method of reducing the parasitic capacitance between metal wires is mainly to use low dielectric constant (k < 3) materials such as FSG, HSQ, FLAREKi, or SiLKTM. The characteristics of these low dielectric constant materials basically need to include smart dielectric constant, low surface conductivity (rSiStlVity > 1015Ω), and low stress (compressive 埶 獐 —wowei) Slle > 3〇MPa ), Excellent mechanical strength and chemical fish

^; 7Κ α A ^ ^ ^, i (f A compatibUuy). However, many process reliability and speckle number materials have serious problems, which are caused by the new generation of low dielectric constant / material type. Before the advent of process technology to overcome the time delay, how to become a subject worthy of discussion and improvement and a decrease in operating efficiency was due to the ideal dielectric constant of air.

As an insulating material for metal wiring, j 'so use air (one of the solutions of air capacity. Although the bucket is to reduce the parasitics between metal wires' technology applied to integrated circuits ^ α Xi's low dielectric The electric constant j does not have the value of mass production. For example, $, published, but most of the 1 1 ^ 11 y.1 (. Y 66 is a method disclosed in Li ^ Patent No. 4 9 2 0 6 39 The method is to first use the integrated electric fresh layer of light 1 and ... with air separation, to complete the metal interconnect 1 = temporary between the metal interconnect: after the clothes are made, then use the solvent to remove ^

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_Case No. 92131566 V. Description of the invention (3), or even all photoresistors, and a large amount of air space is formed between the metal interconnects. This method will cause the metal interconnects to be almost completely suspended without sufficient support, which may easily cause the integrated circuit to be damaged by mechanical forces. In addition, U.S. Patent No. 6 1 3 0 1 51 discloses a method for forming a silicon oxide layer with air spaced between metal interconnects. The method is to first form a silicon oxide layer and a nitrogen oxide layer on the metal layer. Then, a plurality of openings are defined on the nitrogen stone layer through a lithography process, and then an etching process is performed to sequentially etch the silicon oxide layer and the nitrogen silicon layer or the silicon only along the foregoing openings. An oxygen layer to form air spaced inside the silicon-oxygen layer. -U.S. Patent No. 5 9 4 9 1 4 3 discloses a method for forming air space between metal interconnects. The method is to first form a double damascene metal connection in the dielectric layer and then deposit it for a while. The termination layer (etchst ο p 1 ayer) is on the metal connection and the dielectric layer, but the exposed part of the dielectric layer is finally etched to remove the dielectric layer that is not covered by the termination layer. To form an air gap between each of the metal lines and the etch stop layer. Others, such as U.S. Patent Nos. 5 324683, 6077767, 6083821, and 5 4 0 7 8 60, etc., also disclose various methods for forming an air gap between metal interconnects', which are not described here. However, in addition to the above-mentioned conventional technologies, which are too complex and difficult to integrate, they also face some problems with reliable friction, such as the metal interconnects cannot obtain sufficient support. The present invention can provide a complete solution

Page 8 1232496 _ Case No. 92131566_ • Year Month _i ± i-_ · V. Description of Invention (4) The case is to solve the bottleneck that the conventional technology cannot break through, and can reach a mass production specification and model. [Content] The main purpose of the present invention is to provide a high-efficiency integrated circuit structure and a manufacturing method thereof. Another object of the present invention is to provide an integrated circuit structure having an air gap and sufficient support, and a manufacturing method thereof, so as to make a large amount of air gaps between metal interconnects, thereby reducing the time delay of the metal interconnects. Late effect. Make the leader and the structure to be gold-separated, and the space between electricity and gas can be large enough to contain the structure when the structure is high, and the same branch can be charged with enough electricity. . The line of the line belongs to the starting line of the gold dew. The original line of the line was first formed in the form of the case [S11, the line structure is a branch of the gold branch 1 or 2; The gold is in layer one, the case is the figure in the line formation structure, the branch line is the gold in the guide, the layer is the second line in the line, and the guide is the gold line in the second line, the line is the guide # 金 支 层Let ’s use the first layer. The guide line of the floor plan of the room is covered by a guide and a layer of gold. • The second floor of the electricity should be between the engraved shapes. There are. Included in the form of a package. The method of the French method is highly productive. It is made on the Mitsui species 1 when it is exposed.

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1232496 _ Case No. 92131566 Amendment V. Description of the invention (5) In the preferred embodiment of the present invention, the method first forms a bottom layer on a substrate and forms a first layer of metal wire pattern on the bottom layer. . A dielectric layer is formed next to the first metal wire pattern and the bottom layer, and a second metal wire pattern is formed on the dielectric layer. Subsequently, the first layer of metal wire pattern and the second layer of metal wire pattern are used as an etch mask, and the dielectric layer and the bottom layer are anisotropically etched to form a plurality of grooves, and at the same time, the remaining dielectric The layers constitute a support structure for the second layer of metal wire patterns. Finally, a chemical vapor deposition (CVD) process is performed to deposit a capping layer on the surface of each groove and the second layer of metal wire pattern, and cover each groove to form a plurality of air spaces. Zhi · Jianjian Road can be layered when the electricity is drawn, the structure of the electric connection layer is connected to the layered layer of gold, which belongs to the layer of gold, which is in the sense of electricity. Shaofa supports the use of layers to cut the square branch or belong to ########################################################### Figure to wait for the use of the degree or not, non-profit lines are separated by a metal cover, and can be covered with gold and inside and outside with a moment of engraving this belongs to Lu Li # 余 空. Jin Dianming has a physical effect on the body and the number of layers has a higher level. The structure is higher than the resistance. The structure is delayed by light. [Implementation method] »Please refer to Figure 1 for the structure of the present invention. FIG. 1 is a schematic cross-sectional view of an integrated circuit structure having an air gap or an air gap in a comparative embodiment of the present invention. As shown in FIG. 1, the semiconductor wafer 10 includes a substrate

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1232496 ___ Case No. 92131566_Year Month Day Amendment __ V. Description of the invention (6) π ′ may be a single crystal silicon substrate or other semiconductor substrate. The surface of the substrate 411 may include a semiconductor device that has been fabricated, such as a memory unit (m e m 0 r y c e 1 1), an M 0S transistor, a resistor, or a capacitor. Since these elements are not the focus of the invention, they are not shown in the illustration. The bottom layer 12 is formed on the substrate 11, wherein the bottom layer 12 may be composed of a single dielectric layer or a plurality of dielectric layers. Three metal pattern layers (MI, M2, and M3), metal plugs 24a and 26a, and dielectric layers 24, 26, and 28 are formed on the bottom layer 12 to form a stacked metal interconnect structure. Here, the metal pattern layers (M1, M2, and M3) are metal wire patterns defined in the same layer. Define metal wire patterns (Ml, M2, and M3) and metal plugs 24a and 26a can use traditional gold lip sputtering and etching techniques. Dielectric layers 2 4, 2 6 and 28 can use general chemical vapor phase Formed by deposition or spin coating. 'In FIG. 1, the air gaps 22 a and 22 b are formed between the metal pattern layer M2 ′ and extend downward to the dielectric layer 24 and even further downward into the bottom layer 12. The air gaps 2 3a and 2 3b are formed between the metal pattern layers M3 and extend downward to the dielectric layer 26. The air gaps 2 2 a and 2 2 b are covered by a dielectric layer 26 and have an overhang closed structure on top of the air gaps 2 2 b. The air gaps 23a and 23b are formed by being covered with a dielectric layer 28. The air gap 2 2a is in a connected state with the air gap 2 3a. This is because during the formation of the air gap 2 3 a, the anisotropy cuts through the air gap 2 2 a originally covered by the dielectric layer 2 6. . In other embodiments of the present invention, the excavated air gap 2 2a can be closed again by the dielectric layer 28 to form two independent air gaps 2 2 a and

Page 11 1232496 Case No. 92131566_ Year Month Revision "V. Description of the invention (7) 2 3 a. This can be achieved by adjusting the degree of step coverage when the dielectric layer 28 is deposited. For example, please refer to the spaced semiconductor. The photoresist layer is formed on the top of the mechanical plug 13a in the first order. Figs. 2 to 6 and Figs. 2 to 6 are schematic diagrams of a method for manufacturing an air circuit structure according to the present invention. As shown in FIG. 2, the wafer 10 includes a substrate 11 and a bottom layer 12. A metal pattern 13 located on the substrate 11 can be formed on the bottom layer 12 by sputtering, lithography, and etching. A dielectric layer 14 is then deposited on the first layer of metal pattern 13 and the bottom layer, and then through the processes of lithography, etching, deposition, and chemical polishing (CMP), metal inserts are formed in the dielectric layer 14. Subsequently, a metal layer 15 is formed on the dielectric layer 14 and the metal plug 1 3 a, and a defined photoresist layer ΐβ is formed on the surface of the metal layer 15. -16 defines a second metal pattern on the metal layer 15. Next, as shown in FIG. 3, the photoresist layer 16 is used as an etching mask to etch the metal layer 15 to form a second metal pattern 17 over the dielectric layer 14 and the metal plug i3a. The metal plug 1 3 a is electrically connected to the first layer metal pattern 13 as a via plug. The photoresist layer 16 is subsequently removed. The first metal layer pattern 13 and the second metal pattern 17 may be made of aluminum metal, copper alloy or copper metal. The metal plug 1 3 a may be composed of W (W) and titanium / titanium nitride (Ti / TiN). The composition of the dielectric layer 14 may be SiO 2, fluorinated silicate glass (FSG), or other enhancement using electropolymerization. Plasma-enhanced chemical vapor deposition (PECVD) or high Density plasma chemistry

Page 12 1232496 Case No. 92131566 Date of Amendment V. Description of the Invention (8) A dielectric layer formed by high-density plasma chemical vapor deposition (HDPCVD). The structure of Yijin's structure has been built up in time, and it ’s time. There is a structured line in the sky. ‘Ming Lian Fa ’s internal genus, gold is copper. It ’s called on demand. Case d.

丄 * 丄 frt 捅 金 > 3 1A cap and

a W Arts and technology items The knowledge of drinking, ML introduces the technique of gold in technology-Zhizhi Chengshu Institute e) The dual-use Ricoh 7 11 plan is embedded. Mosaic double redundant. This layer is not easy to use because it is easy to lightly publish the text, and to publish the text for the applicants. In the technical process, the system knows the copper habit. The pre-groove line is recessed and removed, and the rest is used as the cover. The system 2 is now hidden to 14 controls. In the process of eroding electricity to electricity, i-piece 7 covers the whole case and engraved it. Reverberation etch + :: Mainland film belongs to the case of gold 1C Figure 14 is suitable for the layer OP layer X degree two tr gold electricity can be deep so layer interlayer P groove with ni two to de concave, (B section 18S A display is # le * -this direction is not concave im but four equal degrees (t, the figure is not deep. If it is a certain time depth, then as shown in Figure 5, the media in the groove 18 The electrical layer 14 is subjected to an isotropic dry or wet etch process to further expand the area of the groove 18 to form an undercut profile on the second layer of metal. Under the pattern 17. It should be noted that the aforementioned isotropic etching process is an optional step, that is, the isotropic etching process may be omitted and not performed, and on the other hand, the isotropic process is performed. The main process of etching

Page 13 1232496 Case No. 92131566 Amendment Date V. Invention Description (9) The purpose is to selectively expand the area of the groove 18, so that only the dielectric layer under the second metal pattern 17 is partially removed. 14. The supporting structure for supporting the second metal pattern 17 includes a dielectric layer 14 and a metal plug 13a.

And) 1 8 Γ 1 e Caoya Concave 1 #a, C XC The first layer 9 seals, and is a system of sound &sound; VD is empty The line guide groove is recessed and covered with gold. The same amount of power is required. V Day 9 11 layer cover is deposited in the metal layer. The second layer is on the 9 11 layer cover. Get the value of "Teaching Qi" 8 daggers will quickly reduce the speed of the ground to 8 11, groove g) recessed into the rh product eVV 0 9 κίν 1 Suspension projection into a small shape reduction. Into and out of the corner, cover the cover with 7 seals, 11 cases, 18 1111 slots. Concave line Embodiment 2 Please refer to FIG. 7 and FIG. 8. FIG. 7 and FIG. 8 are schematic diagrams of a manufacturing method according to another embodiment of the present invention. Among them, FIG. 7 continues the process steps of FIG. 2. After exposure, development, and etching processes, a second layer of metal pattern 17 is formed on the dielectric layer 14 and the metal plug 13 a. Photoresist layer 16 of two-layer metal pattern 17. As shown in FIG. 8, the method of the present invention can use the photoresist layer 16 as an etching mask, and sequentially perform the anisotropic money engraving and isotropic #etching process shown in FIG. 4 and FIG. Subsequent to 15, a plurality of grooves 18 are formed in the dielectric layer 14 by etching, and the groove 18 forms an undercut profile under the second layer metal pattern 17. That is, after the second layer of metal pattern 17 is completed, the composition of the etching gas is adjusted at the same time to simultaneously (i η-s i t u)

Page 14 1232496 Case No. 92131566 _η Revision V. Description of the invention (10) Electrical layer 14. Finally, the photoresist layer 16 is removed, and a chemical vapor deposition (CVD) process shown in FIG. 6 is performed, and a cap layer 19 is deposited on the surface of the groove 18 and the second metal wire pattern 17. The grooves 18 are covered to form a plurality of air intervals 1 8 a. Embodiment 3 According to the present invention, the manufacturing method for manufacturing the air interval 18 a shown in FIG. 4, FIG. 5, and FIG. 8 can also be implemented in any metal pattern layer or each metal layer in the multi-metal interconnection process. Pattern layer. Referring to FIG. 9, after three consecutive metal pattern layers (M1, M2, and M3) and each metal plug 1 3 a are made, the uppermost metal pattern layer M 3 is used as an etching mask, and the metal pattern layer is used. M2, the metal pattern layer M1 is used as an etch stop layer to perform anisotropic etching, and a large number of air grooves 18 are made between the multiple metal interconnects. In addition, as shown in FIG. 10, in the present invention, a barrier layer (s t ο ρ 1 a y e r) 1 2 a can be added to the bottom layer 12, so that over-etching can be avoided and the components under the bottom layer 12 can be destroyed. Embodiment 4 In order to prevent the gap between the wires in the second layer metal pattern 17 shown in FIG. 10 from being too large, so that no matter how to adjust the process parameters of the chemical vapor deposition process, the cover layer 19 will be deposited into the groove 18 In this case, the volume of the air gap is reduced by 18 a, and a du mmy pattern can be formed on a region with a large gap between the metal wires. Please refer to Fig. 11 to Fig. 14. Fig. 11 to Fig. 14 are schematic diagrams for making air gaps on metal inner wires with excessively large gaps between the wires. First, as shown in Figure 11, when the first

_111 1 II III 111 1 11 III Draw 1_1_ 1 ill ill II ill ill Page 15 1232496 _ Case No. 92131566 Fifth, the description of the invention (11) Means to modify the two-layer metal pattern 17 The wires and interspaces are too large, the present invention A dummy pattern (dummy. Pa 11 er η) 1 7 a may be appropriately added on the dielectric layer 14 in the gap between the excessively large wires. Wherein, the method for forming the dummy pattern 17 a may include a plurality of dummy patterns in the layout of the mask of the second metal pattern 17, so that the second metal pattern 17 and the dummy pattern i7 a are simultaneously formed on the dielectric layer 14. As a result, the space between the wires of the second-layer metal / metal pattern 17 is reduced. Then, sequentially perform the anisotropic relief, the specific money engraving, and the chemical vapor deposition process shown in FIGS. 4 to 6 in order to form a plurality of air spaces 1 8 a in the dielectric layer, as shown in FIG. 12 As shown. As shown in FIG. 13, when the space between the wires of the second metal pattern 17 is large. The method of the present invention can also deposit a thin film layer after the second metal pattern 1 is formed (not shown) ) On the second layer of metal pattern 1, an etching process is used to form a side wall 17b on the side of the second layer of metal pattern 7. Among them, the method of forming the side wall 17b is well known to those skilled in the art ', and therefore will not be described again. Due to the formation of the side wall member 17b, the space between the wires is narrowed. Then, the anisotropic etching, isotropic engraving, and chemical vapor deposition processes shown in FIGS. 3 to 5 are sequentially performed to form a plurality of air spaces in the dielectric layer 14. As shown in FIG. 14 'When the gap between the wires of the first metal pattern 17 is too large, the method of the present invention can also cover the wires with a photoresist layer 20 after forming the second metal pattern 17 The second layer metal pattern 17 with a large gap is only exposed, and only the second layer metal pattern 17 'with a small gap between the wires is exposed or the photoresist layer 20 uses the second layer with a large gap between the wires.

Page 16 1232496 Case No. 92131566 __Year Month Amendment _ V. Description of the invention (12) At least one dummy pattern is formed between 17 two-layer metal patterns. Then, the anisotropic money arrival and the isotropic surname shown in FIG. 4 and FIG. 5 are sequentially performed, so that a plurality of grooves 18 are formed in the dielectric layer 14 not covered by the photoresist layer 20. Then, the photoresist layer 20 is removed, and a chemical vapor deposition process shown in FIG. 6 is performed to form a plurality of air spaces 18 a in the dielectric layer 14. -The method guides the obscuration gas in the Γ Fang Yijin route, which belongs to the etching space. The well-defined conductivity of the layer of the metal erosive effect la is used to calculate the power of each case, and the nt is the same. The diagram is made after the layers are connected one by one (i # line is supported by various straight resistance line extension layers to guide it, so that the belonging case of light into the electricity is enough. When the layer is lined, the gold pattern is enough to etch energy. The time line of the mesopod line of the electric company was recorded. The inner line layer got a lead of the same line. The line of the line was obtained. Each line was clear enough. There is a gold line and a foot line. The subordinates follow each layer continuously. The layered capital case is separated by gold and Θ with several masks. The meaning map, less subordinates can be used to cover the legal line and reduce the positive gold. In the eclipse, the space obtained by using the attribute reaching the line h or the known or golden direction leads to 1C space. The case size is familiar, and the equivalent mapping of tr belongs to the case. The gold ec becomes the line. The bottom is compared with the figure, and the elliptical shape of the guide wire cover and each dl are the same middle diagram.

Dedicated to 1232496 Case No. 92131566 Month and Day Amendment Simple illustration of the drawing Simple illustration of the drawing Large gaps in the production system. . The air gap in Tutu is empty. The air-to-air, air-to-air, or air-to-air display of the display body interval means the method of showing the square of the air-conducting surface between the product lines. The result is good in the air department. For example, there are two examples: the road is compared with the plan, the intention is to implement electricity, the entity is expressly stated that the air quality accumulation method is issued for this purpose. Six-to-eight diagrams The diagrams of the ri diagrams are perfect. It is a map of b to lu and yi yi yi two electric seventy or ninety domains (a picture of the body of the diagram, the diagram of the square area of the symbol description 10 semiconductor wafer 11 substrate 12 bottom layer 13 first layer metal pattern 13a metal plug 14 Dielectric layer 15 Second metal 16 Photoresist layer 17 Second metal pattern 17a Dummy pattern 17b Side wall 18 Pore 18a Air gap, 19 Cover layer 20 Photoresist layer 22a Air gap 22b Air gap 23a Air gap 23b Air gap 24 Dielectric layer

Page 18 1232496 Case No. 92131566 Modification of the drawing Brief description of 24a plug 26 dielectric layer 26a plug 28 dielectric layer Ml metal pattern layer M2 metal pattern layer M3 metal pattern layer m · page 19

Claims (1)

1232496 _ Case No. 92131566_ Modification of Year of the Month _ 6. Scope of Patent Application 1. An integrated circuit structure with an air gap, comprising: a substrate having a bottom layer thereon; a first layer of metal wire pattern formed on On the bottom layer; a second layer of metal wire pattern formed above the first layer of metal wire pattern; a support structure formed between the first layer of metal wire pattern and the second layer of metal wire pattern 'for supporting The second layer of metal wire patterns, wherein the support structure includes a dielectric layer subjected to isotropic etching; and a plurality of air gaps formed by a capping layer are formed between the second layer of metal wire patterns. · 2. For the integrated circuit structure of item 1 of the patent application scope, in which the substrate is a Shixi substrate. Page 20 1232496 _ Case No. 92131566 _ Month and Day __ VI. The scope of the patent application also includes at least one via plug that electrically connects the first layer of metal wire pattern and the second layer of metal wire pattern. . 6. The integrated circuit structure according to item 1 of the patent application scope, wherein the capping layer uses a plasma enhanced chemical vapor deposition method (pi asma-enhanced CVD, PECVD) or a high-density plasma chemical vapor deposition method (high density plasma CVD (HDPCVD). Structured •: Cases of the support of Fan Zhifan's special case, please apply for the line, such as the outline of the structure of the road structure in L Jindi. The second line of the second layer of the gold map is the second line: the guide and the first line belong to the content; the gold file is formed on the upper layer of the package, and the first line and the second shape of the bottom are the first and second lines. The gold braces are electrically formed into layered branches and the gas shape comes. The empty product, the first case should be counted as follows: • The interval picture is formed by the line between the multiple lines. The air-conducting guide forms a space-generating genus, and the figure has a gold-gold structure line with a layered structure and a layer map type 12; the supporting genus is covered with a line of the first party branch; a guide 8.11 Upper level case Page 21 1232496 _Case No. 92131566 __ Sixth, the scope of the patent application is 10. For example, the integrated circuit structure of the eighth patent application scope, wherein the support structure includes a dielectric and dielectric layer after isotropic etching. . 1 1. The integrated circuit structure according to item 8 of the scope of patent application, wherein the second layer of metal wire patterns includes a dummy pattern to reduce the gap between the metal wires of the second layer of metal wire patterns. 1 2. The integrated circuit structure according to item 8 of the scope of patent application, wherein the second-layer metal wire pattern includes a sidewall formed on each side wall of the second-layer metal wire pattern. · 1 3. The integrated circuit structure according to item 8 of the patent application scope, wherein the cap layer * is formed by plasma enhanced chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition (HDPCVD). 1 4. A manufacturing method of an integrated circuit with an air gap, the manufacturing method includes: providing a substrate having a bottom layer thereon; forming a first layer of metal wire pattern on the bottom layer; and forming the first layer of metal A wire pattern and a dielectric layer are formed on the bottom layer; a second metal wire pattern is formed on the dielectric layer; the first metal wire pattern and the second metal wire pattern are used as an etching mask; Isotropically etch the dielectric layer to form a plurality Page 22 1232496 _Case No. 92131566 Rev. _ 6. Apply for patents with grooves and make the remaining dielectric layer constitute the supporting structure of the second metal wire pattern; and perform a chemical vapor deposition ( CVD) process, a capping layer is deposited on the groove surface and the second metal wire pattern to cover the groove to form a plurality of air gaps. 15. The manufacturing method according to item 14 of the scope of patent application, wherein the substrate is a silicon substrate. 16. The manufacturing method according to item 14 of the scope of patent application, wherein the first layer of metal wire pattern is inlaid on the bottom layer. · 1 7. The manufacturing method according to item 14 of the scope of patent application, wherein the second layer of metal wire pattern is inlaid on the dielectric layer. 18. The manufacturing method according to item 14 of the scope of patent application, wherein the first layer of metal wire pattern and the second layer of metal wire pattern are made of copper. 19. The manufacturing method according to item 14 of the scope of patent application, wherein the first layer of metal wire pattern and the second layer of metal wire pattern both include aluminum metal. 2 0. The manufacturing method according to item 14 of the scope of patent application, wherein the manufacturing method Page 23 1232496 _Case No. 92131566_ Amendment Month_ Sixth, the scope of the patent application is after the dielectric layer and the bottom layer are anisotropically etched, and the support for isotropically etching the second metal wire pattern is also included. Structure to form an undercut profile and expand the area of the groove. 2 1. A method for manufacturing an integrated circuit with an air gap, comprising: providing a substrate having a bottom layer thereon; forming a dielectric layer on the bottom layer; forming a metal wire pattern on the dielectric layer And using the metal wire pattern as an etching mask to etch the dielectric layer to a predetermined depth to form a plurality of grooves in the dielectric layer, and at the same time, the remaining dielectric layer to form the metal wire pattern Its support structure. · 2 2. The manufacturing method according to item 21 of the scope of patent application, wherein the metal wire pattern forms 'inter 1 ine spacings' on the dielectric layer, and the plurality of grooves are formed in In the dielectric layer in the spaces between the plurality of wires. 2 3. The manufacturing method according to item 21 of the patent application scope, wherein the method of etching the dielectric layer uses an anisotropic etching technique. 2 4. The manufacturing method according to item 21 of the scope of patent application, wherein the metal wire pattern is embedded in the dielectric layer. 2 5. The manufacturing method according to item 21 of the patent application scope, wherein the manufacturing method Page 24 1232496 _Case No. 92131566_ Year Month ___ Sixth, the scope of applying for a patent after etching the dielectric layer, and also includes the following steps: Isotropic (is 〇tr 〇pic) engraving the metal wire pattern Supporting structure to form an undercut profile to expand the area of the groove; and performing a chemical vapor deposition (CVD) process on the surface of the groove and the metal wire A cap layer (cap 1 ayer) is deposited on the pattern, and the groove is covered at the same time to form a plurality of air gaps. Page 25