TW490801B - Method for forming isolation gap between bit line and capacitor - Google Patents

Abstract

The present invention discloses a manufacturing method for forming isolation gap between the bit line plug and the capacitor of dynamic random access memory (DRAM). At first, capacitor is defined on the semiconductor substrate, in which the capacitor is on the first dielectric layer and is connected with the source/drain of the lower transistor through the first conducting plug inlaid in the first dielectric layer. The second dielectric layer is formed on the periphery of the capacitor so as to cover the first dielectric layer and the second conducting plug in the lower part, and, in addition, part of the sidewall outer edge of the capacitor is exposed. Then, the third dielectric layer can be formed along the capacitor surface. The fourth dielectric layer is deposited flatly on the third dielectric layer. After that, opening hole of the bit line is defined in between the films to expose part of the upper surface of the second conducting plug. A selectively etching process is then conducted onto the third dielectric layer to make the third dielectric layer shrink along sidewall of opening hole in the bit line such that the isolation gap is formed at the sidewall edge of the capacitor. After that, the spacer can be formed on the sidewall of opening hole in the bit line and bit line plug can be manufactured inside the bit line opening hole.

Description

490801

V. Description of the invention (1) Field of the invention: The present invention relates to a dynamic random access with bit line power off bit "ne;CUB); = 1: un; er especially-a kind between the bit line and the capacitor Process of line parasitic capacitance #〉 Go. Table work gap ^ to reduce the position of the background of the invention: With the (ULSI) trend, it keeps on building up so that its memory is reduced by the size of the digital line and the word, so the question of access to memory is The reduction in the size of various components in the development and design of the semiconductor industry has also led to problems that have not been encountered, and when the common mobile cells (ce 1 1) in the circuit, the capacitors and transistors are stored in the capacitor speech line array. The problem in access memory reduced to sub-micron and its memory carrier (DRAM) is in addition to the progress of how to increase the capacitor storage capacity in the element size. Below submicron. And because of the semiconductor manufacturing process, the complexity of the system is often increasing. For example, in terms of state random access memory (DRAM), in a process that includes transistors and capacitors, the source / drain makes electrical contact. Digital data for bit capacitors. Therefore, when the device is underneath, the size of the capacitor in the DRAM is also reduced and the energy is relatively reduced. Therefore, for a dynamic random memory cell, in addition to its capacity to keep shrinking in size and increasing its accumulation, it is also necessary to consider each

Page 4 5. Description of the invention (2), the parasitic capacitance generated between electrical components to increase the reliability of the capacitor and the accuracy of signal transmission. Please refer to the bit line below. First, lines) uses 14. Then, on the region 14, a second polycrystalline particle volume is oxidized and the bottom surface of the phenocrystalline grain is defined. The first figure is that the capacitor can be deposited on the gate of the semiconducting material, and the layer 20 is lithographed at the bottom of the electrode. The polysilicon plug 18 and the first port pattern on the electrode 22 are shown in the process formation diagram. This figure shows the DRAM memory cell according to the transmission. A structure 12 is made on a typical substrate 10, and a polycrystalline stone located in the first oxide layer 16 of the gate defines a contact hole in the gate, and then opens a pattern table to control the manufacturing process, and the manufacturing steps of the manufacturing process The following is the word line (the source / drain region structure 12 between the word and the source / drain between them. Then by packing 18. Then, the upper surface of the sinkable oxide layer 16 can be deposited with a hemispherical surface. Storage capacity In the process of making a retrospective engraving procedure, the capacitor dielectric layer 24 is in the crown opening of the capacitor dielectric layer 24. The crystalline silicon plug 18 connected to the second oxide layer 2 2 sense line plug is generally shown in the above table. In order to further enhance the storage capacity of the bottom electrode 22, the second oxide layer 20 will be exposed to expose the surface of the bottom electrode 22. Then, sink on the outer surface of the bottom electrode 22 and define the surface of the top electrode 26. And filled with the bottom electrode 22 can be deposited with a third oxide layer 28 can be deposited on the top electrode 26 and on top, and then through the rhyme process, the opening pattern 30 is formed to expose the central portion. Multi-faceted servings. 490801 V. Explanation (3) The surface of the noteworthy capacitor is short. In order to have the pole 22, it is often difficult to describe the opening pattern 30. Of course, the second oxide is exposed to the bottom electrode 2 except for etching back. The pattern on the two sides is 30, and it is easy to determine, increasing the aspect ratio of the product, increasing its aspect ratio, increasing the layer 20, increasing the outer edge of the wall and the bits in the element dimension, and the capacitance storage capacity of each other is south. However The outer step of the height of the rear capacitor has been increased, so that the effect of the bottom area has been reduced. The top electrode 2 6 wire plugs continue to shrink between the plugs, so that the distance between each of them becomes more 'in making the above bottom electricity The bit line plugs that will continue to be manufactured can also be exposed by exposing the outer side walls of the electrodes 22 above. However, in this way, the coverage will be closer to the opening parasitic capacitance. In fact, as component accumulation As the distance between the bit line plug and the bottom electrode 22 or the top electrode 26 is getting closer, the capacitance of the bit 7L line has increased significantly. In addition, in order to improve the cell Capacitor (ceU capacitor) storage capacity, and making the bottom electrode with a larger height, or making the top electrode 26 cover the outer edge sidewall of the bottom electrode 22, will cause the bit line capacitance value to increase more significantly. Extra == In addition to reducing the speed of unit cell signal transmission, 'will also make the signal weaker U and reduce the accuracy of the interpretation. It is a problem with the capacitance of the bit line capacitors, which is not possible in the current semiconductor manufacturing process. : Ϊ Use low dielectric constant material to fill capacitors and bit line plugs to reduce parasitic capacitance. However, when manufacturing line plugs, high-temperature RTp processes are often performed first to form materials such as silicon.

Page 6 490801 Description of the invention (4) The barrier layer made of titanium material is in the bit line opening pattern, which will reduce the low dielectricity, the characteristics of several materials, or even generate bit line plugs such as ⑽gas丨 ng good response. Therefore, for the current semiconductor industry, there is an urgent need for a six-method in order to effectively solve the problem of bit line capacitance while reducing the component size. Purpose and summary of the invention: The purpose of Shi Ming is to provide a process for manufacturing a DRAM memory element that isolates a gap between a bit line plug and a valley device. The present invention provides a method for manufacturing a dynamic random access memory with a bit-line capacitor. First, a plurality of inter-electrode structures are formed on a semiconductor substrate to be used as daughter wires. Next, a source / drain region is defined in the semiconductor substrate between the gate structures, and a first dielectric layer is deposited on the semiconductor material to cover the gate structure and the source / > and electrode regions. After the iron, the first dielectric layer is lined up until it reaches the surface of the semiconductor substrate f to form a first opening between adjacent gate structures, and a portion of the upper surface of the source / drain region is exposed. Subsequently, a self-aligned conductive plug may be formed in the first opening to connect the source / drain region. Among them, the self-aligned conductive plug can be divided into a first, the first conductive plug is used to connect to the bottom electrode of the capacitor, and the second conductive plug is used to connect to the bit line. The second dielectric layer is deposited by iron on the first dielectric layer and the self-aligned conductive plug. ",, V. Description of the invention (5) The electrode openings are drawn with the flute-Figure 荦 € ϋ m"丨 in the electrical layer. Among them, the bottom electrode is opened to expose the upper surface of a conductive plug. Next, a bottom is deposited to define a part of the bottom electrode surface, and is deposited on the bottom electrode opening electrode surface to form a film layer above the second electrical layer, wherein the film and the capacitor and the dielectric film layer also have a layer, A third dielectric film layer on the second conductive plug has a third dielectric film layer side wall opening side wall and an outer edge. Then along the opening of the potential gap, the sidewalls and electrical layers of the element line plugs and capacitor capacitors are exposed on the bottom electrode, and filled, along the top layer and the second dielectric between the third dielectric and the third dielectric. The electrical layer and the fourth dielectric at the third moment until it arrives. Next, the electrical film layer is sealed in the isolation space by the side wall of the bit electrode, in which the bit line parasitic electricity the first conductive layer defines the bottom electrode in the bottom electrode opening, and the second dielectric side wall is engraved with the rice. Subsequently, a second dielectric layer is formed in the surface pattern of the capacitor dielectric layer to define a top electrode. Then there are two dielectric film layers, of which the third dielectric film is selected differently. Re-deposit the fourth dielectric layer. The fourth dielectric layer can completely cover the lower surface and has a flat upper surface. Then, the selective etching process is performed on the surface of the etchable layer, the second conductive layer, and the second dielectric layer to form bit line openings, so that the third interspace is retracted, and an isolation gap is formed on the side wall of the top element line opening. Form the gap wall and densely make the bit line plug between the bit line openings with an isolation gap to reduce the bit. Detailed description of the invention. Page 8 490801 V. Description of the invention (6) Please refer to the second figure, first provide a The semiconductor substrate 100 is used to deposit a desired film layer. Among these, the semiconductor substrate 100 can be composed of single crystal silicon having a crystal orientation of < 100 >. In general, other types of semiconductor materials, such as gallium arsenide, germanium, or siHc〇n 〇ri insulator (SOI) on the insulation layer can also be used here The semiconductor substrate 100 is used. In addition, since the characteristics of the surface of the semiconductor substrate 100 do not cause any special influence to the present invention, < 11〇 > or < m > can be selected depending on its crystal orientation. In addition, through a well-known shallow trench isolation process, a shallow trench isolation structure (STI) can be fabricated on this semiconductor substrate, in order to define the active area used to make the device. On the material 100, a plurality of gate structures 102 used as word lines 2 U'ilnes) and source / drain regions 104 in the semiconductor substrate 100 on both sides of the gate electrode are fabricated. Next, a dielectric layer 106 is formed on the semiconductor substrate 100 to cover the lower / source regions below. ! Up to half of the body substrate 100, to expose some 02 rooms. ^ n ^ And the meaning of a plurality of contact holes in the adjacent gate structure oxide embodiment, here the first-dielectric layer can be used. Among them, conductive plugs 108 and 110 may be formed on the first dielectric layer 106 to deposit a conductive layer on the first dielectric 106 first, and filled with 490801. V. Description of the invention (7) in the above contact hole and reused The chemical mechanical polishing (CMp) procedure removes a part of the conductive layer on the upper surface of the first dielectric layer 106, and forms self-aligned conductive plugs 108 and 11〇 (self_aHgned, contact, SAC). Among them, the conductive plugs 10 on both sides are mainly used to connect with the bottom electrode of the capacitor. As for the conductive plug 110 located in the central part, it is used to connect with the bit line to be produced later. In a preferred embodiment, the conductive layer herein may be formed using a polycrystalline silicon material, and the conductive plug defined herein is a polycrystalline silicon plug. A second dielectric layer 112 is then deposited on the top surfaces of the conductive plugs 108 and 110 and the first dielectric layer 106. Generally speaking, the second dielectric layer 112 can be made of undoped silicide glass (USG). Then, by performing an anisotropic etching process, the opening pattern of the bottom electrode can be defined in the two dielectric layers 112. Then, a polycrystalline silicon film layer 116 can be deposited along the surface of the opening pattern 4. That is, a polycrystalline silicon film layer is deposited on the surfaces of the conductive plug 108, the first dielectric layer 106, and the second dielectric layer 112. The soil then 'can form a silicon seed (nuclei) on the surface of the polycrystalline stone film layer 6' and perform a thermal tempering process under a high vacuum environment to form a hemi-Spherical Grain ; HSG) Coarse key table for 118

Surface to increase the surface area of the bottom electrode of the capacitor. In this way, a bottom electrode 12 consisting of a crown-type polycrystalline silicon film layer U6 and a hemispherical spherulite surface 118 can be defined on the semiconductor substrate 100. M Page 10 490801

Next, please refer to the third dielectric layer 112 of FIG. 1 to reduce the surface height of about 3,000 to 8000 /. Outer edge of the side wall. Then, along the second dielectric layer; two valleys: the surface of the bottom electrode 120, a capacitor dielectric layer 122 is formed. In a preferred embodiment, the capacitor dielectric layer 22 can be a composite thin film of 0 / N, 0 / to 0, or a high-dielectric thin film such as Ta205, BST, and p4. It is on the surface of the capacitor dielectric layer 122, and is filled with two; in order to define the use of the capacitor top electrode (toppUte). Generally, a doped polycrystalline silicon material can be selected to form the conductive layer 124 with a thickness of about 500 to 1000 angstroms. A third dielectric layer 1 2 6 may then be deposited along the surface of the conductive layer 1 2 4. It is worth noting that the material of the third dielectric layer 丨 2 6 here needs to be selected from the material having a large etching selection difference from the second dielectric layer 112. For example, when the second dielectric layer 112 is made of undoped silicon glass (USG), the third dielectric layer 126 may be formed using borosilicate glass (BPSG) or silicon nitride material. Thus, by virtue of the difference in the characteristics of the two materials, a difference in etching selection between the second dielectric layer 112 and the third dielectric layer 126 greater than 50: 1 can be provided. In a preferred embodiment, atmospheric pressure chemical vapor deposition (ApCVD) or plasma enhanced chemical vapor deposition (PECVD) can be used at a temperature of about 30 to 600 ° C and a pressure of about 1 to 10 Torr Borophosphosilicate glass with a thickness of about 300 to 1000 angstroms is formed in the environment of the ear. As for the reaction gas used, you can choose

SiH4, PH3, B2H6, TEOS, 03, TEB (Tri-Ethyl-Borate), TMP0 (Tri-Methyl-Phosphate), and so on. Or you can use low voltage

2. Description of the invention (9) Processes such as dry vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECvd) are used to deposit silicon nitride to obtain the required film layer. The temperature at which nitrogen fossils are formed is about 40 0-80 0 ° C.

Subsequently, a fourth dielectric layer 128 may be deposited on the surface of the third dielectric layer 126 and fill the gaps between the conductive layers 1 2 4. In other words, the lower third dielectric layer 126 and the conductive layer 124 can be covered by the thicker fourth dielectric layer 128. Generally, after the deposition of the fourth dielectric layer Kg, two lines of chemical mechanical polishing can be performed to make it have a flatter surface. In a preferred yoke example, this fourth dielectric layer 丨 2 8 can be made of a material that is in phase with the second dielectric layer 丨 丨 2 to provide a larger etch between it and the third dielectric layer 丨 2 6 Select j 异. For example, it can be formed by a general process of manufacturing an interlayer dielectric layer (ILD), such as a density deposition process (HDP), or by introducing 03 and ^ reactive gas 1 to form an undoped silica glass (USG). Required fourth dielectric layer

Eight next ', as shown in the fourth figure, a photoresist material layer 13 can be coated on the second island, 1 28, and by performing the relevant lithographic exposure, development, and clearing: the 70 position The opening pattern is in the photoresist layer 130. Subsequently, the photoresist layer 13 〇 is used as an etching mask to etch the second dielectric layer 126 of the fourth dielectric layer below: the I dielectric layer 124 and the second dielectric layer 112. / Come to reach the conductive plug 110 to define the subsequent use = 1 :: read the bit line opening pattern 132 of the plug. Generally speaking, during the engraving process, the electrical conductivity above each bottom electrode 120 is separated by

Page 12 490801 Fifth, the invention description (124) layer 124 can simultaneously define the top electrode 134 of the capacitor. After the photoresist layer 130 is removed, as shown in the fifth figure, a selective selective etching process may be performed on the third ^ 26, so that the electrical lines are opened by the bit lines, and a portion of the third dielectric is removed to both sides. The electrical layer 126 forms an isolation gap J (air gaPM36 between the fourth dielectric layer 128 and the top electrode 134.) In terms of the third dielectric layer 126 made of BPSG material and the second dielectric layer When U2 and the fourth dielectric layer 128 are made of a USG material, the third dielectric layer 126 can be etched using HF vapor. In this way, a # tick selection ratio of up to 1_: 1 will be able to Without harming the side wall of the bit line mouth 132, the third dielectric layer 126 exposed to the etchant is retracted, causing the above-mentioned isolation gap 136. As for the material of the dielectric layer 126, When composed of nitrogen cutting, the thermal process can be used to perform the etching process, and the surface of the second dielectric layer 1 26 can be retracted at an etching selection ratio exceeding 50: 1. In the embodiment, the space of the isolation gap 136 is increased, and the stability of the overall structural support of the capacitor is taken into consideration, so that the surface of the second dielectric layer 126 can be restored. The position to the bottom electrode 丨 2 is shown in the fifth figure. The above should be specially private. In order to more effectively prevent the top electrode 丨 3 4 from short-circuiting with the bit line plugs to be produced, you can also choose one. Etch procedure 'in order to open along the bit line! 32 sidewalls, remove part of the top electrode 134 to make it puU back, and increase the space to isolate the gap 136. Among them, by wet etching Method or dry etching such as ion plasma

: Sequence: ^: Top electrode 1 34 made of crystalline silicon material is etched = Λ When the entire isolation gap is made, the top electrode 112 which is part of the electrode iu and a which is adjacent to the second dielectric layer 112 is removed. The upper part 3P only removes the top electrode 134 of the horizontal portion of the bit line opening 132 distributed on the upper surface of the second dielectric drawer. In this way, it is possible to avoid shifting the two: member electrodes 134 'and reduce the storage capacity of the overall capacitor. When the capacitor is located at 199 丄, the electrode 134 is exposed, and the 8-3 adjacent to the field is exposed. However, in this process of etching the polycrystalline silicon material, the layer 122 can be used as an etch stop layer "topper", so that the bottom electrode 120 located in the inner layer will not be eroded. Refer to the sixth figure, and then a sidewall can be formed. The partition wall 138 is on the wall of the bit green opening to seal the opening of the above-mentioned isolation gap 136 to prevent soil, and a short circuit is generated between the bit line and the top electrode 34 which are continuously manufactured. Low pressure chemical vapor deposition (LPCVD) can be performed first. # Use TEQS material to deposit thick layer along the surface of semiconductor substrate ⑽: about 丄 00 to 500 Å. The deposited oxide film layer is also filled with the isolation gap on the sidewall of the bit line opening 1 3 2 and filled with the opening 3, and 9 to the desired sealing effect. Then, by performing an etching process, The electrical plug 110 and a portion of the oxide film layer on the upper surface of the fourth dielectric layer 128 'define the sidewall spacer 1 3 8 in the bit line opening 1 32. Then, the metal layer 140 is deposited on the fourth dielectric Layer 128 and filled in

490801

The bit line is opened in σ 1 3 2 to form a bit line plug. In general, when the metal layer 140 used as a bit line is deposited, a barrier layer 142 may be formed on the surface of the fourth dielectric layer 128, the sidewall spacer 138, and the conductive plug 110. The early halt resist layer 142 is mainly used to prevent the diffusion between the metal layer 14 formed later and the dielectric layer or the semiconductor substrate, thereby causing a spiking effect. It is worth noting that when the metal barrier layer 142 deposited here is intermittently distributed due to a poor manufacturing process, the above-mentioned wall spacer 138 can also prevent the bit line plug material from diffusing. Then, the above-mentioned metal layer 14 can be deposited on the surface of the barrier layer 142, and a bit line structure can be fabricated. In this way, a dynamic random access memory device having a bit-line capacitor (CUB) can be formed. Using the method of the invention has considerable benefits. Among them, by forming an isolation gap (a i Γ gap) between the bit line plug and the capacitor electrode plate, the low dielectric constant of the air can be used to reduce the bit line capacitance. In this way, even with the increase in the accumulation degree, the distance between the bit line plug and the capacitor becomes smaller and smaller, but by using the gap to produce the isolation effect, excessive parasitic capacitance can still be avoided, and Maintain normal operation between components. In addition, since the method of the present invention is completely compatible with the current CMOS manufacturing process, there is no need to perform additional steps or use other processing equipment when actually manufacturing on-line, and the situation without affecting production capacity and manufacturing cycle Next, make the required isolation gap. Although the present invention has been described above with reference to a preferred example, it is not intended to limit it.

490801

Page 16

The HyuQui diagram is simply explained by the above: < the upper and lower ¥ Λ the above content and the description of Γ combined with the many advantages of the invention and this invention, with the position: Άί „Guide = sectional view of the material, the second picture ϊ Steps of the μ memory element electrode; cross-section view of the conductor substrate 'The third figure is a cross-sectional view of a semiconductor substrate, the BPSG material layer (or nitride layer) is placed on the capacitor. The fourth picture is a cross-sectional view of a semiconductor substrate, USG material Layer (undoped silicate gl; steps above the BPSG layer or nitride layer); the fifth figure is a cross-sectional view of a semiconductor substrate with a gap on the side wall of the capacitor; and the sixth figure is a cross-sectional view of a semiconductor substrate, a meta wire plug The step f shows the difference can be easily understood: = shows the step according to the invention on the surface of the electrode formed according to the definition of the traditional process; shows the step on the surface of the electrode formed according to the present invention; Miscellaneous oxidative fragmentation) In the display according to the present invention, the spacers are formed according to the present invention.

Claims (1)

49〇fine_Please Patent Scope 1 · A method for forming a random access memory that forms an isolation gap between a bit line plug and a capacitor, the method provides at least-a semiconductor substrate, which has J semiconductor substrates; A crystal structure, and a first dielectric layer is covered above the crystal structure, and the upper surface of the first dielectric layer is provided with a capacitor, wherein an electrode of the capacitor can be passed through the first dielectric layer embedded in the first dielectric layer. A conductive plug, and the source / drain connection of the transistor, and a second dielectric layer surrounding the capacitor, covering the first dielectric layer and the second lightning-conducting plug below, Wherein the second conductive plug is embedded in the first dielectric layer and is at another source / drain of the transistor, and the top electrode of the capacitor is connected to cover all the bottom electrode and the second dielectric. An electric layer; f ^ forming a third dielectric film layer along the top electrode surface, the electric film layer and the first dielectric layer having a difference in money selection; depositing a fourth dielectric layer on the third dielectric film layer Above, its dielectric layer can completely cover the third The electric film and the capacitor = fourth have a flat upper surface, the fourth dielectric layer is different from the third dielectric, and there is a difference in etching selection; the fourth dielectric layer and the third dielectric are also etched between the exposed layers. The film layer and the second dielectric layer are formed until they reach the surface electrode on the second conductive plug to form a bit line opening; ",, and only," select the third dielectric film layer The etching process causes an electrical film layer to retract inwardly along the side wall of the bit line opening, and the shape is located between the edges of the side wall of the capacitor; and an isolation gap is formed along the side wall of the bit line opening. The side wall is closed Page 18 490801 6. Scope of patent application Opening from the gap; and making a bit line plug in the bit line opening, wherein the bit line plug and the capacitor have the isolation gap between them to reduce parasitic capacitance. 2. The method according to item 1 of the application, wherein the second dielectric layer and the fourth dielectric layer are made of undoped silicon glass (USG). 3. The method according to item 2 of the scope of patent application, in which the material of the third dielectric film layer can be selected from borophosphosilicate glass (BPSG), silicon nitride or any group thereof 4. The method according to item 3 of the scope of patent application The method, wherein the selective etching process performed on the second dielectric hafnium layer is performed using a hydrofluoric acid hafnium gas or a diphosphoric acid. "Wherein the above bottom part is electrically exposed to expose the bottom part 5. The method of item 1 of the patent application range is extremely higher than the second dielectric layer by about 3,000 to 80,000 angstroms. . According to the method of applying for the first item in the scope of patent application, douzhong pi + / pi e shan guangyi eight T side wall 璧 疋 is composed of silicon oxide with a thickness of about 200 to 50 angstroms. 490801 VI. Application for Patent Scope 8. The method according to item 7 of the patent application scope, in which the above-mentioned sidewall gaps are formed by using a low-pressure chemical vapor deposition method using TEOS material as a reactant. • ..... one, w ... ,, Si Fenru < cut / ~ • method of making biliary biliary, the method includes at least the following steps: · forming a plurality of gate structures on a semiconductor substrate as a word line Use; ^ define the source / non-electrode region in the semiconductor substrate between the gate structures; redundant first electrical layers on the semiconductor substrate, and cover the gate structure and the source / drain Area; etching the first dielectric layer until reaching the surface of the semiconductor substrate is two to form a first opening between adjacent gate structures and expose the upper surface of the source / drain area; Ώ 1 pole area The mu- opening is connected to the source " and the second conductive-aligned conductive plug can be divided into a first-conductive plug and ^. And the first conductive plug is used to establish a p-thunder with the capacitor; 5 Γ g ^ conductive plug is used to connect with the bit line; upper; electrical layer on the first dielectric layer and the self-aligned conductive plug engraved the second dielectric layer until reaching the first, to Form the bottom electrode opening pattern on the fth person; ::: The pattern on the upper surface will expose the top surface of the first conductive plug ; Fly end Page 20 6. The scope of the application for a patent deposits a first conductive layer on the bottom portion to define a bottom electrode; a sidewall of the opening pattern and a bottom form a dielectric layer to expose a portion of the bottom electrode side wall. Bin or Dianjin Dielectric layer on the surface of the bottom electrode · Diameter W 2; A second conductive layer is defined in the opening pattern of the bottom electrode of the Lei Xuanren to define; the page portion; the t-plane and filling the dielectric dielectric film layer … The third TL ^ M has an etching choice difference between the two; 啻 四 四 四 四 四 电 "Electric θ above the third dielectric film layer, JL in the four dielectric layer can completely cover the bottom ^ The fourth has a flat sweep on the first and the capacitor, and the upper surface of the capacitor, and the fourth dielectric has a difference in choice between money and engraving; Θ ^ one; | Also = the fourth dielectric layer and the third dielectric film layer 'until the second conductive plug-in' electrical opening is reached; the upper surface of the soil is formed to form a bit line electrical film and the dielectric layer is selected Sexual sting procedure, Qian third introduced the outer edge of the side wall of the top electrode; There is a gap between the gaps; the side wall of the bit line opening forms a gap wall to seal the isolation plug "ΐίίίίίΓ: in the opening of the element line ', where the bit line is inserted into the gap between the valley and the gap can be Reduce parasitic capacitance. 10. The method according to item 9 of the scope of patent application, in which the above-mentioned second 490801 VI. Patent-applying dielectric layer and the fourth dielectric layer are composed of undoped silicon glass (USG). 11. The method of claim 10, wherein the third dielectric film layer is made of borophosphosilicate glass (BPSG) or silicon nitride. 12. The method according to item 11 of the scope of patent application, wherein the above-mentioned selective etch-down procedure for the triple dielectric film layer is performed using hydrogen acid vapor hot phosphoric acid. / The bottom edge side 13. The method according to item 9 of the scope of patent application, wherein the step of the second dielectric layer described above can cause the upper surface of the second dielectric layer to be lower than the remaining electrode by about 300 to 8000 angstroms, and expose Part of the bottom electrode = wall. 14. The method of claim 9 in the patent application range, wherein the upper dielectric film layer has a thickness of about 300 to 1,000 angstroms. < Brother III 15. According to the method of claim 9 in the scope of patent application, the composite spacer wall is composed of silicon oxide having a thickness of about 200 to 50 angstroms. 16. Side wall 16. According to the method of claim 15 in the scope of patent application, the partition wall in 1 is formed by using the blue material as the reactant, and the method of the side wall product is used. -^ Resolve dry lice Page 22 490801 6. Scope of patent application 17. For the method of claim 9 of the patent scope, the self-aligning conductive plug mentioned above is made of polycrystalline silicon material. 18. The method according to item 9 of the scope of patent application, wherein the bottom electrode has a hemispherical stone grain surface to increase the surface area of the capacitor. 19. The method according to item 9 of the application, wherein the first conductive layer and the second conductive layer are made of doped polycrystalline silicon. 20. The method according to item 9 of the scope of patent application, wherein the thickness of the second conductive layer is about 500 to 1000 Angstroms. Page 23 _1