TW499731B - Method for forming gap isolation between bit-line contact and capacitor-under-bitline DRAM cell - Google Patents

Abstract

A method for forming air gap isolation between bit-line contact and capacitor-under-bitline DRAM cell is disclosed. It comprises the following steps: (1) forming a dielectric layer on a semiconductor substrate; (2)etching out a part of the first dielectric layer and forming holes in it; (3) depositing silicon material on the first dielectric layer and filling in the holes; (4) removing a part of the silicon material; (5) forming a capacitor dielectric layer on the silicon material; (6) making a conductive layer to cover the capacitor dielectric layer; (7) forming spacers on the sidewalls of the conductive layer; (8) depositing a second dielectric layer on the first dielectric layer and the conductive layer; (9) etching back the second dielectric layer till exposing a part of the sidewall spacer; (10) removing the spacer to form an air gap on the position of the spacer; (11) forming a third dielectric layer on the second dielectric layer, conductive layer and air gap, where the third dielectric layer has poor gap fill-in capability; (12) removing a part of the third, the second and the first dielectric layers to form a bit-line contact in the first dielectric layer; and (13) forming a first conductive plug in the bit-line contact.

Description

499731 V. Description of invention α) Field of invention: The present invention relates to a dynamic random access memory cell (DRAMC e 1 1) of a capacitor under bit 1 ine, especially a capacitor under bit line A method for forming a gap isolation between a dynamic random access memory cell and a bit line contact, and a method for manufacturing a self-aligned top electrode in a dynamic random access memory cell of a capacitor below a bit line.背景 Background of the invention: Dynamic random access memory cell (DRAM Cel 1) is composed of a transistor and a capacitor. One end of the capacitor is connected to the doped region of the transistor, and the other end of the capacitor is connected to a reference potential. Electrical contact of the source region to store digital information in the capacitor, and pass the metal-oxide-semiconductor field-effect transistor (M 0 SFET), word line (w 〇rd 1 ine) and bit line (bit 1 i ne ) Array to get the digital data in the capacitor. As the accumulation of DRAM continues to increase with the progress of the semiconductor industry, the height of the capacitor in the DRAM must be increased. However, as a result of increasing the height of the capacitor, the dynamic random access memory bit structure of the capacitor below the bit line will Element line contact is difficult to form (due to the high aspect ratio i). In addition, the isolation between the bit line contact and the top electrode of the capacitor in the capacitor memory cell structure of the bit line is also reduced (for example:

Page 6 499731 V. Description of the invention (2) Due to misalignment. ) Generally, the method to solve the problem of bit-line capacitors due to the increase in height of bit-line capacitors is that the bit-line contact in the cell structure is difficult to form. The outer sidewall of the capacitor is also exposed, so that As the bottom electrode. In this way, the height of the valley device can be reduced, and the size of the unit memory cell capacitance (cel 1 capacitance) can still be maintained above 25fF. However, the dynamic random access memory cells of the capacitors under each bit line formed by the above method are increased due to the increased capacitance between the bit line to the bottom electrode and the bit line to the top electrode, so the total bit line capacitance (bit -line capacitance) (also known as parasitic capacitance) (per column) is also significantly increased, and the increase in the total bit line capacitance will reduce the strength of the memory cell signal and make part of the effort to increase the memory cell capacitance ineffective. — In addition, another way to reduce the total bit line capacitance is to use a low dielectric ~ electrical material. However, this will make the rapid thermal processing (RTP) used in contact barriers such as TiSiX structures need to be very hot, so low-dielectric materials are usually avoided. «For the production of dynamic random access memory for bit-line capacitors, please refer to the n Method for fabricating capacitor-under-bit 1i ne (CUB) dynamic random access memory disclosed in US Patent No. 5 8 9 3 7 3 4 (DRAM) using tungesten 499731 V. Description of the invention (3) Landing plug contacts 1 '. Now using Figure 1A to Figure 1D, the traditional method of forming the dynamic random access memory of the crown shape capacitor under the bit line is briefly described as follows:

Please refer to FIG. 1A. First, a shallow trench isolation region 102 is formed, a transistor gate structure 104, a drain / source 106, and a first inner polycrystalline dielectric layer. (Inter-poly dielectric layer) 108. A second inner polycrystalline dielectric layer 1 12 is formed on a semiconductor substrate 100 of a polycrystalline silicon plug (polysilicon) ii using a conventional technique. Then, a part of the second inner polycrystalline dielectric layer 1 1 2 is removed to form a contact hole (c ο n t a c t h ο 1 e) 1 1 3 so that a capacitor formed later can make electrical contact with the transistor. Then refer to FIG. 1B to sequentially form the bottom electrode, the inter-electrode dielectric layer and the top electrode of the capacitor in order to complete the fabrication of the capacitor. Here, the bottom electrode of the capacitor is made of Hemi-Spherical Grain (HSG) which can effectively increase the surface area of the storage electrode. First, a he in ispherica 1 grains silicon (HSG-Si) layer 4 is formed on the second inner polycrystalline dielectric layer u 2 and filled in the contact holes 1 1 3 ′, and then coated with light Resist (not shown) in the contact hole 113 to protect the required HSG-Si 114, and then etch back or chemical mechanical polishing the JJSG-Si 11 4 to remove the polycrystalline dielectric layer 11 located in the second inner layer. HSG-Si 114 on 2 and finally remove the photoresist.

Page 8 499731 V. Description of the invention (4) A dielectric thin film 1 1 6 is then deposited on the surface of the HSG-Si 1 14 structure as the dielectric layer of the capacitor. The dielectric thin film 1 1 6 can be oxidized Compound layer, nitride / oxide (N / 0) composite layer composed of material layer, nitride layer, or oxide layer, nitride layer., Oxide / nitride / oxide composite composed of oxide layer Layer (0 / N / 0). Next, a conductive layer 1 1 8 is deposited on the second inner polycrystalline dielectric layer 11 2, and the entire dielectric film 1 1 6 is covered as the top electrode of the capacitor. Then, a portion of the conductive layer 1 18 directly above the second inner polycrystalline dielectric layer 1 12 is removed to expose a portion of the second inner polycrystalline dielectric layer 112, thereby completing the production of a crown shape capacitor. Referring to FIG. 1C, an inter-layer dielectric layer 120 is first formed on the conductive layer 118 and the second inner polycrystalline dielectric layer 112, and then a part of the inner layer dielectric layer 120 is removed. A portion of the second inner polycrystalline dielectric layer 1 12 is formed until a portion of the upper surface of the polycrystalline silicon plug 1 10 is exposed to form a bit line contact hole 1 2 1. Please refer to FIG. 1D, and then use a method such as sputtering to form a conductive plug 12 as a conductive connection in the bit line contact hole 1 21 (ie, as a bit line). The conductive plug 1 2 2 may include a W / TiN / Ti composite layer composed of a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer. From Figure 1D, it can be found that when the height of the crown capacitor under the bit line increases and the distance from the bit line to the cell capacitor decreases, the total bit

Page 9 499731 V. Description of the invention (5) The line capacitance will increase, and usually the total bit line capacitance is about 100 times the cell capacitance in each cell, so reading from the bit line will be reduced. The strength of the retrieved memory cell signal (this can be known from the following formula ... The change in the intensity of the memory cell signal in the bit line before and after reading = the intensity of the memory cell signal read in the bit line X (Cell capacitance / total bit line capacitance in a mother cell)). In addition, when the height of the crown capacitor below the bit line increases and the critical dimension (CD) is small, the formation of the top electrode will be a difficult and critical step. Therefore, it is very important to avoid the problems mentioned above when manufacturing bit-line capacitor DRAM. Object and Summary of the Invention: One object of the present invention is to form a gap isolation between a dynamic random access memory cell of a capacitor below a bit line and a bit line contact, so as to provide a minimum dielectric isolation between a bit line contact and a capacitor top electrode. Therefore, the purpose of reducing the parasitic capacitance in the dynamic random access memory cell of the bit line capacitor is achieved. Another object of the present invention is to manufacture a self-aligned top electrode in a dynamic random access memory cell of a capacitor below a bit line to save process costs. Another object of the present invention is to dynamically store capacitors under bit lines.

Page 10

499731 V. Description of the invention (6) Take the self-aligned top electrode from the memory cell, so that the isolation distance between the bit line contact and the top electrode of the capacitor can be controlled, and by increasing the size of the bit line contact window, Solve the phenomenon of short circuit between the bit line contact and the top electrode of the capacitor caused by incorrect pattern line contact (P a 11 er η T ransfer). According to an embodiment of the present invention, an air gap is formed between the dynamic random access memory cell (DR AMC e 1 1) of the proposed capacitor under bit line and the bit line. A method of isolation, which includes the following steps:

Page 11 499731 V. Description of the invention (7) 13 Dielectric layer to form bit line contact holes in the first dielectric layer. () Forming a first conductive plug in the bit line contact hole. Before forming the first dielectric layer on the semiconductor substrate, the method further includes the following steps: (1) forming a plurality of transistors on the semiconductor substrate. (2) forming a fourth dielectric layer on the plurality of transistors. And (3) forming a second conductive plug in the fourth dielectric layer, wherein the hole corresponds to the second conductive plug. In addition, the material of the first dielectric layer includes an oxide or silicon dioxide formed from Tetraethyl-orthosilicate (TEOS). The silicon material contains hemispherical grain silicon, and the capacitor dielectric layer includes one of the following: a nitride / oxide (N / 0) composite layer, an oxide / nitride / oxide composite layer (0 / N / 0 ), T a 20 5, T i 0 2. As for the material of the conductive layer, doped polycrystalite (d 0 p e d ρ ο 1 y s i 1 i c ο η). In addition, the material of the spacer structure includes borophosphosilicate glass (BPSG) or silicon nitride (for example, silicon nitride formed by low-pressure chemical vapor deposition (LPCVD)), and the removal method includes wet etch-back. In addition, the material of the second dielectric layer includes an oxide layer formed using a high density plasma (HDP), or undoped silica glass (USG) formed in a 03-TE0S gas environment, and a third The dielectric layer includes PE-TE0S (plasma enhanced TEOS) or PE-SiH 4. The first conductive plug includes a polycrystalline silicon plug.

Page 12 499731 V. Description of the invention (8) Where the material of the spacer structure is borophosphosilicate glass (BPSG) or silicon nitride, the formation method includes: (1) forming a borophosphosilicate glass (BPSG) layer or A silicon nitride layer is formed on the first dielectric layer and the conductive layer. (2) Use a dry plasma etch-back method to remove part of the borophosphosilicate glass (BPSG) layer or silicon nitride layer to form a spacer structure on the side wall of the conductive layer. In addition, if the material of the second dielectric layer and the material of the spacer structure are respectively undoped silica glass (USG) and borophosphosilicate glass (BPSG), the etchant used in the wet etchback method may include HF gas. In addition, if the material of the second dielectric layer and the material of the spacer structure are made of undoped stone glass (USG) and low pressure chemical vapor deposition (Low Pressure Chemical V a ρ or Depositi ο η; LPCVD), respectively When the nitride is formed, the etchant used in the wet etch-back method may include hot phosphoric acid. According to another embodiment of the present invention, a method for manufacturing a self-aligned top electrode in a dynamic random access memory cell of a bit-line capacitor is provided, including the following steps:

Page 13 499731 V. Description of the invention (9) On the surface of silicon material. (6) A conductive layer is formed to cover the capacitor dielectric layer. (7) A non-conformal structural layer is formed on the conductive layer. (8) Remove part of the non-conformal structural layer to expose part of the upper surface of the conductive layer. (9) Using the remaining non-conformal structural layer as a mask, remove part of the conductive layer to form a self-aligned capacitor top electrode. (1 0) Remove the non-conformal structural layer. After removing the non-conformal structure layer, the method further includes the following steps: (1) forming a second dielectric layer on the conductive layer and the first dielectric layer. (2) Remove part of the second dielectric layer and part of the first dielectric layer to form bit line contact holes in the first dielectric layer and the second dielectric layer. (3) A first conductive plug is formed in the bit line contact hole. Before forming the first dielectric layer on the semiconductor substrate, the method further includes the following steps: (1) forming a plurality of transistors on the semiconductor substrate. (2) forming a third dielectric layer on the plurality of transistors. (3) A second conductive plug is formed in the third dielectric layer, and the hole corresponds to the second conductive plug. In addition, the material of the first dielectric layer includes an oxide or two atmosphere silicon formed of Tetraethyl-ortho silicate (TEOS). The silicon material includes hemispherical grain silicon, and the capacitor dielectric layer includes one of the following: a composite layer of a vapor / oxide (N / 0), a composite layer of an oxide / nitride / oxide (0 / N / 0 ), Ta 20 5, T i 0 2. As for conductivity

Page 14 499731 V. Description of the Invention The material of the layer includes doped polysilicon. The material of the non-conformal structure layer includes a polymer (po 1 ymer), and the forming method of the polymer includes using 6-8seem C4F8, 360-480sccm CO, and 400-800 W power to form. The material of the second dielectric layer includes an oxide, and the first conductive plug includes a polycrystalline stone plug. In addition, the method for removing the non-conformal structural layer includes a wet etching method, and the method for removing a part of the conductive layer includes a plasma #etching method. The wet-etching method mentioned above involves the use of dilute hydrofluoric acid or SPM. In addition, according to another embodiment of the present invention, a method for manufacturing a self-aligned top electrode in a dynamic random access memory cell of a bit line capacitor includes the following steps: (0) forming a first dielectric layer on the On a semiconductor substrate. (2) I etch a part of the first dielectric layer to form holes in the first dielectric layer. (3) form a silicon material on the first dielectric layer and fill the holes. (4) Remove part of the silicon material on the first dielectric layer, and the remaining part of the silicon material is used as the bottom electrode of the capacitor. (5) Form the capacitor dielectric layer on the surface of the silicon material. (6) ) Forming a conductive layer to cover the capacitor dielectric layer. (7) forming a first conformal structural layer on the conductive layer. (8) forming a non-confomal structural layer on the first conformal layer (C ο nf 〇rma 1) on the structural layer. (9) Remove part of the non-conformal structural layer to expose part of the upper surface of the first conformal structural layer. (1 0)

Page 15 499731 V. Description of the invention (11) The remaining non-conformal structural layer is a mask, and a part of the first conformal structural layer and a part of the conductive layer are removed to form a self-aligned capacitor top electrode. (1 1) Remove the non-conformal structural layer. The empty t: into the step. The step: the interlayer row T ^ t includes the first and second layers, the structure and the post-layer structure. Angular, one-in-one, U, tr, / 1T ##, and removability. In the W-layer "° 丨 ^ ¾, select its conductivity 1) copies of the adjacent part of C 2) phase C is large. The positive gap on the square of the fraction β—

, Layered structure} 3 ± P connected to 4) lines (elements. The shape of the layer is electrically, the junction angle of the dielectric layer and the first layer of the first component is between the second layer and the second layer of the second layer. The second part of the intermediary part is the second part of the dielectric layer. The first part of the second part of the middle part of the middle part and the hole layer of the electrical contacting dielectric line is located in the hole of the hole and the second part of the electrical contact formation.) / 5

Outside 1) This C step is included in the following steps: The structure can be followed by the protection of bp to remove the layer C) / E2. {部 圈: The space between the layered dielectric layer and the layer structure angle is maintained at the first position 0. The recursive selection of the node angle is provided-the first layer of the dielectric shape is formed at the node angle. Guarantee the layer and Λ— /, 3 on C. The gap in the layer, the dielectric space, the first space, the first space, and the filling junction, the corner protection layer, the dielectric space, the first and the first, β—removal of the structure, the corner protection, and the first part

Conjunction \) / Angle 1 4 Guaranteed C The contact angle of the connection layer structure element in the same hole is formed into a conformal shape 2 and 3D, and the layered electrical structure is connected to a corner. The same in construction: / hole contact wiring element is located in the plug conductance

Page 16 499731 V. Description of the invention (12) Before forming the first dielectric layer on the semiconductor substrate, the method further includes the following steps: (1) forming a plurality of transistors on the semiconductor substrate. (2) forming a third dielectric layer on the plurality of transistors. (3) A second conductive plug is formed in the third dielectric layer, and the hole corresponds to the second conductive plug. In addition, the material of the first dielectric layer includes an oxide or silicon dioxide formed from Tetraethyl-orthosilicate (TEOS). The silicon material contains hemispherical grain silicon, the capacitor dielectric layer includes one of the following: a nitride / oxide (N / 0) composite layer, an oxide / nitride / oxide composite layer (0 / N / 0), Ta 20 5, Ti02. The material of the conductive layer includes doped polysilicon. The material of the second dielectric layer includes an oxide, the first conductive plug includes a polycrystalline silicon plug, and the material of the second conformal structure layer includes LP-TEOS. In addition, the method for removing the non-conformal structure layer includes a wet etching method, and the method for removing a part of the conductive layer and part of the first conformal structure layer includes a plasma etching method. The wet etching method includes the use of dilute hydrofluoric acid or SPM. Among them, the material of the conformal structure layer can be selected from those having a high wet etching selectivity compared to the conductive layer, and the thickness thereof is about 300-500 angstroms. As for the formation method thereof, LPCVD is included. In addition, if the material of the conductive layer is polycrystalline silicon, the material of the conformal structure layer may include LP-Si N or an oxide. The material of the above non-conformal structural layer includes poly

Page 17 499731 V. Description of the invention (13) Compound (ρο 1 ym e r), and the formation method of this polymer includes using 6-8sccm C4F8, 360-480sccm C0, and 400-800W power to envy

to make. The method for selectively restoring a part of the conductive layer includes APM (Ammonia peroxide mixture) (APM is an aqueous solution containing ammonia and hydrogen peroxide. Wet etching method). Detailed description of the invention: One object of the present invention is to form a gap isolation between the dynamic random access memory cell of the bit line capacitor and the bit line contact, so as to provide a small medium between the bit line contact and the valley as the top electrode. Electrical isolation, so as to achieve the purpose of reducing the power trough off-line device to access the parasitic capacitance in the memory cell. Another object of the present invention is to manufacture a self-aligned top electrode in a dynamic random access memory cell of a capacitor below a bit line to save process costs. Another object of the present invention is to make self-aligned top electrodes in bit line capacitors and dynamic random access memory cells, so that the isolation distance between the bit line contacts and the top electrode of the valley can be controlled, and The size of the bit line contact window is increased to solve the phenomenon of short circuit between the bit line contact and the top electrode of the capacitor caused by the incorrect pattern line contact pattern transfer. '

499731

The present invention provides a method for dynamic random access of a capacitor below a bit line to form a gap isolation between the contact between the memory cell and the bit line. A preferred embodiment is now made in the white c valley state, and the invention is described in detail as follows: Please refer to FIG. 2A. First, a semiconductor substrate 200 is provided, in which a half or tower substrate 200 can be a < 1 00 > or < 11 1 > single crystal silicon or other types of crystal orientation ^ Semiconductor materials, such as gallium arsenide (GaAs), germanium (Ge), or silicon on insulator, etc. 9 Then use known techniques to form isolation areas such as shallow trench isolation bars, ( Shallow trench isolation) 20 2 in the semiconductor substrate 200 :: Insulation effect is then formed on the semiconductor substrate 200, in order to form a complex number, a transistor gate structure 204, and an electrode / source 2 The transistor gate structure 204 is used as a word line, and the outer layer is an insulating material. The transistor gate structure 204 here may include a silicon dioxide layer, a polycrystalline silicon layer, Tungsten silicide layer, silicon nitride protective layer, etc., and the above drain / source 2 〇 The 6 series is formed by ion implantation. Since the above-mentioned process is made by the technology known in the past and is not the focus of the present invention, it will not be described in detail. Then on the semiconductor substrate 200, the shallow trench isolation area 2 2, and the gate An internal polycrystalline dielectric layer (inter ~ p0ly dielectric layer) 208 is formed on the structure 204 and the non-source / source 206. After that, a self-etching technique is used to form The first conductive plug 2 1 0 of the self-aligned contact is in the inner polycrystalline dielectric layer 2 0 8.

Page 19 499731 V. Description of the invention (15) Electrical plug 21 〇 may be a polycrystalline silicon plug (p 〇1 yp 1 ug), in this preferred embodiment, chemical vapor deposition (Chemical Vapor Deposition) CVD) deposits polycrystalline silicon and backfills into the contact holes. The polycrystalline silicon is then re-used, such as back engraving or chemical mechanical polishing, to form the polycrystalline silicon inspection described above. In a preferred embodiment, the polycrystalline stone of the present invention is a compound polycrystalline stone (i η-situd 〇pedp 〇1 ysi 1 ic η) or doped polycrystalline stone (doped) polysilicon). Subsequently, a first dielectric layer 212 for insulating is formed on the upper surface of the inner polycrystalline dielectric layer 208 and the first conductive plug 2 10 (the first dielectric layer 2 1 2 is used here). As the inner polycrystalline dielectric layer). After that, a portion of the first dielectric layer 2 1 2 is removed to form a contact hole (c ο n t a c t h ο 1 e) 2 1 3 so that a capacitor formed later can make electrical contact with the transistor. Among them, the inner polycrystalline dielectric layer 208 and the first dielectric layer 2 12 may be oxides or dioxides formed from Tetraethyl-orthosilicate (TEOS). Subsequently, referring to FIG. 2B ′, the bottom electrode, the inter-electrode dielectric layer and the top electrode of the capacitor are sequentially formed to complete the fabrication of the capacitor. The material of the bottom electrode of the capacitor includes doped polycrystalline silicon. The manufacturing process is based on the conventional hemi-Spherical Grain (HSG) process, which can effectively increase the surface area of the storage electrode. One note. On the first day, a silicon layer (hem i spherical gH ins ^ silicon; HSG-Si) 214 is formed on the first dielectric layer 212 and filled in the holes 2 1 3 ′, and then coated with a photoresist ( Not shown) at the contact hole

499731 5. In the description of the invention (16), the HSG-S i 2 1 4 required for protection is used as the bottom electrode of the capacitor, and then etch back or chemical mechanical polishing is used to remove the first dielectric layer 21 HSG-Si 214 on 2 and finally remove the photoresist. The HSG-S i 2 1 4 formation step is as follows: firstly deposit a silicon thin film and a silicon seed (nuc 1 ei) in sequence, for example, a silicon-containing gas such as Si can be used to reduce Si 2H to form, and the process temperature is about The temperature is between 450 ° and 600 ° C, the pressure is about 1E (-310-3 to 1 Ε (-5) Torr, and then a thermal tempering process is performed in a high vacuum environment to form Hemispherical silicon grains. The process temperature is about 450 to 600 degrees Celsius, and the pressure is about 1 Ε (-7) to 1 Ε (-9) Torr. HSG-Si 2 14 is then extended. A dielectric film 2 1 6 is deposited on the surface of the structure as a dielectric layer of the capacitor. Generally, the dielectric film 2 1 6 can be a nitride / oxide (N / 0) composite layer. Or oxide / nitride / oxide composite layer (0 / N / 0) composed of an oxide layer, a nitride layer, or an oxide layer. Or a high dielectric film For example, Ta 20 5 and Ti 0 are thin. Next, a conductive layer 2 1 8 is deposited on the first dielectric layer 2 1 2 and the entire dielectric thin film 2 1 6 is covered as the top electrode of the capacitor. Then, a portion of the conductive layer 218 directly above the first dielectric layer 2 1 2 is exposed to expose a portion of the first dielectric layer 212, thereby completing the production of a crown shape capacitor. In this preferred embodiment, The deposition method of the conductive layer 2 1 8 may be a Low Pressure Chemical Vapor Deposition (LPCVD) method.

Page 21 499731 V. Description of the invention (17) Its preferred thickness is about 5 0-1 0 0 0 angstroms, and the conductive layer 2 1 8 can use doped polycrystalline silicon (d 〇ped ρ ο 1 ysi 1 ic ο η), i η-situ doped polysilicon. Please refer to FIG. 2C. After the capacitor is manufactured, a spacer structure 2 1 9 is formed on the side wall of the conductive layer 2 18. The material of the spacer structure 2 1 9 includes borophosphosilicate glass (BPSG) or Silicon nitride (the formation method includes low pressure chemical vapor deposition (LPCVD)). If the material of the spacer structure 2 1 9 is borophosphosilicate glass (BPSG) or silicon nitride, the preferred formation step is: firstly deposit a thickness of about 4 on the first dielectric layer 21 2 and the conductive layer 21 8. 0 0-6 0 0 angstrom borophosphosilicate glass (BPSG) layer or silicon nitride layer, and then use a dry plasma etch-back method to remove part of the borophosphosilicate glass (BPSG) layer or silicon nitride layer to A spacer structure 219 is formed on a sidewall of the conductive layer 2 1 8. A second dielectric layer 22 0 is then formed on the first dielectric layer 21 2 and the conductive layer 2 18 as an inner layer dielectric layer. The second dielectric layer 2 2 0 is etched back and forth with, for example, a dry plasma, until a portion of the surface of the spacer structure 2 1 9 is exposed. The second dielectric layer 220 includes an oxide layer formed using high density plasma (HDP), or undoped silica glass (USG) formed in a 03-TE0 S gas environment. Then referring to FIG. 2D, using a wet etch-back technique to remove the spacer structure 2 1 9 to form a gap at the location of the spacer structure 2 1 9 499731 V. Description of the invention (18) 2 2 4 The space 2 2 4 is filled with air, so it can provide the minimum dielectric isolation between the bit line contacts formed later and the conductive layer 2 1 8. If the material of the second dielectric layer 220 is USG and the material of the spacer structure 219 is borophosphosilicate glass (BPSG), the etchant used in the wet etch-back technology may include HF gas. Among them, the etching rate ratio of HF gas to borophosphosilicate glass and USG is about 100 0: 1, so the HF gas can anisotropically remove the spacer structure 2 1 9 made of borophosphosilicate glass, and in the gap A gap 2 2 4 is formed at the position of the wall structure 2 1 9 (this is because the amount of the USG that is removed at the same time as the space wall structure 2 1 9 is removed). In addition, if the material of the second dielectric layer 220 is USG, and if the material of the spacer structure 2 1 9 is silicon nitride (LP-S i N) formed by a low-pressure chemical p vapor deposition method, the wet type The etchant used in the etch-back technology may include thermal phosphoric acid, where the etching rate ratio of thermal phosphoric acid to LP-S i N and USG is about 100: 1, so the thermal phosphoric acid can be anisotropically removed as LP- The spacer structure 219 of SiN, and a gap 2 2 4 is formed at the position of the spacer structure 219 (this is because the amount of _USG removed is very, very small while the spacer structure 2 1 9 is removed. ). Referring to FIG. 2E, a third dielectric layer 226 is then deposited on the second dielectric layer 220, the conductive layer 21 8 and the gap 22 4 as an inner dielectric layer. The third dielectric layer 2 2 6 has poor gap filling ability, which can quickly form a protruding portion at the top edge of the gap 2 2 4 # and quickly seal the top hole (ie, the gap 2 2 4 can Securely encapsulated inside the third dielectric layer 2 2 6). What about the third dielectric layer 22 6? £ -ugly 08 (? 1 & 31118 enhanced TEOS) or PE-SiH4. Then remove part of the third dielectric layer

Page 23 499731 V. Description of the invention (19) Touch 226, partly damage the first dielectric layer 22 0 and part of the first dielectric layer 212, and partially expose the top surface of the polycrystalline stone 2 1 0, After forming the bit line hole 2 2 7 °, please refer to FIG. 2F, and then use a method such as sputtering to form a second conductive plug 2 2 8 as a conductive connection line in the bit line contact hole 2 2 7. The second conductive plug 228 includes a W / TiN / Ty | combined layer composed of a titanium (Ti) layer, a titanium nitride f layer, and a tungsten (W) layer. ΜίΠϊ Provides a kind of dynamic random access to the bit line power-down device. I k self-aligns the top electrode in the memory cell. A preferred embodiment has been prepared, and the present invention is expected to be as follows: the semiconductor substrate is formed at 3 ° to form a "channel 3 0 2, a plurality of electricity a, a bow holder, 4 shide 0, and an eight-leaf exhibition in the engraving field of the sun." Gate structure 304, drain / source 306, inner multi-layer "electrical layer 308", first self-aligned contact = 312, and then remove part of the A dielectric layer contact 313) is used to make electrical contact. The materials that can be used to make the bottom electrode of the capacitor with Dingtong 4 are the conventional materials, such as silicon and silicon, and the grain (Hemi-sphenw; plus the surface area of the storage electrode). The bottom electrode of the spherical silicon container is made of iron ($ 7.11, HSG) as an example to make electrical and top electrodes. . First formed to be used as electricity

Page 24 499731 V. Description of the invention (20) Hemispheric 1 grains silicon (HSG-Si) 3114 of the bottom electrode of the trough, and then sequentially forming the dielectric between the plates of the capacitor Layer of dielectric film 3 1 6 and the conductive layer 3 1 8 ′ of the top electrode of the capacitor to complete the fabrication of the capacitor. The process of FIGS. 3A to 3b is compared with the process of FIGS. 2A to 2B, except that the conductive layer 3 1 8 shown in FIG. 3b is formed on the first dielectric layer 3 1 2. After covering the entire dielectric film 3 1 6, the portion directly above the first dielectric layer 3 丨 2 is not removed immediately to expose part of the first dielectric layer 3 1 2 (Figure The conductive layer 2 1 8 shown in the second B is formed on the first dielectric layer 3 1 2 and covers the entire dielectric film 2 1 6, and then it is positioned on the first dielectric layer 2 1 The part directly above 2 is removed to expose part of the first dielectric layer 212.), other processes are the same as described in FIG. 2A to FIG. 2B, so the details will not be repeated. Then referring to FIG. 3C, a non-conformal (η〇η-connfoma 1) structure layer 3 1 9 is formed on the conductive layer 3 1 8, wherein the non-conformal structure layer 3 1 9 has a conformal property ( c ο nf 〇rma 1) Poor, its poor step coverage characteristics are similar to electric 楽: enhanced chemical vapor deposition (ρ 1 asmaenhanced chemical vapor deposition (PECVD) thin film, so the top layer is thicker than the bottom layer. Non-conformal structural layer 319.

Page 25 499731 V. Description of the invention (21) 6-8sccm C4F8, 3 6 0 -4 8 0 sccm C0 and 4 0 0 -8 0 0W power to form a polymer with a thickness of about 1000-200 0 Angstroms Floor. Then, a part of the non-conformal structural layer 3 1 9 is removed to expose a part of the upper surface of the conductive layer 3 1 8. The method for removing the part of the non-conformal structural layer 3 1 9 can be similar to the method of removing the organic BARC. Since the non-conformal structural layer 3 1 9 has poor step coverage characteristics, the thickness of the bottom and side walls of the non-conformal structural layer 3 1 9 formed here will be thinner than the top (about 25% of the top thickness- 30%), so after removing part of the non-conformal structural layer 3 1 9 to expose part of the upper surface of the conductive layer 3 1 8, only a part of the top of the non-conformal structural layer 3 1 9 is consumed. (Approximately 35% -50%). ⑩

Next, referring to FIG. 3D, using the remaining non-conformal structural layer 3 19 as a mask, a part of the conductive layer 3 1 8 is removed to form a self-aligned capacitor top electrode. Subsequently, conventional techniques (eg, dilute hydrofluoric acid 100: 1 and SPM) are used to remove the non-conformal structure layer 3 1 9. If the material of the non-conformal structural layer 3 1 9 is a polymer, the method for removing a part of the conductive layer 3 1 8 includes a plasma etching method. Usually, the selectivity of plasma etching of polycrystalline silicon relative to polymer is about 1.5: 1 to 2: 1, so it will be enough to etch away part of the conductive layer 3 1 8 and dig a hole for subsequent bits. The progress of the line contact process. It is worth noting here that the top electrode of the capacitor formed here has a hole (to form a bit line contact) that is self-aligned to the side wall of the capacitor. Furthermore, with the self-alignment method described above, the lithography step of the conductive layer 3 1 8 will become a non-critical step.

Page 26 499731 V. Description of the invention (22) Please refer to FIG. 3E, and then deposit a second dielectric layer 32 0 on the conductive layer 318 and the first dielectric layer 3 1 2. Then remove part of the second dielectric layer 3 2 0 and part of the first dielectric layer 3 1 2 until the upper surface of the polycrystalline silicon plug 3 1 0 is exposed to form a bit line contact hole 3 2 1. The second dielectric layer 3 2 0 is used as an inner dielectric layer, and its material includes an oxide. After referring to FIG. 3F, a method such as sputtering is used to form a second conductive plug 3 2 4 as a conductive connection in the bit line contact hole 3 2 1. The second conductive plug 3 2 4 includes a W / TiN / Ti composite layer composed of a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer. Because in the above embodiment (shown in FIGS. 3A to 3F), the self-aligned capacitor top electrode formed has a protruding portion, and this protruding portion will cause the bit line to form when the subsequent bit line contact is formed The probability of a short circuit between the contact and the top electrode of this capacitor increases. Therefore, in order to enable the implementation of the present invention to have better effects, another preferred embodiment made of a crown-type capacitor is described in detail in the present invention for manufacturing in a dynamic random access memory cell of a bit-line capacitor. The method of self-aligning the top electrode is as follows: please refer to FIG. 4A to FIG. 4B, and sequentially form a shallow trench isolation region 4 0 on a semiconductor substrate 4 0 2, a plurality of transistor gate structures 4 0 4 Drain / source 406, inner polycrystalline dielectric layer 408, first conductive plug 4 1 0 in self-aligned contact, first dielectric layer 4 1 2 and then removing part of the first dielectric The electrical layer 4 1 2 is used to form a contact hole (c ο ntacth ο 1 e) 4 1 3 so that the capacitor formed later can make electrical contact with the transistor.

Page 27 499731 V. Description of the invention (23) Generally, the material for the bottom electrode of the capacitor contains doped polycrystalline silicon, and here is a conventional semi-spherical silicon crystal (Hemi-Spherical) which can effectively increase the surface area of the storage electrode. Grain; HSG) process is used as an example to make the bottom electrode of the capacitor, and then sequentially form the dielectric layer between the plates of the capacitor and the top electrode to complete the production of the capacitor. Firstly, hemispherica 1 grains silicon (HSG-Si) 414 is formed as the bottom electrode of the capacitor, and then a dielectric film 4 1 6 is formed in order to form a dielectric layer between the plates of the capacitor. The conductive layer 418 of the top electrode of the capacitor is used to complete the fabrication of the capacitor. The manufacturing process of Figure 4A ~ Figure 4B is exactly the same as that of Figure 3A ~ Figure 3B, so the details will not be repeated. Referring to FIG. 4C, a conformal structure layer 419 is formed on the conductive layer 4 1 8. Among them, the conformal structure ′ layer 4 1 9 has better conformalness (c ο n f ο r in a 1), so its thickness can be formed more uniformly on the conductive layer 418. The better material of the conformal structural layer 4 1 9 can be selected to have a higher wet etching selective material than the conductive layer 4 1 8 (for example: APM (Ammonia peroxide mixture) method, in which APM (Ammonia peroxide mixture) It is an aqueous solution containing ammonia and hydrogen peroxide.) Selective materials, for example, the material of the conductive layer 4 1 8 is polycrystalline silicon, and the material of the conformal structure layer 4 1 9 can be LP-S i N or oxide and many more. As for the preferable thickness of the conformal structure layer 4 19, it is about 300-500 Angstroms, and the formation method thereof includes 1 ^ (^ 0.

Page 28 499731 V. Description of the invention (24) Then a non-con formal structure layer 4 2 0 is formed on the conformal structure layer 41 9, where the non-conformal structure layer 4 2 0 is conformal (c ο nf 〇rma 1) Poor, its outstanding characteristics and poor step coverage characteristics are similar to Plasma enhanced chemical vapor deposition 'PECVD films, so a top layer and a lower layer will be formed here Thick non-conformal structural layer 4 2 0. In addition, the material of the non-conformal structural layer 4 2 0 includes a polymer (ρ ο 1 ymer), and if the material of the non-conformal structural layer 4 2 0 is a polymer, a preferred embodiment of its formation is: In a conventional plasma etching chamber, a C4F8 of 6-8sccm, a CO of 360-480sccm, and a power of 400-800W are used to form a polymer layer having a thickness of about 100 0 _ 2 0 0 0 Angstroms. The formation rate is about 400-800 Angstroms per minute. Then remove a part of the non-conformal structure layer 4 2 0 to expose a part of the upper surface of the conformal structure layer 4 1 9. The method of removing a part of the non-conformal structure layer 4 2 0 can be similar to the method of removing organic BARC. method. Because of the non-guaranteed structure; 42 0 has poor step coverage characteristics, the thickness of the bottom and side walls of the non-conformal structure layer 42 0 formed here will be thinner than the top (about 25% -30% of the top thickness). ), After removing part of the non-conformal structure layer 420 'to expose part of the upper surface of the conformal structure layer 419, only a part of the top of the non-conformal structure layer 420 is consumed (about 35%) _50%). Then refer to Figure 4D,

With the remaining non-conformal structural layer 4 2 0 as the cover

499731 V. Description of the invention (25) The screen, removing part of the conformal structure layer 4 1 9 and part of the conductive layer 4 1 8 to form a self-aligned capacitor top electrode. It is worth noting here that the top electrode of the capacitor formed here has a hole (to form a bit line contact) that is self-aligned to the side wall of the capacitor. Moreover, with the self-alignment method described above, the lithography step of the conductive layer 3 1 8 will become a non-critical (c r i t i c a 1) step. Subsequently, the non-conformal structure layer 4 2 0 is removed using a conventional technique (for example, dilute hydrofluoric acid 100: 1 and SPM). Then, a part of the conductive layer 4 1 8 between the conformal structure layer 4 1 9 and the first dielectric layer 4 1 2 is selectively etched back, so that the conformal structure layer 4 1 9 and the first dielectric layer 4 1 2 Formation of voids. In this preferred embodiment, the method of selectively etching back a part of the conductive layer 1 2 2 is a wet etching method that can be APM (Ammonia peroxide mixture) (the solution used by APM households is 04011/11 20 2). . The etch-back rate of the conductive layer 418 is about 30-50 Angstroms per minute, and the temperature of the APM, the concentration of the problem 4011 and 11202, and the concentration of the polycrystalline doping in the conductive layer 418 are appropriately selected, and the conductive layer 4 1 The etching selection rate ratio of 8 to the conformal structure layer 4 1 9 may be greater than 10: 1. In this way, the distance between the subsequent bit line contact and the top electrode of the capacitor can be increased (that is, an additional alignment boundary between the bit line contact and the top electrode of the capacitor can be achieved). Please refer to FIG. 4E, and then use a technique such as dry #etching to remove a portion of the conformal structure layer 4 1 9 (that is, the protruding portion of the conformal structure layer 4 1 9) directly above the gap to increase 499731 between two adjacent conformal structural layers 4 1 9 V. Description of the invention (26)

distance. A second dielectric layer 4 2 2 is then deposited on the conformal structure layer 4 1 9 and the first dielectric layer 4 1 2. The part of the conformal structure layer 4 1 9 that is directly above the gap is intended to allow the second dielectric layer 4 2 2 to be filled to fill the void directly under the protruding portion of the conformal structure layer 4 1 9. The second dielectric layer 4 2 2 is used as an inner dielectric layer, and its material includes an oxide. Of course, if the part of the conformal structure layer 4 1 9 directly above the gap is not removed, an oxide layer with good conformalness (for example: LP-TEOS) can be directly used to fill the conformal structure layer 4 1 9 The void area directly below the protrusion (this replacement method is not shown). In this way, the top electrode of the self-aligned capacitor formed no longer has a protruding portion, so the size of the processing window for subsequent bit line contact can be increased, thereby avoiding some alignment errors during subsequent bit line contact formation. The resulting bit line contact is short-circuited with the top electrode of this capacitor. Subsequently, a part of the second dielectric layer 4 2 2 and a part of the first dielectric layer 4 1 2 are removed until the upper surface of the polycrystalline silicon plug 4 1 0 is exposed to form a bit line contact hole 4 2 3. Of course, before removing part of the second dielectric layer 4 2 2 and part of the first dielectric layer 4 12, the conformal structure layer 4 1 9 can also be selectively removed first (not shown).

Referring to FIG. 4F, a method such as sputtering is used to form a second conductive plug 4 2 4 as a conductive connection in the bit line contact hole 4 2 3. The second conductive plug 424 includes a W / TiN / T i composite layer composed of a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer. 499731 V. Description of the invention (27) In addition, combining the advantages of the above three embodiments, we can propose other embodiments to achieve the self-aligned top electrode in the dynamic random access memory cell of the bit line capacitor at the same time. And the purpose of forming a gap between the dynamic random access memory cell of the capacitor below the bit line and the bit line contact. Among other embodiments of the present invention, which have the advantages of the above three embodiments, the execution conditions of any of the process steps may be the same as those described in the above three embodiments. The only difference is that the above three embodiments are implemented. The process steps of the examples are rearranged and combined. Due to space, it is omitted here. The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be deemed to be the present invention. The protection of inventions Fan Shou.

Page 499731 Brief Description of Drawings Using the following description with the following drawings will make the contents and advantages of the present invention clearer. Among them: Figure 1A is a cross-sectional view of a semiconductor wafer, showing Steps of sequentially forming contact holes of transistors and crown-type capacitors on a semiconductor substrate; FIG. 1B is a cross-sectional view of a semiconductor wafer showing a step of forming a capacitor on a semiconductor substrate according to a conventional technique; FIG. 1C is a cross-sectional view of a semiconductor wafer Shows the step of forming a bit line contact hole on a semiconductor substrate according to the conventional technology; FIG. 1D is a cross-sectional view of a semiconductor wafer, showing the step of forming a conductive plug in the bit line contact hole according to the conventional technology as a step of conducting a connection Figure 2A is a cross-sectional view of a semiconductor wafer, showing the steps of sequentially forming contact holes of transistors and crown capacitors on a semiconductor substrate according to an embodiment of the present invention; Figure 2B is a cross-sectional view of a semiconductor wafer, showing According to an embodiment of the present invention, a step of forming a capacitor on a semiconductor substrate; FIG. 2C is a cross-sectional view of a semiconductor wafer, showing a step of forming a spacer structure on a sidewall of a crown-type capacitor, and then depositing an inner dielectric layer and etching back according to an embodiment of the present invention; FIG. 2D is a semiconductor wafer A cross-sectional view showing a step of removing the spacer structure to form a void at the position of the spacer structure according to an embodiment of the present invention; FIG. 2E is a cross-sectional view of a semiconductor wafer showing one of the present invention

Page 499731 The diagram briefly illustrates the steps of depositing an inner dielectric layer with poor void filling ability on the top electrode and the gap of the capacitor, and then forming a bit line contact hole by a lithographic etching method. FIG. 2F is a semiconductor wafer A cross-sectional view showing a step of forming a conductive plug in a bit line contact hole as a conductive connection according to an embodiment of the present invention; FIG. 3A is a cross-sectional view of a semiconductor wafer showing another embodiment of the present invention Steps of sequentially forming contact holes of transistors and crown-type capacitors on a semiconductor substrate; FIG. 3B is a cross-sectional view of a semiconductor wafer, showing a step of forming a capacitor on a semiconductor substrate according to another embodiment of the present invention; FIG. 3C is a cross-sectional view of a semiconductor wafer, showing that according to another embodiment of the present invention, a non-conformal structure layer is formed on a crown type capacitor, and then a part of the non-conformal structure layer is removed to expose a part of the conductive layer. K; FIG. 3D is a cross-sectional view of a semiconductor wafer, showing a residual non-conformal structure according to another embodiment of the present invention. For the mask, a part of the conductive layer is removed to form a self-aligned capacitor top electrode, and then the non-conformal structure layer is removed. FIG. 3E is a cross-sectional view of a semiconductor wafer, showing another embodiment according to the present invention. Steps of depositing an inner dielectric layer on a crown type capacitor, and then forming a bit line contact hole by using a p-lithography etching method; FIG. 3F is a cross-sectional view of a semiconductor wafer, showing the formation of a conductive plug according to another embodiment of the present invention In the bit line contact hole as a step of conducting the connection;

Page 499731 Brief Description of Drawings Figure 4A is a cross-sectional view of a semiconductor wafer, showing the steps of sequentially forming contact holes of transistors and crown-type capacitors on a semiconductor substrate according to another embodiment of the present invention; Figure 4B A cross-sectional view of a semiconductor wafer 'shows a step of forming a capacitor on a semiconductor substrate according to another embodiment of the present invention; FIG. 4C is a cross-sectional view of a semiconductor wafer, showing a sequential formation according to another embodiment of the present invention Conformal structure layer, non-conformal structure layer on the crown type capacitor, and then removing part of the non-conformal structure layer to expose part of the conformal structure layer; Figure 4D is a cross-sectional view of a semiconductor wafer, showing the basis In another embodiment of the present invention, the remaining non-conformal structure layer is used as a mask, and a part of the conformal structure layer and a part of the conductive layer are removed to form a self-aligned capacitor top electrode, and then the non-conformal structure layer is removed. And a step of selectively etching back a part of the conductive layer; FIG. 4E is a cross-sectional view of a semiconductor wafer, showing that according to another embodiment of the present invention, an inner dielectric layer is deposited in a crown type A step of forming a bit line contact hole on the container, and then using a lithographic etching method; FIG. 4F is a cross-sectional view of a semiconductor wafer, showing a conductive plug formed in the bit line contact hole according to another embodiment of the present invention; As a step of conductive wiring. Drawing number part: semiconductor substrate 100, 2 0 0, 3 0 0, 4 0 0; shallow trench isolation area 1 0 2, 2 0 2, 3 0 2, 4 0 2;

The 499731 diagram on page 35 briefly illustrates the transistor gate structure 1 0 4, 2 0 4, 3 0 4, 4 0 4; pole / source 1 0 6, 2 0 6, 3 0 6, 4 0 6; First inner polycrystalline dielectric layer 108; inner polycrystalline dielectric layers 208, 308, 408; polycrystalline stone plug (ρ ο 1 yp 1 ug) 11 0; first conductive plug 2 1 0, 3 10, 4 1 0; second inner polycrystalline dielectric layer 1 1 2; first dielectric layers 212, 312, 412; contact holes 1 1 3, 2 1 3, 3 1 3, 4 1 3; hemispherical Grain silicon layer 1 1 4, 2 1 4, 3 1 4, 4 1 4; Dielectric film 1 1 6, 2 1 6, 3 1 6, 4 1 6; Conductive layer 118, 218, 318, 418; Inner dielectric layer 1 2 0; bit line contact hole 1 2 1; conductive plug 12 2; spacer structure 2 1 9; second dielectric layer 2 2 0; void 2 2 4; third dielectric layer 226 Bit line contact hole 2 2 7; second conductive plug 2 2 8; non-conformal structural layer 3 1 9; second dielectric layer 3 2 0; bit line contact hole 3 2 1;

Page 499731 The diagram briefly illustrates the second conductive plug 3 2 4; conformal structural layer 4 1 9; non-conformal structural layer 4 2 0; second dielectric layer 4 2 2; bit line contact hole 4 2 3second conductive plug 4 2 4

Page 37

Claims (1)

499731 Sixth, the scope of the patent application and the memory of the ancient times ° The storage capacity of the storage device is in accordance with the state of the device. The offline element is located in the β 0 gap of the method of the conventional method. The dielectric layer 1 of Shi 5 is the first hole = ° • at the bottom of the upper hole, which is formed in the form of a half layer, an electric layer on the dielectric layer, and an electric layer. Filled and upper layer dielectrics remain in the silicon material forming Φ — its material material = ° part β, the upper layer dielectric of the mouth φ * σ is removed in place; the bottom of the upper pole meter section High-quality materials, silicon capacitors, capacitors, and capacitors are used as dielectric materials. The component shape is β-Li0; the capacitors on the upper side of the capacitor are electrically conductive. The layer-to-wall gap conductance forms a shaped structure; the interstitial space between the layer and the layer is exposed to electrical contact with the layer and the layer is exposed to the first layer. Back forming The upper-positioned structure wall gap is helium-δ. The structure wall; the gap space is the surface to remove the gap on the surface. The gap Lr fills the gap and fills the gap. Requires the use of dielectric material II. This is selected in the layered dielectric dielectric. The third and third layers are formed in the middle. The upper part of the part and the layered dielectric. Φ Partially removed layer dielectric 1 The first helium = 0 is formed in the same hole contact wiring element as the layer dielectric and the first middle Page 38 499731 VI. Scope of patent application The first conductive plug is formed in the bit line contact hole. 2. The method of claim 1 in the patent application scope, wherein before forming the first dielectric layer on the semiconductor substrate, the method further includes the following steps: forming a plurality of transistors on the semiconductor substrate; forming a fourth dielectric Layer on the plurality of transistors; and forming a second conductive plug in the fourth dielectric layer, wherein the hole corresponds to the second conductive plug. 3. The method according to item 1 of the scope of patent application, wherein the material of the first dielectric layer mentioned above comprises an oxide or a stone oxide formed with Tetraethyl-orthosilicate (TEOS). 4. The method according to item 1 of the patent application range, wherein the above-mentioned silicon material includes hemispherical grains ^ 7. 5. The method according to item 1 of the patent application range, wherein the capacitor dielectric layer includes one of the following: a nitride / oxide (N / 0) composite layer, an oxide / nitride / oxide composite layer ( 0 / N / 0), Ta 20 5, Ti02. 6. The method according to item 1 of the patent application range, wherein the material of the conductive layer comprises doped polysilicon. 7. The method according to item 1 of the scope of patent application, in which the above-mentioned spacer structure is 499731 6. The scope of patent application The material includes borophosphosilicate glass (BPSG) or silicon nitride. 8. The method according to item 1 of the scope of patent application, wherein the material of the second dielectric layer includes an oxide layer formed by using high density plasma (HDp), or an unformed layer formed in an OrTEOS gas environment. Replace with miscellaneous silica glass (USG). '乂 9. The method according to item 1 of the scope of patent application, wherein the method of etching back the second dielectric layer includes a dry method of engraving. Φ 1〇 · ^ The scope of patent application! The method according to the above item, wherein the method for removing the above-mentioned partition structure includes a wet worming method. 11. The method according to item 丨 of the scope of patent application, wherein t includes PE-TEOSC Plasma enhanced TEs) or Brother Heart L. Dian Yue 12 · If the method of the scope of patent application No. 10, where the material and the material of the partition structure are not mixed :: S ((η) two m broken glass (bpsg) Risi, Then, the final etching agent used in the dry etch-back method may include HF gas. 13 · As stated in the method of item 10 of the patent scope, wherein the material of the second dielectric layer and the material of the spacer structure are respectively undoped stone glass (USG) and low-pressure chemical vapor deposition ( Low Pressure Chemical Page 40 499731 VI. Patent application scope V a ρ 〇 r D e ρ s i t i ο η; L P C V D) When the nitride is formed, the etchant used in the dry etch-back method may include hot phosphoric acid. 14. A method for manufacturing a self-aligned top electrode in a dynamic random access memory cell with a capacitor under a bit line. The method includes at least the following steps: forming a first dielectric layer on a semiconductor substrate; Part of the first dielectric layer to form a hole in the first dielectric layer; forming a silicon material on the first dielectric layer and filling the hole; removing the first dielectric layer Part of the silicon material, the remaining part of which is used as the bottom electrode of the capacitor; forming a capacitor dielectric layer on the surface of the silicon material; forming a conductive layer to cover the capacitor dielectric layer; forming a non-protective layer A non-conformal structural layer is formed on the conductive layer; a part of the non-conformal structural layer is removed to expose a part of the upper surface of the conductive layer; and the remaining non-conformal structural layer is used as a mask, Removing part of the conductive layer to form a self-aligned capacitor top electrode; removing the non-conformal structure layer; forming a second dielectric layer on the conductive layer and the first dielectric layer; removing part of the second dielectric layer Dielectric layer and Parts of the first dielectric layer, to form bit line contact holes in the dielectric layer in the first and the second dielectric layer; and Page 41 499731 6. Scope of patent application The first conductive plug is formed in the bit line contact hole. 15. The method according to item 14 of the patent application scope, wherein before forming the first dielectric layer on the semiconductor substrate, the method further comprises the following steps: forming a plurality of transistors on the semiconductor substrate; forming a third A dielectric layer is on the plurality of transistors; and a second conductive plug is formed in the third dielectric layer, wherein the hole corresponds to the second conductive plug. The structure of the angle guarantee is described in the above 0 method \) y Sr θ of the my term 1 4 〇1—I p The c-closing object Fan Heli Ju specially included, please apply the quality as the material • The 6 1 layer 1 7. For example, the method of claim 14 in the patent application scope, wherein the method for removing the non-conformal structure layer described above includes a wet etching method. 1 8. The method according to item 16 of the scope of patent application, wherein the method for forming the non-conformal structure layer includes using 6-8sccm C4F8, 360-480sccm C0, and power of 4 0-8 0 0 W . 19. The method according to item 16 of the scope of patent application, wherein the method for removing a part of the conductive layer includes a plasma etching method. 20. The method according to item 17 of the scope of patent application, wherein the wet etching method includes using dilute hydrofluoric acid or SPM to achieve the same. Page 42 499731 VI. Application Patent Scope 2 1. —A method for manufacturing self-aligned top electrode in dynamic random access memory cells of bit-line capacitors, the method includes at least the following steps: forming the first dielectric An electrical layer is on a semiconductor substrate; a part of the first dielectric layer is etched to form a hole in the first dielectric layer; a silicon material is formed on the first dielectric layer and filled in the hole ; Removing a part of the silicon material on the first dielectric layer, the remaining part of the silicon material is used as the bottom electrode of the capacitor; forming a capacitor dielectric layer on the surface of the silicon material; forming a conductive layer to Covering the capacitor dielectric layer; forming a conformal structural layer on the conductive layer; forming a non-conformal (η ο η-c ο nf 〇rma 1) structural layer on the conformal β (conformal) structural layer Remove the part of the non-conformal structure layer to expose part of the upper surface of the conformal structure layer; use the remaining non-conformal structure layer as a cover, remove part of the conformal structure layer and part of the Conductive layer to form Self-aligned capacitor top electrode; remove the non-conformal structure layer; ^ selectively etch back part of the conductive layer between the conformal structure layer and the first dielectric layer, so that the conformal structure layer and the first A gap is formed between a dielectric layer; a portion of the conformal structure layer located directly above the gap is removed to enlarge Page 43 499731 6. The distance between two adjacent conformal structure layers in the scope of patent application; forming a second dielectric layer on the conformal structure layer and the first dielectric layer; excluding part of the second dielectric layer A dielectric layer and a portion of the first dielectric layer to form a bit line contact hole in the first dielectric layer and the second dielectric layer; and forming a first conductive plug in the bit line contact hole In. 2 2. The method according to item 21 of the patent application scope, wherein before forming the first dielectric layer on the semiconductor substrate, the method further includes the following steps: forming a plurality of transistors on the semiconductor substrate; ^ forming a first Three dielectric layers are on the plurality of transistors; and a second conductive plug is formed in the third dielectric layer, wherein the hole corresponds to the second conductive plug. 2 3. The method according to item 21 of the scope of patent application, wherein the material of the conformal structure layer can be selected from a material having a higher wet etching selectivity than the conductive layer. 2 4. The method according to item 21 of the scope of patent application, wherein the method for forming the conformal structure layer includes LPCVD. P 2 5. The method according to item 21 of the scope of patent application, wherein if the material of the conductive layer is polycrystalline silicon, the material of the conformal structure layer may include LP-SiN or an oxide. Page 44 499731 Sixth, the scope of the application for patent (Fanhe Lijuan special application method including the application of 6 2 layer 2 1 item, in which the above non-conformal structure polymer) 〇 2 7 · If you apply The method of claim 21, wherein the method for removing the non-conformal structure layer includes a wet etching method. i 28. The method according to item 21 of the scope of patent application, wherein the method for selectively etching back a part of the conductive layer includes a wet #etching method of APM (Ammonia peroxide mixture). 29. The method according to item 26 of the scope of patent application, wherein the method for forming the non-conformal structure layer includes using 6-8 sccm C4F8, 360-480sccc m C 0 and 4 0 0-8 0 0 W Power to form. 30. The method according to item 26 of the scope of patent application, wherein the method for removing a part of the conformal structure layer and a part of the conductive layer includes a plasma etching method. _ 3 1. The method according to item 27 of the scope of patent application, wherein the above wet I engraving method includes using dilute hydrofluoric acid or SPM to achieve. 3 2. —A method for manufacturing a self-aligned top electrode in a dynamic random access memory cell of a bit line capacitor, the method including at least the following steps: forming a first dielectric layer on a semiconductor substrate; Page 45 499731 VI. Patent application scope Etching part of the first dielectric layer to form holes in the first dielectric layer; forming silicon material on the first dielectric layer and filling the holes. ; Removing a part of the silicon material on the first dielectric layer, the remaining part of the silicon material is used as the bottom electrode of the capacitor; forming a capacitor dielectric layer on the surface of the silicon material; forming a conductive layer to Cover the capacitor dielectric layer; form a first conformal structure layer over the conductive layer; form a non-conformal structure layer over the first conformal structure layer; remove Part of the non-conformal structural layer to expose a portion of the upper surface of the first conformal structural layer; using the remaining non-conformal structural layer as a cover, removing part of the first conformal structural layer and part of the A conductive layer to form a self-aligned capacitor top electrode; remove the non-conformal structure layer; selectively etch back a portion of the conductive layer located between the first conformal structure layer and the first dielectric layer, so that the first Conformal structural layer A gap is formed between the first dielectric layer; a second conformal structure layer is formed on the first conformal structure layer and the first dielectric layer, and is filled in the first conformal structure layer and the first dielectric layer In the gap between the layers; Page 46 499731 6. The scope of the patent application removes part of the second conformal structure layer, part of the first conformal structure layer-and part of the first dielectric layer to form bit line contact holes in the first A dielectric layer, the first conformal structure layer and the second conformal structure layer; and a first conductive plug is formed in the bit line contact hole. 3 3. The method according to item 32 of the scope of patent application, wherein before forming the first dielectric layer on the semiconductor substrate, the method further comprises the following steps: forming a plurality of transistors on the semiconductor substrate; forming a second A dielectric layer is on the plurality of transistors; and a second conductive plug is formed in the second dielectric layer, wherein the hole pair 0 corresponds to the second conductive plug. 34. The method according to item 32 of the scope of patent application, wherein the material of the first conformal structure layer can be selected from the-material having a higher wet etching selectivity than the conductive layer. _ 35. The method according to item 32 of the scope of patent application, wherein the method for forming the first conformal structure layer includes LPCVD. 36. The method according to item 32 of the scope of patent application, wherein if the material of the conductive layer # is polycrystalline silicon, the material of the first conformal structure layer may include L P-Si N or oxide. 37. The method according to item 32 of the scope of patent application, wherein the above non-conformal structure Page 47 499731 VI. Scope of patent application The material of the layer includes polymer. 38. The method according to item 32 of the scope of patent application, wherein the method for removing the non-conformal structure layer includes a wet etching method. 39. The method according to item 32 of the scope of patent application, wherein the method for selectively etching back a part of the conductive layer includes wet etching of APM (Ammonia peroxide mi x t u r e). 40. The method according to item 32 of the scope of patent application, wherein the material of the second conformal structure layer includes LP-TEOS. 4 1. The method according to item 37 of the scope of patent application, wherein the method for forming the non-conformal structure layer includes using 6-8sccm C4F8, 360-480sccm C0, and power of 4 0-8 0 0 W . 4 2. The method according to item 37 of the scope of patent application, wherein the method for removing part of the first conformal structure layer and part of the conductive layer includes plasma etching. 43. The method according to item 38 of the scope of patent application, wherein the wet etching method includes using dilute hydrofluoric acid or SPM to achieve. 4 4. A method for manufacturing a self-aligned top electrode in a dynamic random access memory cell of a bit line capacitor, the method includes at least the following steps: Page 48 499731 6. The scope of the patent application forms a first dielectric layer on a semiconductor substrate; etching part of the first dielectric layer to form a hole in the first dielectric layer; forming a silicon material on the first Over the dielectric layer and filled in the hole; remove a part of the silicon material on the first dielectric layer, and the remaining part of the silicon material is used as the bottom electrode of the capacitor; forming a capacitor dielectric layer On the surface of the silicon material; forming a conductive layer to cover the capacitor dielectric layer; forming a non-conformal structure layer on the conductive layer; removing a part of the non-conformal structure layer to expose the portion Part of the upper surface of the conductive layer; using the remaining non-conformal structure layer as a mask, removing a part of the conductive layer to form a self-aligned capacitor top electrode; and removing the non-conformal structure layer. 4 5. The method according to item 44 of the scope of patent application, wherein after removing the non-conformal structural layer, the method further comprises the following steps: forming a second dielectric layer on the conductive layer and the first dielectric layer; removing Part of the second dielectric layer and part of the first dielectric layer to form bit line contact holes in the first dielectric layer and the second dielectric layer; and forming a first conductive plug in the The bit line touches the hole. Page 49 499731 VI. Scope of Patent Application 4 6 · The method according to item 45 of the scope of patent application, wherein the material of the non-conformal structure layer includes a polymer. 47. The method according to item 45 of the scope of patent application, wherein the method for removing the non-conformal structure layer comprises a wet I insect method. 48. The method according to item 46 of the scope of patent application, wherein the method for forming the non-conformal structure layer includes forming using 6-8sccm C4F8, 360-480sccm CO, and 400-800 W power. 4 9. A method for manufacturing a self-aligned top electrode in a dynamic random access memory cell of a capacitor under a bit line, the method includes at least the following steps: forming a first dielectric layer on a semiconductor substrate; etching a portion of the A first dielectric layer to form a hole in the first dielectric layer; forming a silicon material on the first dielectric layer and filling the hole; removing a portion on the first dielectric layer The silicon material, the remaining part of the material is used as the bottom electrode of the capacitor; Forming a capacitor dielectric layer on the surface of the silicon material; forming a conductive layer to cover the capacitor dielectric layer; forming a first conformal structural layer on the conductive layer; forming a non-conformal The structure layer is on the first conformal structure layer 499731 6. The patented conformal structure layer is removed; part of the non-conformal structure layer is removed to expose part of the upper surface of the first conformal structure layer; The non-conformal structure layer is a mask, removing part of the first conformal structure layer and part of the conductive layer to form a self-aligned capacitor top electrode; and removing the non-conformal structure layer. 5 〇. The method according to item 49 of the patent application scope, wherein after removing the non-conformal structure layer, the method further comprises the following steps: 4 Selectively etch back the layer between the first conformal structure layer and the first dielectric layer. Part of the conductive layer to form a gap between the first conformal structure layer and the first dielectric layer; removing a part of the first conformal structure layer directly above the gap to enlarge two adjacent ones The distance between the first conformal structure layers; forming a second dielectric layer on the first conformal structure layer and the first dielectric layer; removing part of the second dielectric layer and part of the first dielectric layer An electrical layer to form a bit line contact hole in the first dielectric layer and the second dielectric layer; and a first conductive plug to form a bit line contact hole. 51. The method according to item 49 of the scope of patent application, wherein after removing the non-conformal structure layer, the method further includes the following steps: selective etchback is located between the first conformal structure layer and the first dielectric layer (The enclosing object Fan Heli Ju specifically includes the application of quality and materials. • 4 5 layers 499731 6. Part of the patent application scope of the conductive layer, between the first conformal structure layer and the first dielectric layer Forming a gap; forming a second conformal structure layer on the first conformal structure layer and the first dielectric layer, and filling the gap between the first conformal structure layer and the first dielectric layer; Remove part of the second conformal structure layer, part of the first conformal structure layer and part of the first dielectric layer to form bit line contact holes in the first dielectric layer, the first conformal A structure layer and the second conformal structure layer; and forming a first conductive plug in the bit line contact hole. 5 2. The method according to item 49 of the patent application scope, wherein the first conformal structure is described above. The material of the layer may be selected to have a material with a higher degree of wet etching selectivity than the conductive layer. 5 3. If the method of the scope of patent application No. 49 is applied, if the material of the above conductive layer is polycrystalline, then the The material of a conformal structure layer may include LP-Si N or oxide. The method according to item 9 which The above non-conformal structure polymer). 55. The method according to item 49 of the scope of patent application, wherein the method for removing the non-conformal structure layer includes a wet etching method. Page 52 499731 VI. Scope of patent application Electric layer 5 6 · If the method of scope 50 of the patent application is applied, the above-mentioned material includes oxide. 57. The method of claim 50 or 51, wherein the method of selectively returning the last part of the conductive layer includes the wet lasting method of APM (Ammonia peroxide mixture). 58. The method according to item 51 of the scope of patent application, wherein the material of the second conformal structure layer comprises LP-TEOS. 59. The method according to item 54 of the scope of patent application, wherein the method for forming the non-conformal structure layer includes using 6-8sccra C4F8, 360-480sccm CO, and 400-800 W power. Page 53