TW480673B - Manufacturing method of DRAM having capacitor under bit line - Google Patents

Abstract

There is disclosed a manufacturing method of DRAM having capacitor under bit line (CUB), which comprises, first, forming a plurality of gate structures on a semiconductor substrate for use as word lines, and defining source/drain areas on the edge thereof; next, depositing a first dielectric layer on the gate structure, and forming a self-aligned conductive plug in the first dielectric layer for connecting the source/drain areas; next, depositing a second dielectric layer in the first dielectric layer and on the self-aligned conductive plug, and etching a second dielectric layer for simultaneously defining a bottom electrode and forming a bit line plug; then, sequentially forming a capacitor dielectric layer and a top electrode; and forming a sidewall spacer on the sidewall of the top electrode to preventing a short circuit with the bit line; subsequently, defining a metal pattern on the upper surface of the bit line plug, so as to define the bit line structure.

Description

480673

V. Description of the invention (1) Field of the invention: The present invention relates to a process of dynamic random access memory (MAM), and particularly to a dynamic and evil random with a capacitor (capacitor unhr bit line; CUB). Method for making memory access. Background of the Invention: With the advancement of the semiconductor industry, in the development and design of ultra-large integrated circuits (ULSI), in order to meet the design trend of high-density integrated circuits, the size of various components has been reduced to sub-micron. In addition, due to the shrinkage of components, there are often difficulties encountered in the related semiconductor manufacturing process, and the complexity of the process has also increased. For example, with the dynamic random access memory (DRAM) commonly found in integrated circuits, f memory cells (cells) often include the transistor and capacitor system, and by using the source of the capacitor and transistor The electrode / drain makes electrical contact, and the digital information is stored in the capacitor, and the transistor's digital data is stored in the capacitor by the transistor, bit line, and word line array. Therefore, when the size of the device is reduced to less than sub-micron, the size of the capacitor in the DRAM is also reduced, so the performance of the stored carrier is also relatively reduced. Therefore, to access the memory cells in the dynamic memory (DRAM) of the dynamic machine, the biggest problem is how to increase the capacitance when the component size tends to shrink and the product yield increases. Storage capacity and increased capacitance

48〇673 Description of the invention (2) Please refer to the first figure, which shows a DRAM memory cell with a bit-line capacitor manufactured according to the traditional process. The relevant process steps are described in: ^. First, a shallow trench insulator (STI) 12 is fabricated on a semiconductor substrate 10 to define an active area of a semiconductor device. Then, on this semiconductor substrate 10, a gate structure 14 for word lines and a source / drain region 16 therebetween can be determined. Then, a first oxide layer 18 can be deposited on the gate structure 14 and the semiconductor substrate 10, and the contact hole 1 is defined by the lithography process. Then, a polycrystalline silicon material is filled to form the polycrystalline silicon plug 20 in the figure. Next, a second oxide layer 22 can be deposited on the upper surface of the polycrystalline silicon plug 20 and the first chemical layer 18, and the opening of the bottom electrode is defined by a lithography process. In it. Then, a bottom electrode 24 having a surface of a hemispherical silicon crystal grain may be sequentially deposited on the surface of the opening pattern, and then a capacitor dielectric layer 26 may be deposited on the outer surfaces of the bottom electrode 24 and the second oxide layer 22. A conductive layer is then deposited on the surface of the capacitive dielectric layer 26 and filled in the opening pattern to form a structure in a figure. / Brother

Then, a photoresist layer 30 may be coated on the conductive layer 28 as a mask, and the conducting process of the conductive layer 28 may be performed to define the top electrode 32 'of each device as shown in the second figure. Next, a second oxide layer 34 is deposited on the top electrode 32 and the exposed second oxide layer 22 to form a photoresist layer 36 on the upper surface of the third oxide layer 34. A uses 2 photoresist ^

480673

As the last name mask, the third oxide layer 34 and the second oxide layer 22 are etched until they reach the upper surface of the polycrystalline silicon plug 20 located in the center, so as to form bit lines. The opening pattern 38 of the plug is shown in the third figure. Next, referring to the fourth figure, after the photoresist layer 36 is removed, the barrier layer 40 can be deposited on the sidewall and the bottom of the opening pattern 38 by a known process. ^ Deposition ^ The metal layer 42 is on the surface of the barrier layer 40, and is completely filled in the opening pattern 38: 丄 to form a bit line plug. Subsequently, an etching process can be performed on the barrier layer 40 and the metal layer on the dielectric layer 34 through a lithography process to define a desired pattern. Machine 4: 'It is worth noting that due to the continuous shrinking of the component dimensions, the allowable error value (PrOCeSS Wind0W) of Ϊ = has also been greatly reduced, and the process of defining patterns on semiconductor substrates has become more difficult. more difficult. Please refer to the figure ^ = ^, where due to misalignment error (mis_aHgnment), the lithography program of the fixed electrode = partial electrode is biased #, and the conductive layer 3 2: 4 is shifted to the right. And the 'top electrode of the left capacitor' will also extend to the right along the upper surface of the second oxide layer 22. And coating: Come, refer to the sixth figure, when the third oxide layer 34 is subsequently deposited, the tr layer 36 is on it, so that the opening pattern 38 ′ of the bit line plug opening top post ^ may be exposed. The ... electrode 32 of the left capacitor is shown as shown by arrow A in the figure. Once set

4S〇673

38 日 2 copies of the surface of the top electrode 32 will cause a short circuit between the bit line plug and the top electrode 32, which will cause component failure. In addition, referring to the color scheme, the deviation of the opening pattern from the opening pattern in the plug opening pattern to the opening in the photoresist layer 36 is not completed. For example, the trioxide layer 34 and the second opening pattern 38 are as shown by the arrow B in the opening made in FIG. The purpose of 1 is to provide and reduce the production surface of the opening pattern 38 once, resulting in post characteristics. Seven pictures', even in the case of defining a slight misalignment of the top electrode of the capacitor. However, in the subsequent production of the bit lithography process, an alignment error may also occur and it is shifted in the seventh figure. It is shown that the temple on the transfer mask has an alignment error, which causes the photoresist layer 36. When the photoresist layer 36 is used to perform the money engraving process on the second oxide layer 22, the defined eight figures are shifted to the left. In this way, J pattern 38 exposes the part of the capacitor. Fang Tong: Temple said that due to the manufactured bit line plugs, the electrical connection between the silicon plugs on the 2nd day was 20. Therefore, 浐 = will also cause the exposed polycrystalline silicon plug 20 and Becha polycrystalline silicon plug 20 to have poor electrical conductivity. The purpose and summary of the invention: " — > The purpose of the present invention is to provide a # ρ + process «With the contact hole of the line—the element of the pattern, the pattern of the electrode opening at the bottom of the electrode is made of a capacitor under the green. Another object of the present invention is to provide a connector that can be inserted in the element line.

Page 7 V. Description of the invention (5)-Method of wall aspect ratio. Lei: Another purpose of K j t j f is to provide a method that includes a wall spacer on the top electrode side wall to prevent it from forming a short circuit with the bit line. Take note 5 2: 1 A kind of dynamic random storage material with bit-line capacitors in the first -ΓΓ: First, a plurality of inter-, / i conductor substrates are formed to be used as word lines. Next, define the conductive substrate's domain in between pole junctions. The first dielectric layer is deposited on a half ρ. 'And covers the gate structure and the source / drain region. Then, a second inter-electrode structure is formed, and a part of the source / drain ^ ill is exposed. A finely formed 1-aligned conductive plug is formed in the first opening, and can be electrically connected to the source / drain region. The white electrical plug is connected to the second conductive plug, which is connected to the standard / electrical electrode, and the first conductive plug is used to deposit a second dielectric on the bottom of the capacitor. The electrical plug is used to connect to the bit.线 连接。 Line connection. Then, δ branches L in the above table and the second dielectric layer is etched until the first dielectric acoustic pattern is reached therein: =: f bottom electrode opening pattern, and contact with the bit line 丄 ^, Zn. _. The polar opening pattern will expose the first conductive plug surface, and the bit line will contact the hole diagram, and see the above, drag it on. Then, depositing the first if case will expose the top surface of the first conductive plug to form the bottom electrode, the surface of the pattern, and form the bit line 2. The conductive layer will actually fill the bit line contact hole electrical layer , And filled in the bottom 呷;. Then, a capacitor dielectric layer and a second conductive layer are sequentially formed to define each ΐϊΐ2 pole opening pattern. Then use the lithography process to make the top electrode of the valley, and form a sidewall spacer to cover the top electrode with V. Description of Invention (6). The redeposition metal layer is used as a bit line structure. As provided in the present invention, the method is to deposit the first dielectric ## 八 ^ lean embodiment, and more specifically, directly redeposit the first dielectric layer; Make a conductive plug in it, and define the bottom electrode = M at the same time. Then, in the same etching step pattern, in the second dielectric box. Second: the contact hole substrate with the bit line plug. The bottom electrode on the source / nonpolar region of the upper region is exposed in the μ and + domains, respectively, and the bottom electrodes of the semiconducting surface are exposed. Then, a bit line plug having a semi-spherical silicon crystal grain is formed. The contact surface is filled with a conductive pattern on the top surface of the contact hole pattern. The electrical bottom electrode is repeated as described above, and the third surface is deposited. Then, it is deposited on the side wall of the top electrode, and then is deposited on the side wall of the top electrode by lithography; ^ ^: on the surface of the wall and bit line plug. Constellation use. A metal pattern is defined as a bit line junction. Detailed description of the invention: State random access: = for the production of capacitors with bit lines, and at the same time, ^ element line = f is defined. Among them, by using the same lithography process substrate, the right six Λ contact hole and the bottom electrode opening pattern are misaligned with the semiconductor, so! ^, Stop the traditional manufacturing process due to two lithographic processes ^ 70-line plug and capacitor bottom electrode short circuit 480673

2. In addition, in the present invention, after the top of the capacitor is defined, a sidewall gap of an insulating material is formed on the side of the top electrode. This will ensure that the top electrode of the capacitor will not be short with the bit line. The detailed description of the present invention is as follows. Extremely. Please refer to the ninth figure for the road, first provide a semiconductor substrate to sink, = film layer. Among them, the semiconductor substrate 100 can be composed of a device < 100 > crystal orientation and crystal silicon. Generally speaking, other types of semiconductor materials, such as Gallium arsenide, germanium, or silicon substrates (silicoon, insolator, s〇I) on the edge layer. ) Can also be used as the semiconductor substrate 100 here. In addition, since the characteristics of the surface of the semiconductor substrate 100 do not cause a special shadow direction to the present invention, it is possible to select < 11〇 > or < 111 > depending on the crystal direction. ~ Next, a shallow trench insulator (STI) 102 can be fabricated on the semiconductor substrate 100 to define the active area for manufacturing the component. In addition, on the semiconductor substrate 100, a plurality of gate structures used as word lines (word 1 ines) and semiconductor substrates located on both sides of the gate structure 104 can be defined. Source / drain region 106. Next, a first dielectric layer 108 is formed on the semiconductor substrate 100 so as to cover the gate structure below. The lithography process is used to perform a money engraving process on the first dielectric layer 108 until it reaches the semiconductor substrate 100 to expose a part of the source / source region. The contact hole pattern is defined in the phase. Neighboring gate structure 104. In a preferred embodiment, the first dielectric here

480673 V. Description of the invention (8) The layer can be composed of oxides. “As far as I i is concerned, after the gate structure 104 is fabricated, a stop layer will be etched on the surface (not shown in the figure)” to As a result, the gate structure is completely covered. When the first dielectric layer 108 is etched, this etching stop will stop the gate structure i 〇4 to avoid erosion by the etchant. As for the material of the stop layer 'You can choose to use a silicon nitride material in order to take advantage of the higher etching selectivity ratio between the two materials' to effectively preserve the gate structure 104 in the etching sequence. Then, a conductive plug 110 and a conductive plug 110 can be formed. ηι in the first dielectric layer 108. Among them, a conductive layer can be deposited on the first dielectric layer 108 first, that is, in the above-mentioned contact hole, and then chemical mechanical polishing (CM will be used in the first-dielectric layer). Layer ... part of the conductive layer on the upper surface is removed, and becomes :: self-aligned conductive plugs 11 and Ul (self_al_-SAC) in the contact hole. Among them, the conductive plugs 110 on both sides are mainly Connect with the bottom electrode of capacitor H. As for the guide at the center = fill, then 疋 is used for subsequent production In the embodiment where the bit lines are connected, the conductive layer here may be made of polycrystalline silicon material. Yes, the conductive plug defined in this step is a polycrystalline silicon plug. Please refer to the tenth figure Then, a second dielectric layer 112 is deposited on the upper surfaces of the conductive interposers 110, 111 and the first dielectric layer 108. In general, the second dielectric layer m can be the same as the dielectric layer ⑽ of

480673 V. Description of the invention (9) 10%. That is, 'a silicon oxide material can be used to form a desired second dielectric layer.' Then, a photoresist layer 114 is coated on the upper surface of the second dielectric layer 112. Through the processes of exposure, development, and cleaning, the opening pattern 116 of the capacitor electrode and the contact hole pattern of the bit line plug are defined in the photoresist layer j14. Then, referring to the eleventh figure, the second dielectric layer 112 is sequentially etched using the photoresist layer 1-4 as an etching mask, until it reaches the upper surface of the first dielectric layer 108, and is formed to define The opening pattern 1 2 0 ′ of the bottom electrode and the contact hole pattern 12 2 for defining the bit line plug. Among them, the open pattern 120 exposes the upper surface of the conductive plug 11 10, and the contact hole pattern 1 22 Then the upper surface of the conductive plug lu will be exposed. "

Referring to the twelfth figure, after the photoresist layer 丨 4 is removed, a polycrystalline silicon film layer W4 can be deposited along the surfaces of the opening pattern 120 and the contact hole pattern 丨 2 2. In other words, a polycrystalline silicon film layer 124 is deposited on the surfaces of the conductive plug and m, the first dielectric layer 108, and the second dielectric layer 112. The radial width of the opening pattern 122 defined above is approximately twice that of the polycrystalline silicon film layer 124. When the polycrystalline silicon film layer 124 is deposited on the semiconductor substrate i ^) 〇e, the entire contact will be made. The hole pattern 122 is filled. In other words, after the polycrystalline silicon film layer 124 is deposited, polycrystalline silicon bit line plugs 1 2 7 are formed in the contact hole pattern 122. Next, a silicon seed (nuclei) can be formed on the polycrystalline silicon thin film 124

Page 12 480673 V. Description of the invention (10) Figure = 7 degree vacuum environment ^, the heat-tempering process is performed, and the main body is formed. Hei-SpheriCal Grain (HSG) 126 拗: Surface for use as the bottom electrode of a capacitor. In this way, there can be polvsn. Electric surface area. In addition, it is also possible to use the deposited rugged grinding process i ′ =: i and the polycrystalline silicon film 丨 24 to damage the hemispherical silicon crystal grains on the 26 surface. Next, U is the top surface of the second dielectric layer 112. The silicon film layer 1 2 4 and the hemisphere-shaped stone Xiyue] 9 main << 1 2. Xijing 128. On the preferred surface, a capacitor dielectric layer is formed. For example, the dielectric layer 128 can be formed by using PZT. One of the four films is Ta205, BST, and then a conductive layer can be deposited in the capacitor and filled in the opening pattern 120 as:]: f 128 on the surface, and M is used as a metaphor. -In general, Λ is the electrically-conductive doped electrode 掺 m where the conductive layer 13 is here. , A miscellaneous evening, said Shixi material ’to deposit 13. And coating photoresist II: Λ first media = shown in Figure 15. Here, the third dielectric layer 2 and 13 = the upper surface are formed as expected. Subsequently, the photoresist layer is used as: = the third dielectric cymbal under the fossil material and the conductive layer 130 are silver-etched to cover the process until: its I ^ Β page 13 480673 V. Description of the invention (11) Second Up to the upper surface of the dielectric layer 112, in order to define the shape of each capacitor «^ 136 〇 ^, the shape = 2 no, it will be invaded by the money slicing agent #, so it is slightly lower. Please refer to the sixteenth In the figure, after the photoresist layer 34 is removed, a silicon nitride layer 138 can be deposited on the third dielectric layer 132, the top electrode 136, and the second eighth, and the layer 11 2 and the bit line plug 1 2 7 surface. . And a non-isotropic etching process is performed on the silicon nitride layer 丨 3 8 ^, and a sidewall spacer structure 14 is formed on the sidewalls of the third dielectric layer 32 and the top 9 1-36, such as the tenth Seven pictures don't. It should be particularly noted that during the above-mentioned anisotropic etching process, the silicon nitride layer 138 on the bit line plug 127 is completely removed, and the bit line plug 127 is fully exposed. To avoid the occurrence of a disconnection in the bit line and the bit line plug 127 produced later. After one stack, a barrier layer including a titanium layer 142 and a titanium nitride layer 144 is formed on the third dielectric layer 132, the sidewall spacers 40, the second dielectric layer 112, and the bit line. Plug 127 surface. The barrier layer here is mainly used to prevent the subsequent formation of layers, which will cause a diffusion phenomenon with the dielectric layer or the semiconductor substrate, resulting in a spiking effect. In a preferred embodiment, when the barrier layer is manufactured, a sputtering process may be performed first to deposit a titanium layer 142 on the surface of each of the above layers. Then, in an environment of ~ or ^ 3, a desired titanium nitride layer 144 is formed on the surface of the titanium layer 42 through a high temperature treatment to prevent the oxidation of titanium sound 142 in the air. θ 480673 V. Description of the invention (12) Next, a metal layer 146 is further deposited on the surface of the titanium nitride layer 144, and 1 is filled in the opening 135. Then, a photoresist layer 148 is formed on the surface and surface of the metal layer 146, and a lithography process is performed until the third dielectric layer 32 is reached to remove a portion of the metal layer 146 and titanium. The layers 142 'and the titanium nitride layer 144' define the desired metal pattern. In this way, the nineteenth figure S can be formed with a bit-line capacitor (CUB) of the dynamic random access memory cell 0 to one Ik, and referring to the twentieth figure, this figure shows the example provided by the present invention. . Among them, more specifically, after the first dielectric layer 108 is deposited, the conductive plug 110 is not formed or is not formed thereon. Phase: After the electrical layer 108, a second dielectric layer 112 is deposited on the upper surface of the second J layer ~ 108. When #, a thicker dielectric layer is formed under the conditions of the process conditions, and it will not be replaced by the first dielectric layer 108 and the second dielectric layer. = 112. Then "refer to the above process" in the contact hole pattern of the second dielectric layer ι12 and the first dielectric layer, m 'in the · // dielectric layer 108 of the substrate F, and the semiconducting semiconductor material is exposed. On the source / drain region 106. As the surface of the upper body 104 is etched, the gate structure 104 is formed in advance. Μτ stop layer to avoid erosion in the coin-cutting process. After the pattern, the contact hole of the J: 5 ::: pattern and the bit line insert is made. The bottom electrode on the surface of the semi-finished silicon crystal 1 2 5 surface. Page 15 480673

On the surface of the two opening patterns. Same as above, because the "m contact hole pattern" has a smaller caliber. Therefore, when the silicon film layer is deposited, the entire contact hole is filled, and the element line plug 127. As for In the opening pattern of the bottom electrode, the bottom electrode 125 of the Y shape is formed along the second dielectric layer 112, the first dielectric layer 108, the gate structure 04, and the source / drain region 106. Surface deposition. &Amp; After forming the surface of the hemispherical silicon grains, the two adjacent gate structures and the holes between them will also be completely filled by the bottom electrode 25, similar to The structure of the conductive plug. ^ Next, after performing a chemical mechanical polishing process on a part of the bottom electrode 125 on the upper surface of the second dielectric layer 112, a capacitor dielectric layer 28 can be further deposited on the bottom 4 electrode 125 and the second A conductive layer is deposited on the upper surface of the dielectric layer 112, and a conductive layer is deposited on the upper surface of the dielectric layer 128. Then, the above-mentioned process is repeated, a second dielectric layer 132 is deposited on the conductive layer, and a lithography etching process is used. , Define the top electrode of the capacitor 1 3 6. Then make a sidewall spacer 丨 4 〇 on the third dielectric layer 13 2 and the top electrode 136, and a barrier layer including a titanium layer 14f and a nitride θ titanium layer 144 is deposited on the surfaces of the sidewall spacers 140, the second dielectric layer 12 and the bit line plug 127. And a metal layer 146 is deposited on the surface of the barrier layer. Then, a metal pattern can be defined on the third dielectric layer 132 by a lithography process to be used as a bit line structure. It is the same as the above. The bit line structure 150 can be electrically connected to the source / inverter region 106 by the bit line plug 127.

480673 V. Description of the invention (14) The method of the present invention has the advantages of Bai She Xi ^ ^ ^ ^ First of all, due to the opening pattern of the bottom electrode of Luyi and the poor setting, the contact hole diagram of the three-way plugs of Jiashan and Yiweifan plugs. The tea cups can be used in the same lithography process. ^ The table is made, so in the traditional process, due to the two lithography procedures (defining the bottom electrode opening and the alignment error, which leads to the bottom hole and the line contact hole of the subsequent production). The situation of short circuit will not occur in the This hair ruler is prepared in the method of μ 丄% month. In addition, since the method of the present invention can form a bit line plug on the same day in the step of forming the bottom electrode of the RJX and the power source, there can be a reduction in the number of charges. Process steps and reduce the complexity of the process. Yak's other large open element line is inserted in the production ratio, and it is clear from the capacitor gap wall element line that the electrical plug is not used in the twentieth. Because the invention is defined in the third dielectric layer 132, Mouth pattern. Therefore, unlike the conventional method, the plug contact hole in the present invention does not need to penetrate the third dielectric layer 132. Therefore, the contact hole of the: j plug can effectively reduce the aspect ratio &gt; and the difficulty of the manufacturing process. In addition, a sidewall of silicon nitride material is fabricated on the sidewall of the top electrode 136 of the third dielectric layer 32. The top electrode 136 can be effectively covered to avoid defects such as short circuit between the top electrode 136 and the structure 150. In addition, let alone the method provided by the present invention, in addition to being applicable to the bit-line capacitor manufacturing process with self-aligned conductance (refer to FIG. 19), it can also be self-aligned conductive Plug-in bit-line capacitor manufacturing process (refer to "Although the invention is illustrated above with a preferred example, it is not intended to limit

480673

Page 480673 Brief description of the diagrams Through the following detailed description combined with the attached diagrams, the above content and the many advantages of this invention can be easily understood, where the first picture is a half DRAM element capacitor and the second picture is The half-oxide layer in the capacitor is shown in the third picture as a half-bit line contact hole, the fourth picture is a half-bit line step; the fifth picture is the top electrode of the half-capacitor and the sixth picture is the half-bit line contact hole. When the half bit line contacts the hole, the eighth picture is when the half bit line contacts the hole. The ninth picture is half of the gate structure. The tenth picture is the half step. Relevant steps formed according to the traditional process; Cross-sectional view of the conductor substrate, showing the steps above which are formed according to the traditional process; Cross-sectional view of the conductor substrate, which shows the steps defined according to the traditional process; Cross-sectional view of the conductor substrate, which shows the formation of the conductor substrate according to the traditional process When cutting, the cutting of the conductor substrate may occur, the cutting of the conductor substrate may be exposed, the cutting of the conductor substrate may occur, and the cutting of the conductor substrate may be exposed. The bottom view of the semiconductor substrate on the bottom of the container shows the situation where the alignment error is defined according to the traditional process; the top view shows the situation where the top electrode of the capacitor is defined according to the traditional process; the side view shows the situation where the alignment error is defined according to the traditional process; The figure shows the situation where the top electrode of the capacitor is defined according to the traditional process; the side view shows the steps of making a bit plug according to the present invention; the side view shows the contact hole with the bit line at the same electrode opening according to the present invention; the sectional view shows According to the present invention

Page 19 480673 Schematic illustration 'Same 8 cars in steps $

#_ The bottom electrode of D capacitor has the main: a picture is a cross-sectional view of a semiconductor substrate, bit line contact holes; #; bottom electrode on the surface of the shape of a second crystal grain · ", shows the formation of a chemical mechanical conductor according to the present invention Sectional view of the substrate, showing ... "... Grinding the seed to remove part of the capacitor, and performing the fourteenth figure according to the present invention is a sectional view of the semiconductor substrate. The electrode is used to define the conductive layer of the top electrode. The fifteenth figure of the deposition of the present invention is a cross-sectional view of a semiconductor substrate, and the electrical layer is etched to define the top of each capacitor. The sixteenth figure of the guide according to the present invention is a cross-sectional view of a semiconductor substrate, showing the πf pole; ^ Nitriding The step of forming a layer on the side wall of the top electrode; not forming the display according to the present invention; defining the display according to the present invention; depositing the display according to the present invention; The figure shows the cross section of a semiconductor substrate. The metal layer is used as a bit line. The nineteenth figure shows the steps of the metal layer pattern in the cross section of the semiconductor substrate. The twentieth figure shows a semiconductor. Sectional view of the substrate, a display device having the DRAM bit line capacitor according to another embodiment of the present invention prepared in Example. Page 20

Claims (1)

480673 VI. Application for Patent Scope System: A kind of method of dynamic random access memory for A-line capacitors. The violation method includes at least the following steps: Use a plurality of interrogation structures on a semiconductor substrate to As a word line, the m-pole region is in the semiconductor substrate between the gate structures;-a structure: a K-lambda electrical layer on the semiconductor substrate ... covers the question &amp; structure and the source / drain Area; until one or two electrical layers' are reached until the free electrode structure adjacent to the surface of the semiconductor substrate is adjacent, the exposed portion of the electrode is ρ = 成! ^ = Quasi-conductive plug in the first opening to connect the Source / drain ^ f! The self-aligned conductive plug can be divided into a first conductive plug and a second conductive plug, and the first conductive plug is used to contact the bottom electrode of the capacitor and violate the second conductive plug. For connecting to the bit line, &quot; L build a first dielectric layer on the first dielectric layer and the self-aligned conductive plug; and etch the second dielectric layer until the first dielectric layer is reached The upper surface of the layer is a stack to form a bottom electrode opening pattern and a contact hole pattern with the bit line at 'In the electrical layer, the bottom electrode opening pattern will expose the upper surface of the first conductive plug' and the bit line contact hole pattern will expose the upper surface of the second conductive plug; A first conductive layer forms a bottom electrode on the surface of the bottom electrode opening pattern, and the first conductive layer fills the bit line contact hole T ′ to form a bit line plug; Sole 673, the scope of the patent application forms a capacitor dielectric layer on the bottom thunder electrode ^ ^ A surface of the second dielectric layer; the ⑼ electrode, the common line plug, and the second conductive layer deposited on the capacitor dielectric electrode In the opening pattern; s, and filled on the bottom to form a third dielectric layer on the second conductive layer; removing part of the third dielectric layer and the second lightning conducting layer to define the top of each capacitor #: 、 / 、 The capacitor is between the third dielectric layer and the second conductive sound, forming an opening ^ m ', and the exposed part is continued 箸-1 electrical layer and the bit line plug Surface; first forming a sidewall spacer on the side wall of the second opening, and a top electrode; and M covering the deposited metal layer on the third dielectric layer and filling in the first dielectric layer to Form a bit line structure. … X 苐 一口 2. As described in the method of the first patent application, 1 electric layer, the second dielectric acoustic toilet 人 —person eight described in the introduction. The electrical layer and the second dielectric layer are made of oxidized stone material. 3. As the method of the scope of the patent application, the method before the dielectric layer includes the formation of a stop layer; ; The engraving stop layer is composed of nitrogen = outer surface structure. The gate electrode below 480673 VI. Scope of patent application 4. For the method of the first scope of patent application, wherein the above self-aligned conductive plug is made of polycrystalline silicon material. 5. The method according to item 1 of the patent application range, wherein the bottom electrode mentioned above has a hemispherical silicon grain surface to increase the surface area of the capacitor. 6. The method according to item 1 of the patent application, wherein the above procedure for forming the first conductive layer includes at least the following steps: forming a polycrystalline silicon layer on the second dielectric layer, the first dielectric layer, and the first conductive plug On the surface of the plug and the second conductive plug, wherein the polycrystalline silicon layer is deposited along the surface of the bottom electrode opening pattern to form a film layer as a bottom electrode, and the polycrystalline silicon layer fills the bit line contact hole The bit line plug is formed; and a hemispherical silicon crystal grain is formed on the bottom electrode surface to increase the capacitance surface area. 7. The method according to item 1 of the patent application, wherein the second conductive layer is composed of doped polycrystalline silicon. 8. The method according to item 1 of the scope of patent application, wherein the above-mentioned sidewall spacers are made of a nitride nitride material. 9. For the method of applying for the first item of the patent scope, wherein the procedure for forming the above-mentioned side wall and partition wall further includes the following steps: Page 23 480673 6. Apply for a patent to deposit an insulating film layer on the surface of the third dielectric layer, the dielectric layer, and the bit line plug; and the σ electrode and the second undergo an anisotropic etching process to In addition to the part of the insulating film layer located on the upper surface of the bit line plug, the dielectric layer and the wall are on the sidewalls of the third dielectric layer and the top electrode, and the gap between the sidewalls is made by the method Dynamic random access memory for capacitors. The F-Jie method includes at least the following steps: forming a plurality of closed-pole structures on a semiconductor substrate to deposit electricity as a word line and Λ region Λ in the second gate, and the The L and polar regions are on the abundance conductor substrate and cover the interfacial structure. A second dielectric layer is deposited on the upper surface of the first dielectric layer; the body dielectric layer and the first dielectric layer ㉟, until reaching the second half of the semi-conductor ', the bottom electrode opening pattern is formed with Γϋ, and the bottom retort is in the first dielectric layer and the first dielectric layer, where ^ 卞 = 口 pattern is exposed It is located between two adjacent gate structures, and the exposure is also :::; source &quot; The upper surface of the electrode region, and the bit line contacting the hole pattern 荦 V exposes a part of the upper surface of the source / drain region. A conductive layer of tea is formed on the surface of the opening pattern of the bottom electrode, and At the same time, the first conductive layer will be filled in the bit line contact hole to form a bit line plug; a capacitive dielectric layer is formed on the bottom electrode, the bit line plug, and the bit line plug. 480673 6. The surface of the second dielectric layer in the scope of patent application; depositing a second conductive layer on the surface of the capacitor dielectric layer and filling the bottom electrode opening pattern;-forming a third dielectric layer on the second conductive layer ; The second dielectric layer, the second conductive layer, and the capacitor dielectric layer are engraved to define the top electrode of each capacitor and form openings in the third dielectric layer and the second conductive layer, and Exposing part of the upper surface of the second dielectric layer and the bit line plug; a forming a side wall gap on the side wall of the opening so as to cover the top electrode; and 'depositing a metal layer on the third dielectric Layer, and fill the opening to form a bit line structure. 11. The method as claimed in claim 10, wherein the upper dielectric layer, the second dielectric layer, and the third dielectric layer are formed. The electrical layer is made of rolled silicon material. If the method of item 10 of the patent application is applied, before the first dielectric layer, it further includes the steps of accumulating the square surface, LP, and A in the above surface, where The second etch stop layer: the second dielectric is etched on the surface of the interelectrode structure above. The second dielectric is made of silicon material to protect the closed electrode structure below. In the procedures of the electric layer and the first dielectric layer, the protection of the patent application scope No. 10 __ /, T bottom of the above page 25, patent application area area. The electrode has a hemispherical silicon grain surface to increase the capacitance. 14 · As in the method of applying for patent No. 10, the process of straight-conducting layer includes at least the following steps: forming polycrystalline silicon on the upper and middle surfaces. Layer in the second dielectric layer and the eight film contact holes to form a pole structure, the source and the surface of the pole region, where "the first polycrystalline 1 electric layer" should ask the bottom electrode opening The surface of the pattern is deposited, and the layer of the electrode is formed into a film of the F electrode at the bottom to increase the capacitance of the bit line; the layer will fill the area of the bit line; hemispherical The silicon crystal grains are on the surface of the polycrystalline silicon layer, and the chip breaking layer removes a part located on the surface of the second dielectric layer. As described in item 10 of the patent application scope, the electric layer is made of doped polycrystalline silicon. // 、 In the second guideline 16 above, if the method of item 10 in the scope of patent application, the Gantz gap wall is made of silicon nitride material.丨 〇 顼 The procedure of the wall of the wall, including the following steps The above-mentioned side-deposited insulating film layer is formed in 1 to perform a non-uniform ㈣ procedure on the third dielectric so as to be located on the surface of the 第 dielectric layer and the bit line plug: the top electrode of the layer, the second 480673 6. The patent application scope part of the upper surface of the bit line plug is the insulating film layer, and the sidewall spacer is defined on the third dielectric layer and the sidewall of the top electrode. Ii ·! Page 27