CN111742412B - 宽带隙半导体装置 - Google Patents

宽带隙半导体装置 Download PDF

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Publication number
CN111742412B
CN111742412B CN201880089875.XA CN201880089875A CN111742412B CN 111742412 B CN111742412 B CN 111742412B CN 201880089875 A CN201880089875 A CN 201880089875A CN 111742412 B CN111742412 B CN 111742412B
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region
pad
diode
semiconductor device
electrically connected
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CN111742412A (zh
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中村俊一
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Abstract

本发明涉及的宽带隙半导体装置，包括：第一MOSFET区域(M0)，具有第一栅电极10、以及设置在由第二导电型构成的第一阱区20的第一源极区域30；第二MOSFET区域(M1)，设置在栅极焊盘100的下方，具有第二栅电极110、以及设置在由第二导电型构成的第二阱区120的第二源极区域130；以及内置二极管区域，与第二栅电极110电气连接，其中，第二MOSFET区域(M1)的第二源极区域120与栅极焊盘100电气连接。

Description

宽带隙半导体装置
技术领域
本发明涉及一种宽带隙半导体装置，其具有：第一导电型的漂移层；由设置在漂移层上的第二导电型构成的阱区；以及设置在阱区的源极区域。
背景技术
以往，在SiC等宽带隙半导体中，MOSFET(金属-氧化物半导体场效应晶体管)已被普遍认知(国际公开公报2012/001837)。在这种SiC等宽带隙半导体中的MOSFET中，对其单元(Cell)部施加了保护，从而避免从漏极一侧向栅极绝缘膜施加的过剩电场。然而，这样的保护通常会导致降低Crss。虽然在硅元件中有时希望降低Crss，但在SiC等宽带隙半导体装置的情况下，即便是高耐压，其RonA(导通电阻)也很小。因此，一旦降低Crss就会出现高耐压低Crss的情况，从而导致在开关(Switching)时产生非常高的dV/dt。虽然高dV/dt有利于减少开关损耗，但一旦dV/dt过高的话，则会产生浪涌和噪声的产生，所以就有必要根据电路条件将其控制在合适的值。
基于上述情况，可以考虑为调整dV/dt而使用有源镜像电路(Active mirrorcircuit)或有源箝位电路(Active clamp circuit)，而这样就需要外置的MOSFET和二极管。在SiC等宽带隙半导体的情况下，虽然具有能够在高温中使用的有利之处，但当这样的外置MOSFET是由硅材料构成时，就无法在高温中使用了。
另外，由于SiC等宽带隙半导体的价格很高，因此一旦需要额外设置由SiC等宽带隙半导体构成的MOSFET，必然会导致制造成本的增加。
鉴于上述这些情况，本发明的目的是提供一种宽带隙半导体装置，其不但能够抑制制造成本上升，还能够对dV/dt进行调整。
发明内容
【概念1】
本发明涉及的宽带隙半导体装置，包括：
漂移层，采用第一导电型的宽带隙半导体材料；
源极焊盘；
第一MOSFET区域(M0)，设置在所述源极焊盘的下方，具有第一栅电极、以及设置在由第二导电型构成的第一阱区的第一源极区域；
栅极焊盘；
第二MOSFET区域(M1)，设置在所述栅极焊盘的下方，具有第二栅电极、以及设置在由第二导电型构成的第二阱区的第二源极区域；以及
内置二极管区域，与所述第二栅电极电气连接，
其中，所述第二MOSFET区域(M1)的所述第二源极区域与所述栅极焊盘电气连接。
【概念2】
在根据上述【概念1】所述的宽带隙半导体装置中，进一步包括：
第三MOSFET区域(M5)，具有与所述栅极焊盘电气连接的第三栅电极、以及设置在所述第二阱区的第三源极区域。
【概念3】
在根据上述【概念1】所述的宽带隙半导体装置中，
所述第三MOSFET区域(M5)为平面MOSFET，在所述第二阱区内设置有所述第三源极区域以及第三漏极区域。
【概念4】
在根据上述【概念1】至【概念3】中任意一项所述的宽带隙半导体装置中，
进一步包括与所述第二栅电极相连接的二极管用焊盘，
所述内置二极管区域通过所述二极管用焊盘与所述第二栅电极电气连接。
【概念5】
在根据上述【概念4】所述的宽带隙半导体装置中，
所述二极管用焊盘与所述栅极焊盘之间通过电阻部电气连接。
【概念6】
在根据上述【概念4】至【概念5】中任意一项所述的宽带隙半导体装置中，
所述内置二极管区域具有：设置在所述二极管用焊盘的下方并且由第二导电型构成的第三上方阱区、以及设置在所述第三上方阱区的下方并且由掺杂物浓度比所述第三上方阱区更高的第三下方阱区。
【概念7】
在根据上述【概念6】所述的宽带隙半导体装置中，
所述二极管用焊盘与所述第三上方阱区肖特基接触。
【概念8】
在根据上述【概念1】至【概念7】中任意一项所述的宽带隙半导体装置中，
在至少有一部分设置在所述栅极焊盘的下方的第一阱区内，设置有与所述源极焊盘以及所述栅极焊盘电气连接的第一保护二极管区域(D6)。
【概念9】
在根据上述【概念1】至【概念8】中任意一项所述的宽带隙半导体装置中，
进一步包括与所述第二栅电极相连接的二极管用焊盘，
在至少有一部分设置在所述二极管用焊盘的下方的第二阱区内，设置有与所述二极管用焊盘以及所述栅极焊盘电气连接的第二保护二极管区域(D7)。
【概念10】
在根据上述【概念1】至【概念9】中任意一项所述的宽带隙半导体装置中，
进一步包括与所述第二栅电极相连接的二极管用焊盘，
在至少有一部分设置在所述二极管用焊盘的下方的第一阱区内，设置有与所述二极管用焊盘以及所述源极焊盘电气连接的第二保护二极管区域(D7)。
【概念11】
在根据上述【概念1】至【概念10】中任意一项所述的宽带隙半导体装置中，
进一步包括与所述第二栅电极相连接的二极管用焊盘，
在至少有一部分设置在所述二极管用焊盘的下方的第二阱区内，设置有电阻区域，所述电阻区域具有与所述二极管用焊盘以及所述栅极焊盘电气连接的低浓度第一导电型区域。
【概念12】
在根据上述【概念1】至【概念11】中任意一项所述的宽带隙半导体装置中，
在所述栅极焊盘的下方设置有与所述第二栅电极电气连接的第一连接区域。
【概念13】
在根据上述【概念12】所述的宽带隙半导体装置中，
在所述第一连接区域的下方设置有与所述第一连接区域电气连接的内置二极管区域。
【概念14】
在根据上述【概念12】或【概念13】所述的宽带隙半导体装置中，
在位于所述栅极焊盘的下方的第二阱区内，设置有电阻区域，所述电阻区域具有与所述第一连接区域以及所述栅极焊盘电气连接的低浓度第一导电型区域。
【概念15】
在根据上述【概念12】至【概念14】中任意一项所述的宽带隙半导体装置中，
在面内方向上所述源极焊盘与所述栅极焊盘之间，设置有与所述第一连接区域以及所述第二栅电极电气连接的第二布线层，
所述内置二极管区域通过所述第二布线层以及所述第一连接区域与所述第二栅电极电气连接，
在至少有一部分设置在所述第二布线层的下方的第一阱区内，设置有与所述第二布线层以及所述源极焊盘电气连接的第二保护二极管区域(D7)。
发明效果
在本发明中，当采用在栅极焊盘的下方设置第二MOSFET区域(M1)，并且设置与该第二MOSFET区域(M1)的第二栅电极电气连接的二极管区域(D2b+D4)的形态的情况下，就能够提供不但能够抑制制造成本上升，而且还能够对dV/dt进行调整的宽带隙半导体装置。
附图说明
图1是可在本发明第一实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图11以及图12中假想线a1处的截面。
图2是用于说明图1所示的截面处的层功能的图。
图3是可在本发明第一实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图11以及图12中假想线b1处的截面。
图4是用于说明图3所示的截面处的层功能的图。
图5是可在本发明第一实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图11以及图14中假想线c1处的截面。
图6是用于说明图5所示的截面处的层功能的图。
图7是可在本发明第一实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图11以及图14中假想线d1处的截面。
图8是用于说明图7所示的截面处的层功能的图。
图9是可在本发明第一实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图11、图12以及图14中假想线e1处的截面。
图10是用于说明图9所示的截面处的层功能的图。
图11是可在本发明第一实施方式中使用的碳化硅半导体装置的概略平面图。
图12是可在本发明第一实施方式中使用的碳化硅半导体装置的另一个形态的概略平面图。
图13是可在本发明第一实施方式中使用的碳化硅半导体装置的另一个形态的概略平面图。
图14是可在本发明第一实施方式中使用的碳化硅半导体装置的另一个形态的概略平面图，图中展示的是与图12以及图13不同的部位。
图15是可在本发明第一实施方式中使用的碳化硅半导体装置的电路图。
图16是可在本发明第二实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图20中假想线a2处的截面。
图17是用于说明图16所示的截面处的层功能的图。
图18是可在本发明第二实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图21中假想线c2处的截面。
图19是用于说明图18所示的截面处的层功能的图。
图20是可在本发明第二实施方式中使用的碳化硅半导体装置的另一个形态的平面图。
图21是可在本发明第二实施方式中使用的碳化硅半导体装置的另一个形态的平面图，图中展示的是与图20不同的部位。
图22是可在本发明第二实施方式中使用的碳化硅半导体装置的电路图。
图23是可在本发明第三实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图26中假想线f3处的截面。
图24是用于说明图23所示的截面处的层功能的图。
图25是可在本发明第三实施方式中使用的碳化硅半导体装置的概略平面图。
图26是可在本发明第三实施方式中使用的碳化硅半导体装置的另一个形态的概略平面图。
图27是可在本发明第三实施方式中使用的碳化硅半导体装置的电路图。
图28是可在本发明第三实施方式中使用的碳化硅半导体装置的截面图，图中展示的是不同于图25中所示的形态下的图26中假想线f3处的截面，
图29是用于说明图28所示的截面处的层功能的图。
图30是可在本发明第四实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图39中假想线c4处的截面。
图31是用于说明图30所示的截面处的层功能的图。
图32是可在本发明第四实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图39中假想线d4处的截面。
图33是用于说明图32所示的截面处的层功能的图。
图34是可在本发明第四实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图39中假想线g4处的截面。
图35是用于说明图34所示的截面处的层功能的图。
图36是可在本发明第四实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图39中假想线e4处的截面。
图37是用于说明图36所示的截面处的层功能的图。
图38是可在本发明第四实施方式中使用的碳化硅半导体装置的概略平面图。
图39是可在本发明第四实施方式中使用的碳化硅半导体装置的另一个形态的概略平面图。
图40是可在本发明第四实施方式中使用的碳化硅半导体装置的电路图。
图41是可在本发明第五实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图52中假想线c5处的截面。
图42是用于说明图41所示的截面处的层功能的图。
图43是可在本发明第五实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图52中假想线d5处的截面。
图44是用于说明图43所示的截面处的层功能的图。
图45是可在本发明第五实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图52中假想线g5处的截面。
图46是用于说明图45所示的截面处的层功能的图。
图47是可在本发明第五实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图41以及图52中假想线h5a处的截面。
图48是用于说明图47所示的截面处的层功能的图。
图49是可在本发明第五实施方式中使用的碳化硅半导体装置的截面图，图中展示的是图41以及图52中假想线h5b处的截面。
图50是用于说明图49所示的截面处的层功能的图。
图51是可在本发明第五实施方式中使用的碳化硅半导体装置的概略平面图。
图52是可在本发明第五实施方式中使用的碳化硅半导体装置的另一个形态的平面图。
具体实施方式
第一实施方式
在本实施方式中，使用纵型MOSFET来作为一例进行说明。在本实施方式中，虽然是将第一导电型作为n型、将第二导电型作为p型来进行说明的，但是不限于这种形态，也可以将第一导电型作为p型、将第二导电型作为n型。此外，在本实施方式中，虽然是使用碳化硅作为宽带隙半导体来进行说明的，但是也不限于这种形态，也可以使用氮化镓等来作为宽带隙半导体。在本实施方式中，将在图1中作为厚度方向的上下方向显示为第一方向。将与图1的厚度方向(第一方向)正交的方向称为“面内方向”。即，包含有图1的左右方向(第二方向)以及纸面的法线方向的面是“面内方向”。
如图1所示，本实施方式的碳化硅半导体装置，具有：n型碳化硅半导体基板11、设置在碳化硅半导体基板11的第一主面(上端面)上的，并且是使用了n型碳化硅材料的漂移层12、由设置在漂移层12上的p型构成的多个阱区20、以及设置在阱区20的n型源极区域30。阱区20例如可以通过对漂移层12注入p型掺杂物来形成，源极区域30例如可以通过对阱区20注入n型掺杂物来形成。在碳化硅半导体基板11的第二主面(下端面)上设置有漏电极19。被作为单元来使用的区域的周缘外方设置有耐压构造部。例如，可以使用钛、铝、镍等来作为漏电极90。本实施方式的漂移层12中的掺杂物浓度是例如1×1014～4×1016cm－3，碳化硅半导体基板11中的掺杂物浓度是例如1×1018～3×1019cm－3。
如图1以及图2所示，碳化硅半导体装置，具有：源极焊盘1、以及第一MOSFET区域(M0)，设置在源极焊盘1的下方，具有由多晶硅等构成的第一栅电极10、以及设置在由第二导电型构成的第一阱区20的第一源极区域30。第一栅电极10的上端面以及侧面被层间绝缘膜65环绕，并且第一栅电极10的下端面设置有由栅极氧化膜等构成的第一绝缘膜60(参照图11以及图12的假想线a1)。
在第一源极区域30中，与源极焊盘1相连接的部位是超高浓度n型区域(n++)32，并且高浓度n型区域(n+)31与超高浓度n型区域32相邻设置。超高浓度p型半导体区域(p++)21与超高浓度n型区域32相邻设置。超高浓度n型区域32以及超高浓度p型半导体区域21通过金属层40，与源极焊盘1相连接。第一阱区20与层间绝缘膜65之间设置有第一绝缘膜60。
碳化硅半导体装置，具有：栅极焊盘100、以及第二MOSFET区域(M1)，设置在栅极焊盘100的下方，具有由多晶硅等构成的第二栅电极110、以及设置在由第二导电型构成的第二阱区120的第二源极区域130。第二栅电极110的上端面以及侧面被层间绝缘膜65环绕，并且第二栅电极110的下端面设置有由栅极氧化膜等构成的第一绝缘膜60。
第二源极区域130，具有：其一部分是位于第二栅电极110的下方的高浓度n型区域(n+)131、以及与高浓度n型区域131相邻的超高浓度n型区域(n++)132。在第二阱区120中，与超高浓度n型区域132相邻的区域是低浓度p型区域(p-)122,并且高浓度n型区域131与漂移层12之间的区域是高浓度p型区域(p+)121。超高浓度n型区域(n++)以及低浓度p型区域(p-)通过金属层40，与栅极焊盘100相连接。栅极焊盘100下方的金属层40与第二阱区120的低浓度p型区域(p-)肖特基接触。
通过在面内方向的第一源极区域30与第二源极区域130之间设置由n型区域(n)构成的第一分离区域80，从而来分割阱区，进而形成所述的第一阱区20与第二阱区120。
如图3以及图4所示，在不同于第一MOSFET区域(M0)所存在的部位中(参照图11以及图12的假想线b1)，栅极焊盘100与第一栅电极10相连接，从而形成栅极连接区域。通过使第一栅电极10与栅极焊盘100经由设置在层间绝缘膜65上的栅极接触孔来接触，从而形成栅极连接区域。
如图5以及图6所示，面内方向的栅极焊盘100与源极焊盘1之间，设置有第一内置二极管区域(D2b+D4)(参照图11以及图14的假想线c1)。该第一内置二极管区域(D2b+D4)通过由铝等构成的二极管用焊盘200以及外置的电阻部400(参照图11)，与栅极焊盘100相连接。
第一内置二极管区域(D2b+D4)具有第三阱区210。第三阱区210具有：设置在二极管用焊盘200的下方并且由p型构成的第三上方阱区211、以及设置在第三上方阱区211的下方并且由掺杂物浓度比第三上方阱区211更高的第三下方阱区215。第三上方阱区211与二极管用焊盘200通过金属层40来相连接。第三下方阱区215在第三上方阱区211的下方被设置为条纹状。
如图5以及图6所示，第三下方阱区215构成为使其环绕第三上方阱区211的周缘。通过在面内方向的第三下方阱区215与第二阱区120之间设置由n型区域(n)构成的第二分离区域85，从而来将这些分割。如图7以及图8所示，第二栅电极110与二极管用焊盘200相连接。
第三上方阱区211由低浓度p型区域(p-)构成，并且连接于二极管用焊盘200的金属层40与第三上方阱区211肖特基接触。第三下方阱区215由p型区域(p)构成。
如图9以及图10所示，在面内方向的栅极焊盘100的周缘部中设置有第三MOSFET区域(M5)(参照图11、图12以及图14的假想线e1)。第三MOSFET区域(M5)，具有：与栅极焊盘100电气连接的第三栅电极510、以及设置在第二阱区120的第三源极区域。第三MOSFET区域(M5)是平面MOSFET，并且在第二阱区120内设置有第三源极区域以及第三漏极区域。
具体为设置有：其一部分是位于第三栅电极510的下方的一对高浓度n型区域(n+)531、以及与高浓度n型区域531相邻的一对超高浓度n型区域(n++)532。第二阱区120中的一对高浓度n型区域531之间设置有高浓度p型区域(p+)521。并且，通过一侧(图9以及图10中的右侧)的高浓度n型区域531以及超高浓度n型区域532来构成第三源极区域，通过另一侧(图9以及图10中的左侧)的高浓度n型区域531以及超高浓度n型区域532来构成第三漏极区域。在图9以及图10所示的方式中，第三栅电极510与第三源极区域通过栅极焊盘100相连接。
在第二阱区120中，超高浓度p型区域(p++)522与第二MOSFET区域(M1)侧的超高浓度n型区域532相邻设置。超高浓度n型区域(n++)以及超高浓度p型区域(p++)通过金属层40，连接于由铝等构成的第一布线层580。该第一布线层580不与超高浓度n型区域(n++)以及超高浓度p型区域(p++)以外的任何区域相连接。通过设置该第一布线层580，就能够使超高浓度n型区域(n++)与超高浓度p型区域(p++)短路。
第一栅电极10、第二栅电极110、第三栅电极510等栅电极例如可以通过多晶硅等来形成，也可以使用CVD法、光刻技术等来形成。层间绝缘膜65例如可以通过二氧化硅来形成，也可以通过CVD法等来形成。
设置的金属层40由镍、钛或者由含有镍或钛的合金构成。
如图11所示，源极焊盘1的周缘外方设置有保护环等耐压构造90，从而使其环绕源极焊盘1的整体。
第一MOSFET区域(M0)的单元可以如图12所示般在面内方向大致呈矩形(squarecell),也可以如图13所示般呈条纹形(stripe cell)。第二MOSFET区域(M1)可以如图12以及图13所示般在面内方向大致呈矩形,也可以不限于此，呈条纹形。当第二MOSFET区域(M1)在面内方向是大致呈矩形时，为了防止第二阱区120的电位浮动，第二阱区120如图3以及图4所示般连接在第二MOSFET区域(M1)的下方。
在本实施方式中，超高浓度n型区域(n++)的掺杂物浓度是例如2×1019～1×1021cm－3，高浓度n型区域(n+)的掺杂物浓度是例如1×1018～2×1019cm－3，n型区域(n)的掺杂物浓度是例如4×1016～1×1018cm－3，后述的低浓度n型区域(n-)的掺杂物浓度是例如1×1014～4×1016cm－3。超高浓度p型半导体区域(p++)的掺杂物浓度是例如2×1019～1×1021cm－3,高浓度p型区域(p+)的掺杂物浓度是例如3×1017～1×1019cm－3，p型区域(p)的掺杂物浓度是例如1×1017～5×1018cm－3，是比高浓度p型区域(p+)的掺杂物浓度更低的值，低浓度p型区域(p-)的掺杂物浓度是例如1×1016～1×1017cm－3。
在本实施方式中，当采用在栅极焊盘100的下方设置第二MOSFET区域(M1)，并且设置与第二MOSFET区域(M1)的第二栅电极110电气连接的第一内置二极管区域(D2b+D4)的形态时，由于无需额外设置由SiC等宽带隙半导体构成的MOSFET，因此不但能够抑制制造成本上升，还能够对dV/dt进行调整。
根据本实施方式，就能够成为图15所示的电路结构，并且还能够设为是使用第一MOSFET区域(M0)与第二MOSFET区域(M1)的镜像电路。
其中，在图15中用虚线包围的部分成为各个阱区。一旦第二MOSFET区域(M1)的第二阱区120成为负偏置(bias)，第二MOSFET区域虽然会有成为常导通状态(Normal on)的可能性，但是通过设置图15所示的具有第二阱区120的第三MOSFET区域(M5)，就能够在第二MOSFET区域因基板偏置效果而成为常导通状态之前，使第三MOSFET区域(M5)成为导通状态，从而返回零偏置。
第二实施方式
下面，对本发明的第二实施方式进行说明。
在本实施方式中，在面内方向的源极焊盘1的下方的第一MOSFET区域(M0)与栅极焊盘100的下方的第二MOSFET区域(M1)之间，如图16以及图17所示，设置有设置在第一阱区20的第一保护二极管区域(D6)(参照图20的假想线a2)。此外，在面内方向的二极管用焊盘200的下方的第一内置二极管区域(D2b+D4)与栅极焊盘100的下方的第二MOSFET区域(M1)之间，设置有设置在第二阱区120的第二保护二极管区域(D7)(参照图21的假想线C2)。其他方面则与第一实施方式相同，在第一实施方式中采用过的所有构成都能够采用在第二实施方式中。对于在第一实施方式中说明过的构件则添加相同符号来进行说明。其中，图20的假想线b2、图21的假想线d2以及假想线e2的截面，能够各自采用与第一实施方式中的假想线b1、假想线d1以及假想线e1的截面相同的形态。
如图16以及图17所示，第一保护二极管区域(D6)在面内方向与第一源极区域30的超高浓度n型半导体区域(n++)32相邻设置。第一保护二极管区域(D6)，具有：超高浓度p型半导体区域(p++)613、以及在面内方向与超高浓度p型半导体区域(p++)相邻设置的高浓度n型半导体区域(n+)611。超高浓度n型半导体区域(n++)612在面内方向与高浓度n型半导体区域611相邻设置。超高浓度n型半导体区域(n++)通过金属层40，与第一栅极焊盘100相连接。
在第一保护二极管区域(D6)的超高浓度p型半导体区域613与高浓度n型半导体区域611的接合面的上方，也可以不设置焊盘等金属构件。通过采用这种方式，就能够期待提高耐热性。
如图18以及图19所示，第二保护二极管区域(D7)在面内方向通过低浓度p型半导体区域(p-)122，与第二源极区域130的超高浓度n型半导体区域(n++)132相邻设置。第二保护二极管区域(D7)，具有：超高浓度p型半导体区域(p++)621、以及与超高浓度p型半导体区域621相邻设置的高浓度n型半导体区域(n+)623。超高浓度n型半导体区域(n++)624与高浓度n型半导体区域623相邻设置。超高浓度n型半导体区域624通过金属层40，与二极管用焊盘200相连接。
第二保护二极管区域(D7)的超高浓度p型半导体区域621与高浓度n型半导体区域623的接合面的上方，也可以不设置焊盘等金属构件。通过采用这种方式，就能够期待提高耐热性。
此外，图18所示的第二保护二极管区域(D7)的超高浓度p型半导体区域621构成为不与栅极焊盘100相接触。
在第二保护二极管区域(D7)中，通过与第二保护二极管区域(D7)的超高浓度p型半导体区域621相邻的低浓度p型半导体区域122，从而流通雪崩电流。
虽然是通过加宽如图18以及图19所示的第一内置二极管区域(D2b+D4)的第三下方阱区215的间隔来降低耐压，但是由于较大的雪崩能量流通于第一内置二极管区域(D2b+D4)以及电阻部400(R3)中，从而对于该半导体装置的栅极驱动电路来说会有过电流或过电压的可能性，因此就有益于防止出现这些问题。此外，由于同样的理由，虽然对于第一MOSFET区域(M0)的栅极也会有过电压的可能性，但是也有益于防止该过电压。关于这一点，在本实施方式中，由于设置有第一保护二极管区域(D6)，从而就能够防止第一MOSFET区域(M0)的栅电极中的过电压等。
此外，根据在图22作为R3来显示的电阻部400的值、以及第二MOSFET区域(M1)的栅极输入容量Ciss与第一内置二极管区域(D2b+D4)的第三下方阱区215的接合容量Cj的比例，最好对第二MOSFET区域(M1)的栅极也施加保护。对于这一点，通过设置本实施方式的第二保护二极管区域(D7)，就能够保护第二MOSFET区域(M1)的栅极。其中，在图22中虽然展示了第二保护二极管区域(D7)是设置在第二阱区120的方式，但是第二保护二极管区域(D7)也可以设置在第一阱区20，并将阳极作为源极电位。
第三实施方式
下面，对本发明的第三实施方式进行说明。
在上述各实施方式中设置了电阻部400。在本实施方式中，代替电阻部400或在电阻部400之外，在面内方向，在第一内置二极管区域(D2b+D4)与第一MOSFET区域(M0)之间设置有第一内部电阻区域(R3a)(参照图25以及图26的假想线f3)。在本实施方式中，能够采用上述各实施方式中采用过的所有结构。对于在上述各实施方式中说明过的构件将添加相同符号来进行说明。其中，图25的假想线a3、假想线b3、假想线c3、假想线d3以及假想线e3的截面，能够各自采用与第一实施方式中的假想线a1、假想线b1、假想线c1、假想线d1以及假想线e1的截面，或者第二实施方式中的假想线a2、假想线b2、假想线c2、假想线d2以及假想线e2的截面相同的形态。
如图23所示，第一内部电阻区域(R3a)具有设置在第二阱区120内的低浓度n型区域(n-)655。超高浓度n型区域(n++)656在面内方向与低浓度n型区域655相邻设置，并且通过金属层40，与二极管用焊盘200相连接。此外，在相对于低浓度n型区域655与超高浓度n型区域656的面内方向是相反的方向上设置有n型区域(n)653。高浓度n型区域(n+)652在面内方向与n型区域653相邻设置，超高浓度n型区域(n++)651在面内方向与高浓度n型区域652相邻设置，并且通过金属层40，与栅极焊盘100相连接。
在n型区域653的上方通过第一绝缘膜60设置有第四栅电极660。第四栅电极660的上方设置有栅极焊盘100，并且第四栅电极660与栅极焊盘100相连接。n型区域653的厚度比超高浓度n型区域656、低浓度n型区域655、高浓度n型区域652以及超高浓度n型区域651的厚度更薄。
第一内部电阻区域(R3a)的电阻事实上是通过作为平面MOSFET(M3)的LDD(Lightly Doped Drain)的低浓度n型区域655来实现的。也就是，将电阻的大小通过低浓度n型区域655的长度来进行调整，并且低浓度n型区域655在图23中的长度比超高浓度n型区域656、低浓度n型区域655、高浓度n型区域652以及超高浓度n型区域651的长度更长。
在图23以及图24所示的方式中，形成有常导通状态的平面MOSFET(M3)，并且第四栅电极660与作为源极区域的超高浓度n型区域651被栅极焊盘100短路。
当如图11所示方式般外置电阻部400时，就能起到在温度上升的同时电阻也会随之升高，并且降低dV/dt的作用。这时，开关损耗会进一步增加从而进一步导致温度上升。此外，通过如本实施方式般设置第一内部电阻区域(R3a)与平面MOSFET(M3)，就能够提高温度特性。特别是在使用碳化硅来作为材料时由于其界面特性不好，因其影响，MOS沟道的电阻值具有较强的负温度特性，因此相比外置电阻部400时对于温度特性的改善是有益的。其中，虽然图27是本实施方式中的电路图，但是也展示了第一内部电阻区域(R3a)中的寄生容量C3。
如图28以及图29所示，也可以设置低浓度n型区域657来代替超高浓度n型区域656。该低浓度n型区域657和低浓度n型区域655可以是具有相同浓度的相同区域，也可以是具有不同浓度的区域。在设置有低浓度n型区域657时，低浓度n型区域657与二极管用焊盘200通过金属层40来肖特基接触，在这时无需将第一内置二极管区域(D2b+D4)的D2b设置在D4上。因此，如图28以及图29所示，第三上方阱区211是由与第三下方阱区215相同的平面形状构成，并且二极管用焊盘200与漂移层12肖特基接触。在这时，第三上方阱区211的浓度可以与第三下方阱区215相同，或者也可以是更高的高浓度。其中，在图28以及图29所示的方式中，第一内置二极管区域(D2b+D4)的D2b形成在二极管用焊盘200与低浓度n型区域657之间。
第四实施方式
下面，对本发明的第四实施方式进行说明。
在本实施方式中，代替电阻部400或在电阻部400之外、或者代替第一内部电阻区域(R3a)或在第一内部电阻区域(R3a)之外，在面内方向，在二极管用焊盘200的下方的第一内置二极管区域(D4)与栅极焊盘100的下方的第二MOSFET区域(M1)之间设置有第二内部电阻区域(R3b)(参照图38以及图39的假想线c4以及假想线d4)。在本实施方式中也能够采用在上述各实施方式中采用过的所有结构。对于在上述各实施方式中说明过的构件将添加相同符号来进行说明。其中，图38的假想线a4以及假想线b4的截面，能够采用与第一实施方式或者第二实施方式相同的形态。
如图30以及图31所示，第二内部电阻区域(R3b)具有设置在第二阱区120内的低浓度n型区域(n-)705。超高浓度n型区域(n++)706在面内方向与低浓度n型区域705相邻设置，并且通过金属层40，与二极管用焊盘200相连接。此外，在相对于低浓度n型区域705与超高浓度n型区域706的面内方向是相反的方向上设置有低浓度p型区域(p-)710。而且，高浓度n型区域(n+)702在面内方向与低浓度p型区域710相邻设置，超高浓度n型区域(n++)701在面内方向与高浓度n型区域702相邻设置，并且通过金属层40，与栅极焊盘100相连接。
低浓度n型区域705沿面内方向的规定方向连续设置。作为一例，如图39所示，低浓度n型区域705在图39纸面的上下方向延伸。这时，在面内方向与第二内部电阻区域(R3b)相邻的超高浓度n型区域706以及低浓度p型区域710也沿该规定方向连续设置。
如图30至图33所示，第二栅电极110通过第一绝缘膜60设置在低浓度p型区域710的上方。第二栅电极110的上方设置有二极管用焊盘200，并且第二栅电极110与二极管用焊盘200相连接。低浓度p型区域710的厚度比超高浓度n型区域706、低浓度n型区域705、高浓度n型区域702以及超高浓度n型区域701的厚度更薄。
本实施方式的平面MOSFET(M3a)并非是第三实施方式的常导通状态，而是常关闭状态。本实施方式的平面MOSFET(M3a)的Vth能够是比第二MOSFET区域(M1)的Vth更低的值。根据这种方式，可以不设置第一内置二极管区域的D2b。这时，如图30至图33所示，第三上方阱区211是由与第三下方阱区215相同的平面形状构成，例如是在面内方向延伸的条纹形。此外，第三上方阱区211的浓度可以与第三下方阱区215相同，或者是更高的高浓度。通过设为这种不设置第一内置二极管区域的D2b的形态，就能够将D4设为高耐压SBD(JBS)。并且通过设为这种形态，就能够在进入雪崩之前成为软(soft)波形。在使整体成为导通时，由于平面MOSFET(M3a)是关闭的，因此第二MOSFET区域(M1)的Vth可以变低。
如图34以及图35所示，在二极管用焊盘200的下方的第一内置二极管区域(D4)与源极焊盘1的下方的第一MOSFET区域(M0)之间，设置有通过金属层40与二极管用焊盘200相连接的超高浓度n型区域(n++)724、以及在面内方向与超高浓度n型区域724相邻的高浓度n型区域(n+)723，在高浓度n型区域723与第一MOSFET区域(M0)的超高浓度n型区域(n++)32之间，设置有超高浓度p型区域(p++)721(参照图38以及图39的假想线g4)。通过高浓度n型区域723与超高浓度p型区域721来形成第二保护二极管区域(D7)。超高浓度p型区域721与第一MOSFET区域(M0)的超高浓度n型区域32通过金属层40连接于源极焊盘1。
根据所述结构，第二保护二极管区域(D7)的阳极如图40所示，与第一MOSFET区域(M0)的源极相连接。根据这种方式，就能够按照第一保护二极管区域(D6)的Cj(以及/或者第二MOSFET区域(M1)与MOSFET(M3a)的Ciss)与第二保护二极管区域(D7)的Cj比例来分配关闭时的dV/dt，从而仅使第一保护二极管区域(D6)流通于第二内部电阻区域(R3b)与平面MOSFET(M3a)。因此，即使第一内置二极管区域(D4)的面积变得较大，也能够成为所需的实效Crss。此外，还能够使在第一内置二极管区域(D4)发生过度雪崩时的能量被第一内置二极管区域(D4)与第二保护二极管区域(D7)所吸收，进而就能够防止栅极驱动电路侧的过电流与过电压。
图38的假想线e4中的截面可以与第一实施方式相同，也可以是如图36以及图37所示的方式。在图36以及图37中，没有使用第一实施方式中的高浓度p型区域(p+)121以及高浓度p型区域(p+)521(参照图9以及图10)。这是上述的第二MOSFET区域(M1)的低Vth，因此，第三MOSFET区域(M5)的VTH也较低。
第五实施方式
下面，对本发明的第五实施方式进行说明。
在本实施方式中，如图41至图44所示，在栅极焊盘100的下方设置有第三内部电阻区域(R3c)、以及第二内置二极管区域(D4a)(参照图51以及图52的假想线c5以及假想线d5)。作为一例，如图51所示，在栅极焊盘100的下方设置有第二内置二极管区域(D4a)，在第二内置二极管区域(D4a)的面内方向的两侧(图51的左右)设置有一对第二MOSFET区域(M1)，第二内置二极管区域(D4a)与第二MOSFET区域(M1)的面内方向之间设置有一对第三内部电阻区域(R3c)。第二内置二极管区域(D4a)与第三内部电阻区域(R3c)的面内方向之间设置有用于分离第二阱区120的n型区域(n)85a。本实施方式也能够采用上述各实施方式中采用过的所有结构。对于在上述各实施方式中说明过的构件将添加相同符号来进行说明。
如图41以及图42所示，本实施方式的第二内置二极管区域(D4a)具有第三阱区830。第三阱区830具有第三下方阱区825、以及设置在第三下方阱区825的第三上方阱区821。第三上方阱区821与第四实施方式相同，为条纹形。此外，第三上方阱区821的上方设置有由多晶硅等构成的第一连接区域831。这时，第三上方阱区821以及漂移层12与第一连接区域的第一部分831肖特基接触。
如所述般，在第二内置二极管区域(D4a)与第二MOSFET区域(M1)的面内方向之间设置有第三内部电阻区域(R3c)。第三内部电阻区域(R3c)如图41以及图42所示，具有设置在第二阱区120内的低浓度n型区域(n-)805。n型区域(n)806在面内方向上在第二内置二极管区域(D4a)侧与低浓度n型区域805相邻设置。此外，在相对于低浓度n型区域805与该n型区域806的面内方向是相反的方向上，设置有低浓度p型区域(p-)810。高浓度n型区域(n+)802在面内方向与低浓度p型区域810相邻设置，超高浓度n型区域(n++)801在面内方向与高浓度n型区域802相邻设置。n型区域806的上端面设置有由多晶硅等构成的第一连接区域的第二部分832。
如图45以及图46所示，在第二内置二极管区域(D4a)与第一MOSFET区域(M0)之间，设置有超高浓度n型区域(n++)844、在面内方向与超高浓度n型区域844相邻的高浓度n型区域(n+)843、以及与高浓度n型区域(n+)843相邻的超高浓度p型区域(p++)841(参照图51以及图52的假想线g5)。并且，通过高浓度n型区域843与超高浓度p型区域841来形成第二保护二极管区域(D7)。超高浓度p型区域(p++)841与第一MOSFET区域(M0)的超高浓度n型区域(n++)32相邻，并且超高浓度p型区域841与第一MOSFET区域(M0)的超高浓度n型区域32通过金属层40，与源极焊盘1相连接。
第二保护二极管区域(D7)的超高浓度n型区域844通过金属层40，与第二布线层850相连接。设置在第三上方阱区821上方的第一连接区域的第一部分831以及第二部分832的上方，设置有第二布线层850，并且第二布线层850与第一连接区域的第一部分831以及第二部分832相连接。其中，第一连接区域的第一部分831以及第二部分832的周缘部被设置为搭设在由栅极氧化膜等构成的第一绝缘膜60上并形成段差。在第二布线层850的下方，设置有用于将设置了第二内置二极管区域(D4a)的第三阱区830与第一阱区20相分离的n型区域(n)85a。
其中，在图41的假想线h5a中的截面如图47以及图48所示，在图41的假想线h5b中的截面如图49以及图50所示，第一连接区域的第一部分831和第二部分832以及第二栅电极110通过第二布线层850来电气连接，这样一来，二极管区域D4a通过第二布线层850以及第一连接区域831，与第二栅电极110电气连接。
上述各实施方式的记载以及附图的描述，只是用于说明申请范围中记载发明的一例，申请范围中记载的发明不受上述实施方式的记载或者附图所限定。此外，申请最初的权利要求的记载只是一例，基于说明书、附图等记载，能够将权利要求的记载进行适当变更。
符号说明
1 源极焊盘
10 第一栅电极
11 碳化硅半导体基板(宽带隙半导体基板)
12 漂移层
20 第一阱区
30 第一源极区域
100 栅极焊盘
110 第二栅电极
120 第二阱区
130 第二源极区域
200 二极管用焊盘
211 第三上方阱区
215 第三下方阱区
400 电阻部
510 第三栅电极
D2 二极管区域
D4 二极管区域
D6 第一保护二极管区域
D7 第二保护二极管区域
M0 第一MOSFET区域
M1 第二MOSFET区域
M5 第三MOSFET区域

Claims (15)

1.一种宽带隙半导体装置，其特征在于，包括：
漂移层，采用第一导电型的宽带隙半导体材料；
源极焊盘；
第一MOSFET区域，设置在所述源极焊盘的下方，具有第一栅电极、以及设置在由第二导电型构成的第一阱区的第一源极区域，所述源极焊盘与所述第一源极区域电气连接；
栅极焊盘，与所述第一栅电极电气连接；
第二MOSFET区域，设置在所述栅极焊盘的下方，具有第二栅电极、以及设置在由第二导电型构成的第二阱区的第二源极区域，所述栅极焊盘与所述第二源极区域电气连接；以及
内置二极管区域，与所述第二栅电极电气连接。
2.根据权利要求1所述的宽带隙半导体装置，其特征在于：进一步包括：
第三MOSFET区域，具有与所述栅极焊盘电气连接的第三栅电极、以及设置在所述第二阱区的第三源极区域。
3.根据权利要求2所述的宽带隙半导体装置，其特征在于：
其中，所述第三MOSFET区域为平面MOSFET，在所述第二阱区内设置有所述第三源极区域以及第三漏极区域。
4.根据权利要求1所述的宽带隙半导体装置，其特征在于：
进一步包括与所述第二栅电极相连接的二极管用焊盘，
所述内置二极管区域通过所述二极管用焊盘与所述第二栅电极电气连接。
5.根据权利要求4所述的宽带隙半导体装置，其特征在于：
其中，所述二极管用焊盘与所述栅极焊盘之间通过电阻部电气连接。
6.根据权利要求4所述的宽带隙半导体装置，其特征在于：
其中，所述内置二极管区域具有：设置在所述二极管用焊盘的下方并且由第二导电型构成的第三上方阱区、以及设置在所述第三上方阱区的下方并且由掺杂物浓度比所述第三上方阱区更高的第三下方阱区。
7.根据权利要求6所述的宽带隙半导体装置，其特征在于：
其中，所述二极管用焊盘与所述第三上方阱区肖特基接触。
8.根据权利要求1所述的宽带隙半导体装置，其特征在于：
其中，在至少有一部分设置在所述栅极焊盘的下方的第一阱区内，设置有与所述源极焊盘以及所述栅极焊盘电气连接的第一保护二极管区域。
9.根据权利要求1所述的宽带隙半导体装置，其特征在于：
进一步包括与所述第二栅电极相连接的二极管用焊盘，
在至少有一部分设置在所述二极管用焊盘的下方的第二阱区内，设置有与所述二极管用焊盘以及所述栅极焊盘电气连接的第二保护二极管区域。
10.根据权利要求1所述的宽带隙半导体装置，其特征在于：
进一步包括与所述第二栅电极相连接的二极管用焊盘，
在至少有一部分设置在所述二极管用焊盘的下方的第一阱区内，设置有与所述二极管用焊盘以及所述源极焊盘电气连接的第二保护二极管区域。
11.根据权利要求1所述的宽带隙半导体装置，其特征在于：
进一步包括与所述第二栅电极相连接的二极管用焊盘，
在至少有一部分设置在所述二极管用焊盘的下方的第二阱区内，设置有电阻区域，所述电阻区域具有与所述二极管用焊盘以及所述栅极焊盘电气连接的低浓度第一导电型区域。
12.根据权利要求1所述的宽带隙半导体装置，其特征在于：
其中，在所述栅极焊盘的下方设置有与所述第二栅电极电气连接的第一连接区域。
13.根据权利要求12所述的宽带隙半导体装置，其特征在于：
其中，在所述第一连接区域的下方设置有与所述第一连接区域电气连接的内置二极管区域。
14.根据权利要求12所述的宽带隙半导体装置，其特征在于：
其中，在位于所述栅极焊盘的下方的第二阱区内，设置有电阻区域，所述电阻区域具有与所述第一连接区域以及所述栅极焊盘电气连接的低浓度第一导电型区域。
15.根据权利要求12所述的宽带隙半导体装置，其特征在于：
其中，在面内方向上所述源极焊盘与所述栅极焊盘之间，设置有与所述第一连接区域以及所述第二栅电极电气连接的第二布线层，
所述内置二极管区域通过所述第二布线层以及所述第一连接区域与所述第二栅电极电气连接，
在至少有一部分设置在所述第二布线层的下方的第一阱区内，设置有与所述第二布线层以及所述源极焊盘电气连接的第二保护二极管区域。
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US11410990B1 (en) * 2020-08-25 2022-08-09 Semiq Incorporated Silicon carbide MOSFET with optional asymmetric gate clamp
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223705A (ja) * 1999-01-29 2000-08-11 Nissan Motor Co Ltd 半導体装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811065A (en) * 1987-06-11 1989-03-07 Siliconix Incorporated Power DMOS transistor with high speed body diode
JPH0793433B2 (ja) * 1988-11-08 1995-10-09 日本電気株式会社 電界効果トランジスタ
JPH0465878A (ja) * 1990-07-06 1992-03-02 Fuji Electric Co Ltd 半導体装置
US5818084A (en) * 1996-05-15 1998-10-06 Siliconix Incorporated Pseudo-Schottky diode
US6268242B1 (en) * 1997-12-31 2001-07-31 Richard K. Williams Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact
JP3911566B2 (ja) * 1998-01-27 2007-05-09 富士電機デバイステクノロジー株式会社 Ｍｏｓ型半導体装置
US6906386B2 (en) * 2002-12-20 2005-06-14 Advanced Analogic Technologies, Inc. Testable electrostatic discharge protection circuits
TWI313060B (en) * 2003-07-28 2009-08-01 Japan Science & Tech Agency Feild effect transisitor and fabricating method thereof
US7825431B2 (en) * 2007-12-31 2010-11-02 Alpha & Omega Semicondictor, Ltd. Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection
JP2010177454A (ja) * 2009-01-29 2010-08-12 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置
JP5539355B2 (ja) * 2009-07-15 2014-07-02 三菱電機株式会社 電力用半導体装置およびその製造方法
JP5692227B2 (ja) 2010-06-30 2015-04-01 三菱電機株式会社 電力用半導体装置
US9287393B2 (en) * 2013-03-31 2016-03-15 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device
WO2014192198A1 (ja) * 2013-05-29 2014-12-04 パナソニックＩｐマネジメント株式会社 半導体装置
TWI542006B (zh) * 2013-06-21 2016-07-11 竹懋科技股份有限公司 溝渠式ｍｏｓ整流元件及其製造方法
JP6509621B2 (ja) * 2015-04-22 2019-05-08 ルネサスエレクトロニクス株式会社 半導体装置
WO2016174758A1 (ja) * 2015-04-30 2016-11-03 オリンパス株式会社 固体撮像装置および撮像システム
CN115274855A (zh) * 2017-02-24 2022-11-01 三菱电机株式会社 碳化硅半导体装置以及电力变换装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223705A (ja) * 1999-01-29 2000-08-11 Nissan Motor Co Ltd 半導体装置

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