CN1115116A - 半导体器件中制作金属阻挡层的方法 - Google Patents

半导体器件中制作金属阻挡层的方法 Download PDF

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CN1115116A
CN1115116A CN95109193A CN95109193A CN1115116A CN 1115116 A CN1115116 A CN 1115116A CN 95109193 A CN95109193 A CN 95109193A CN 95109193 A CN95109193 A CN 95109193A CN 1115116 A CN1115116 A CN 1115116A
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film
tino
gas
metal barrier
diffusion
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CN1062978C (zh
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张玹珍
李禹奉
文永和
全英昊
高在浣
具永谟
金世桢
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Priority claimed from KR1019940016514A external-priority patent/KR960005873A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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Abstract

本发明涉及一种在金属层间作为阻断Si原子扩散用的扩散阻挡层-TiNO金属阻挡层的制作方法。该方法包含以下步骤：使用Ar和N2气体，通过溅射设备制成-TiN膜；在TiN膜上部注入N2O气体；把所生成的膜层在N2气氛下退火，使氧离子扩散，从而形成均匀的TiNO膜。

Description

半导体器件中制作金 属阻挡层的方法
本发明涉及在半导体器件的制作过程中，用于多层间电连接的金属阻挡层的制作方法。特别涉及TiNO结构的扩散金属阻挡层的制作方法。
在制造具有薄结合层的亚微细器件时，通常铝合金与金属阻挡层一起使用以防止结合部尖峰效应及减小接触部位的电阻。
另一方面，为方便起见，金属阻挡层主要由包括Ti/TiN膜的双层结构组成。TiN膜被用作扩散阻挡层以阻断在金属层之间的Si原子的扩散。为了能作到完全阻挡，TiN的构成比例必须是1∶1。
但是现有的溅射设备难于把该比例控制为1∶1。并且TiN膜由于其多孔性而难于有效地阻止原子的扩散。
本发明是基于上述问题而作出的。本发明的目的是提供一种制作TiNO金属阻挡层的方法，该TiNO金属阻挡层比TiN金属阻挡层具有更致密的结构。
为实现该目的，本发明的第一方面是提供一种制作TiNO金属阻挡层的方法，该TiNO金属阻挡层是用作阻止金属层间原子扩散的扩散阻挡层，该方法包含如下步骤：使用Ar和N2气氛，通过溅射设备制成一TiN膜；在TiN膜上部注入N2O气；把所制成的膜层在N2气氛下退火使氧离子扩散，将所制成的膜层制成均匀的TiNO膜。
本发明的另一方面是提供一种制作TiNO金属阻挡层的方法，该TiNO金属阻挡层是用作阻止金属层间原子扩散的扩散阻挡层，该方法包含以下步骤：在预制作金属阻挡层的部位制成一TiN膜；用等离子增强化学蒸汽沉积(PECVD)法，在温度为300至500℃的氧气氛下对TiN膜进行等离子处理，使氧离子注入到TiN膜中。
本发明的再一方面是提供一种制作TiNO金属阻挡层的方法，该TiNO金属阻挡层是用作阻止金属层间原子扩散的扩散阻挡层，该方法包含以下步骤：制成一Ti膜；把氧离子注入Ti膜，使氧原子置入Ti膜的中部；把所制成的膜层在N2气氛下退火，将所述所制成的膜层制成均匀的TiNO膜。
通过以下结合附图所作的说明，本发明的上述和其它目的、特征和优点将更清楚。
图1A到图1C是说明本发明第一个实施例制作金属阻挡层的方法的横剖视图。
图2A到图2C是说明本发明第二个实施例制作金属阻挡层的方法的横剖视图。
图3A至图3C是说明本发明第三个实施例制作金属阻挡层的方法的横剖视图。
现在参照图1A到图1C、图2A到图2C和图3A到图3C来详述本发明。
图1A到图1C是说明本发明第一个实施例制作金属阻挡层的方法的横剖视图。
首先，如图1A所示，用0～50sccm的Ar气和30～1000sccm N2气，通过溅射设备制作一TiN膜11。
接着，如图1B所示，把5～200sccm的N2O气注入TiN膜11上部，生成比TiN膜结构更致密的TiNO膜12。为了防止因氧原子过多存留在TiNO膜12里使TiN膜11电阻值增大的负效应，此工序分两步进行。
最后，如图1C所示，在温度为200～500℃的N2气氛下退火，使TiNO膜12中多余的氧离子扩散到TiN膜11中。
图2A到图2C是说明本发明的第二个实施例制作金属阻挡层的方法的横剖视图。
首先，如图2A所示，在预制作金属阻挡层的部位上制作一TiN膜21。
其次，如图2B所示，用等离子体增强化学气相沉积法，即PECVD法，在温度为300～500℃的氧气氛下通过等离子体对TiN膜21进行处理，使O-2、O 、O+和O2+离子注入TiN膜21中。此时，由于膜片的温度超过300℃，而且高温对注入的离子提供了激活能量，因而在初始阶段不稳定的TiN膜21就很容易与氧离子结合在一起。
结果，如图2C所示。经以上工序形成了TiNO膜22。
图3A到图3C是说明本发明的第三个实施例制作金属阻挡层的方法的横剖视图。
首先，如图3A所示，制作一个厚度超过300的Ti膜31。
接着，如图3B所示，把氧离子通过一个离子注入系统注入到Ti膜31的表面上。此时离子的注入要直到氧原子置入Ti膜31中部为止。
最后，如图3C所示，把它在N2气氛下退火，形成具有TiNO结构的扩散阻挡膜层33。
这里，退火过程可在温度超过660℃下以快速加热工艺(RPT)进行，也可以在450℃的炉中进行。当在N2气氛下退火处理时，Ti膜中的一部分氧原子扩散到Ti膜底部，另一部分氧原子扩散入Ti膜表面。结果，形成了具有TiNO结构的金属阻挡层。此时，由于过量的氧离子的存在会使元器件产生负效应，因此这时很重要的一点是控制离子注入量，以便使TiNO膜中氧离子的存留量低于10％。
按本发明的方法所制作的具有TiNO结构的金属阻挡层可以作为扩散阻挡层，因为它有着致密的结构，在它里面的原子不易扩散。
并且，由于起到很好阻挡作用的膜层厚度很薄，所以膜的应力可以减小。另外，也可以获得使亚微细薄层结合处的结合漏电流稳定的作用。

Claims (5)

1、一种制作TiNO金属阻挡层的方法，该金属阻挡层是在金属层间作为阻止Si原子扩散用的扩散阻挡层，所述方法包含以下步骤
使用Ar和N2气体，通过一个溅射设备制作一TiN膜；
在所述TiN膜上部注入N2O气体；以及
把所生成的膜层在N2气氛下退火，使氧离子扩散，从而将所述所生成的膜层制成均匀的TiNO膜。
2、根据权利要求1所述的方法，其中，注入所述溅射设备中的所述气体包括：0～50sccm Ar气体，30～1000sccm N2气体和5～200sccm N2O气体。
3、根据权利要求2所述的方法，其中，所述退火工序在200～500℃温度下进行。
4、一种制作TiNO金属阻挡层的方法，该金属阻挡层是在金属层间作为阻止Si原子扩散用的扩散阻挡层，所述的方法包含以下步骤：
在预制作阻挡层的部位生成一TiN膜；以及
用等离子体增强化学气相沉积(PECVD)法，在氧气氛和300～500℃的温度下对所述TiN膜进行等离子处理，使氧离子注入所述TiN膜中。
5、一种制作TiNO金属阻挡层的万法，该金属阻挡层是在金属层间作为阻止Si原子扩散用的扩散阻挡层，所述的方法包含以下步骤：
生成一Ti膜；
把氧离子注入所述Ti膜上使氧原子置入所述Ti膜中部；以及
将所生成的膜层在N2气氛下退火，从而将所述所生成的膜层制成均匀的TiNO膜。
CN95109193A 1994-07-07 1995-07-07 半导体器件中制作金属阻挡层的方法 Expired - Fee Related CN1062978C (zh)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
KR1994-16350 1994-07-07
KR1019940016350A KR100310468B1 (ko) 1994-07-07 1994-07-07 반도체 소자의 장벽금속막 형성방법
KR199416350 1994-07-07
KR1994-16509 1994-07-08
KR1019940016509A KR970007175B1 (ko) 1994-07-08 1994-07-08 반도체 소자의 금속배선 형성방법
KR199416514 1994-07-08
KR1019940016514A KR960005873A (ko) 1994-07-08 1994-07-08 반도체 소자의 금속배선 형성방법
KR199416509 1994-07-08
KR1994-16514 1994-07-08

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CN102623389A (zh) * 2011-01-31 2012-08-01 北京泰龙电子技术有限公司 一种金属氮化物阻挡层的制备方法

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CN102392216A (zh) * 2011-11-22 2012-03-28 南京大学 一种高热稳定性双层扩散阻挡层材料的制备方法

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GB9513938D0 (en) 1995-09-06

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