CN111415982B - 薄膜晶体管及其制造方法 - Google Patents

薄膜晶体管及其制造方法 Download PDF

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CN111415982B
CN111415982B CN201911265505.XA CN201911265505A CN111415982B CN 111415982 B CN111415982 B CN 111415982B CN 201911265505 A CN201911265505 A CN 201911265505A CN 111415982 B CN111415982 B CN 111415982B
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thin film
film transistor
oxide semiconductor
semiconductor layer
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CN111415982A (zh
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郑在景
金兑圭
柳培根
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Industry University Cooperation Foundation IUCF HYU
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Abstract

提供一种薄膜晶体管，其包括源极、漏极，以及连接所述源极和所述漏极的沟道层。所述沟道层包括由SnMO表示的锡基氧化物，其中M包括非金属硫族元素或卤族元素中的至少一种。

Description

薄膜晶体管及其制造方法
相关申请的交叉引用
本专利申请要求于2019年1月7日提交的韩国专利申请第10-2019-0001522号的优先权，其全部内容在此通过引用并入。
技术领域
本公开涉及一种薄膜晶体管及其制造方法，尤其涉及一种使用P型氧化物半导体薄膜作为沟道层的薄膜晶体管及其制造方法。
背景技术
最近，将薄膜晶体管与逻辑电路集成到透明玻璃、塑料衬底或半导体衬底上的技术已经得到研究。为了将薄膜晶体管制成互补金属氧化物半导体(complementary metal-oxide semiconductor，CMOS)型，需要载流子为空穴的P型氧化物薄膜晶体管，连同载流子为电子的N型氧化物薄膜晶体管。N型氧化物薄膜晶体管可以使用N型氧化物半导体作为沟道层，例如，可以使用具有优异的电学和光学特性的非晶氧化铟镓锌(indium-gallium-zinc oxide，IGZO)等作为N型氧化物薄膜晶体管的沟道层。用作P型氧化物薄膜晶体管的沟道层的P型氧化物半导体可以具有较大的空穴有效质量和较差的载流子传输特性，从而可以限制P型氧化物薄膜晶体管的性能。因此，对可以实现具有高性能的P型氧化物薄膜晶体管的P型氧化物半导体薄膜进行了各种研究。
发明内容
本公开提供了一种通过降低P型氧化物半导体的空穴有效质量而具有改良的电学性能的薄膜晶体管及其制造方法。
本公开还提供了一种具有改良的沟道层表面粗糙度的薄膜晶体管及其制造方法。
本发明构思的一个实施例提供了一种薄膜晶体管，包括：源极、漏极，以及连接所述源极和所述漏极的沟道层。所述沟道层可以包括由SnMO表示的锡基氧化物，其中M可以包含或包括非金属硫族元素或卤族元素中的至少一种。
在一个实施例中，M可以包括硒(Se)、硫(S)、氟(F)、氯(Cl)、溴(Br)或碘(I)中的至少一种。
在一个实施例中，所述沟道层可以包括由SnMxO1-x表示的锡基氧化物，其中x可以大于0.2且小于0.8。
在一个实施例中，所述沟道层可以包括由SnMxO1-x表示的锡基氧化物，其中x可以大于0.4且小于0.7。
在一个实施例中，所述锡基氧化物可以包括非晶相。
在一个实施例中，所述沟道层还可以包括用于调节所述锡基氧化物的带隙能量的金属元素。
在一个实施例中，所述金属元素可以包括镧(La)、钙(Ca)、锶(Sr)、钇(Y)、钽(Ta)、铪(Hf)、钛(Ti)、钡(Ba)或锆(Zr)中的至少一种。
在一个实施例中，所述沟道层还可以包括P型杂质。
在一个实施例中，所述P型杂质可以包括氮(N)、磷(P)或砷(As)中的至少一种。
在一个实施例中，所述薄膜晶体管还包括：栅极，以及在所述沟道层和所述栅极之间的栅极介电层。
在本发明构思的一个实施例中，薄膜晶体管包括：源极、漏极，以及连接所述源极和所述漏极的P型氧化物半导体层。所述P型氧化物半导体层可以包括SnMO，其中M可以包含或包括非金属硫族元素或卤族元素中的至少一种。
在一个实施例中，所述P型氧化物半导体层的至少一部分可以为非晶态的。
在一个实施例中，所述P型氧化物半导体层可以包括SnSeO，该SnSeO包括非晶相。
在一个实施例中，所述P型氧化物半导体层可以包括SnSexO1-x，其中x可以大于0.2且小于0.8。
在一个实施例中，所述P型氧化物半导体层可以包括SnSexO1-x，其中x可以大于0.4且小于0.7。
在一个实施例中，所述P型氧化物半导体层还可以包括金属元素。
在一个实施例中，所述P型氧化物半导体层还可以包括P型杂质。
在一个实施例中，所述薄膜晶体管还包括：栅极，以及在所述P型氧化物半导体层和所述栅极之间的栅极介电层。
在本发明构思的一个实施例中，一种制造薄膜晶体管的方法包括：在衬底上形成氧化物半导体层，并对所述氧化物半导体层进行热处理。所述氧化物半导体层可以包括SnMO，其中M可以包含或包括非金属硫族元素或卤族元素中的至少一种。
在一个实施例中，所述形成氧化物半导体层可以包括：通过使用Sn靶和SnM靶来进行溅射工艺；在所述溅射工艺中提供氧气；通过调节施加于所述SnM靶的功率来调节所述氧化物半导体层中的M的量。
附图说明
为提供对本发明构思的进一步理解，包括了附图，附图被并入本说明书并构成本说明书的一部分。附图示出了本发明构思的示例性实施例，并与相关说明一起用于解释本发明构思的原理。在附图中：
图1是根据本发明构思的一些实施例的薄膜晶体管的横截面图；
图2是示出图1中用作沟道层的氧化物半导体的能带的概念图；
图3和4是示出根据本发明构思的一些实施例的薄膜晶体管的传输特性的图；
图5是示出根据本发明构思的一些实施例的薄膜晶体管的输出特性的图；
图6是根据本发明构思的一些实施例的薄膜晶体管的横截面图；
图7是示出根据本发明构思的一些实施例的制造薄膜晶体管的方法的流程图；
图8是专门用来示出图7中步骤S20的流程图。
具体实施方式
本发明构思的优选实施例将参照附图进行描述，以便充分理解本发明构思的实施例的构成和效果。然而，本公开可以具有各种变化的不同形式体现，不应解释为仅限于本文所阐述的实施例。相反，这些实施例的提供是为了使本公开透彻且完整，并将本公开的范围完全传达给本领域技术人员。
在本说明书中，当一个元件被称为在另一个元件“上”时，理解为它可以直接在所述另一个元件上，或者也可以存在中间元件。此外，在附图中，为了清楚地进行说明，夸大了元件的尺寸。相同的标号贯穿全文指代相同元件。
详细描述的实施例将使用作为本发明的理想示例视图的截面视图和/或平面视图来描述。在附图中，为了清楚地进行说明，夸大了层和区域的尺寸。附图中示例的区域具有一般属性，用于示出半导体封装区域的具体形状。因此，这不应解释为限制本发明的范围。
应当理解，尽管本文中的术语第一、第二和第三用于描述各种元件，但这些元件不应受到这些术语的限制。这些术语仅用于将一个区域或层与另一个区域或层区分开来。本文描述并举例说明的实施例包括其互补实施例。
在本说明书中，术语仅用于解释实施例，而不是限制本公开。在本说明书中，除非上下文另有明确说明，否则单数形式也意在包括复数形式。应理解，术语“包括”和/或“包含”在用于本说明书中时，明确了所述组件、步骤、操作和/或元素的存在，但不排除一个或多个其他组件、步骤、操作和/或元素的存在或添加。
下文将参照附图对本发明构思进行更为详细的说明。
图1是根据本发明构思的一些实施例的薄膜晶体管的横截面图，示出了底栅型薄膜晶体管。图2是示出图1中用作沟道层的氧化物半导体的能带的概念图。
参照图1，薄膜晶体管500可以包括衬底100上的栅极110、所述栅极110上的沟道层130、所述栅极110和所述沟道层130之间的栅极介电层120，以及连接到所述沟道层130的源极140和漏极150。所述源极140和所述漏极150可以彼此水平地间隔开，所述沟道层130可以将所述源极140和所述漏极150彼此连接。所述栅极110可以通过所述栅极介电层120与所述沟道层130间隔开。
所述衬底100可以是玻璃、金属箔、塑料或硅中的任何一种，但本实施例不限于此。所述栅极110可以包括以下中的至少一种：选自氧化铟锡(ITO)、氧化镓锌(GZO)、氧化铟镓锌(IGZO)、氧化铟镓(IGO)、氧化铟锌(IZO)以及氧化铟(In2O3)组成的组中的任意一种或者两种或更多种的组合形成的透明金属；或导电金属，如钨、铝和铜。所述栅极介电层120可包括氧化铝、氮化硅或氧化硅中的至少一种。所述源极140和所述漏极150中的每一个可以包括：选自氧化铟锡(ITO)、氧化镓锌(GZO)、氧化铟镓锌(IGZO)、氧化铟镓(IGO)、氧化铟锌(IZO)以及氧化铟(In2O3)组成的组中的一种或者两种或更多种的组合形成的透明金属；和/或导电金属，如镍、金和铂。
所述沟道层130可以是P型氧化物半导体层。所述沟道层130可以包括由SnMO表示的锡基氧化物，其中M可以包含或包括非金属硫族元素或卤族元素中的至少一种。例如，M可包含或包括硒(Se)、硫(S)、氟(F)、氯(Cl)、溴(Br)或碘(I)中的至少一种。所述锡基氧化物可以包括非晶相。因此，所述沟道层130的至少一部分可为非晶的，从而降低所述沟道层130的表面粗糙度。
参照图1和2，所述锡基氧化物SnMO可以具有比氧化锡(SnO)更宽的价带。也就是说，所述锡基氧化物SnMO的价带最大值(E_VBM)可以是比氧化锡(SnO)的价带最大值(VBM)更高的能级。这可以由所述锡基氧化物SnMO价带中Sn的s轨道与M和O的p轨道杂化引起。由于所述锡基氧化物SnMO具有扩展价带，尽管所述锡基氧化物SnMO的结构无序，仍可以减少空穴有效质量。结果，可以增加所述沟道层130中的空穴迁移率(mhall)和空穴载流子密度(nh)，从而提高所述薄膜晶体管500的电学性能。
再次参照图1，所述沟道层130可以包括由SnMxO1-x表示的锡基氧化物，其中x可以大于0.2且小于0.8(即，0.2＜x＜0.8)。在一个示例中，所述沟道层130包括锡基氧化物SnSexO1-x，其中x可以大于0.2且小于0.8。表1示出了取决于所述锡基氧化物中的硒(Se)含量(x)的所述沟道层130的表面粗糙度、空穴迁移率(mhall)和空穴载流子密度(nh)。
[表1]
随着所述锡基氧化物中硒(Se)含量(x)的增加，可以降低所述沟道层130的表面粗糙度。当所述锡基氧化物中硒(Se)元素和氧元素的比例接近于约1：1(例如SnSe0.56O0.44)时，所述沟道层130中的所述空穴迁移率(mhall)和所述空穴载流子密度(nh)可为最大。当所述锡基氧化物中的硒(Se)含量(x)小于0.2(即，x＜0.2)时，所述锡基氧化物可以类似于具有四方晶体结构的氧化锡(SnO)，从而增加所述沟道层130的表面粗糙度。当所述锡基氧化物中的硒(Se)含量(x)大于0.8(即x＞0.8)时，所述锡基氧化物可以类似于具有斜方晶体结构的硒化锡(SnSe)。在这种情况下，可以减小所述沟道层130的表面粗糙度，但是所述薄膜晶体管500可能不显示所需的电学特性(例如，传输或输出特性)。
当所述锡基氧化物中的硒(Se)含量(x)大于0.2且小于0.8(即0.2＜x＜0.8)时，所述锡基氧化物可以包括非晶相，从而降低所述沟道层130的表面粗糙度。另外，在这种情况下，由于所述锡基氧化物具有如参照图2所述的扩展价带，可以减小所述空穴有效质量，结果，可以增加所述沟道层130中的所述空穴迁移率(mhall)和所述空穴载流子密度(nh)。因此，可以在减小所述沟道层130的表面粗糙度的同时提高所述薄膜晶体管500的电学性能。
根据一些实施例，所述沟道层130可以包括由SnMxO1-x表示的锡基氧化物，其中x可以大于0.4且小于0.7(即，0.4＜x＜0.7)。例如，所述沟道层130可以包括锡基氧化物SnSexO1-x，其中x可以大于0.4且小于0.7。表2示出了取决于所述锡基氧化物中的硒(Se)含量(x)的所述沟道层130中的空穴迁移率(mhall)和空穴载流子密度(nh)。
[表2]
SnSe0.46O0.54 SnSe0.52O0.48 SnSe0.56O0.44 SnSe0.62O0.38
nh[cm-3] 9.8x1016 9.1x1016 1.2x1017 8.0x1016
mhall[cm2V-1S-1] 9.3±2 10.8±3 15.0±4 10.3±3
当所述锡基氧化物中的硒(Se)含量(x)大于0.4且小于0.7(即，0.4＜x＜0.7)时，可以显著增加所述沟道层130中的空穴迁移率(mhall)和空穴载流子密度(nh)，从而可以轻易提高所述薄膜晶体管500的电学性能。
根据一些实施例，所述沟道层130还可以包括用于调节所述锡基氧化物的带隙能量的金属元素。在氧化物半导体中，透明度可以随着所述带隙能量的增加而增加。当所述沟道层130中的金属元素的含量增加时，所述锡基氧化物的带隙能量可以增加，因此，所述沟道层130的透明度可以提高。所述金属元素可用于提高所述沟道层130的透明度。所述金属元素可包括例如，镧(La)、钙(Ca)、锶(Sr)、钇(Y)、钽(Ta)、铪(Hf)、钛(Ti)、钡(Ba)或锆(Zr)中的至少一种。
根据一些实施例，所述沟道层130还可以包括P型杂质。所述P型杂质可用于增加所述沟道层130的P型特性。P型杂质可包括例如，氮(N)、磷(P)或砷(As)中的至少一种。
图3和4是示出根据本发明构思的一些实施例的薄膜晶体管的传输特性的图，图5是示出根据本发明构思的一些实施例的薄膜晶体管的输出特性的图。
图3示出了当所述薄膜晶体管500中的所述沟道层130包括锡基氧化物SnSexO1-x(其中0.2＜x＜0.8)时的传输特性，图4示出了当所述薄膜晶体管500中的所述沟道层130包括锡基氧化物SnSexO1-x(其中0.4＜x＜0.7)时的传输特性。参照图3和4，可以确定，当VGS朝向负电压方向增加时，所述薄膜晶体管500导通，IDS增加。也就是说，可以确认，所述薄膜晶体管500作为P型氧化物薄膜晶体管工作。尤其参照图4，可以确认，当所述薄膜晶体管500中的所述沟道层130包括锡基氧化物SnSexO1-x(其中0.4＜x＜0.7)时，所述薄膜晶体管500的传输特性显著提高。
图5示出了当所述薄膜晶体管500中的所述沟道层130包括锡基氧化物SnSe0.56O0.44时的输出特性。参照图5，可以确定，IDS依据VGS的变化而变化。可以确定，由于IDS由VGS控制，所述薄膜晶体管500可以用作P型氧化物薄膜晶体管。
图6是根据本发明构思的一些实施例的薄膜晶体管的横截面图，示出了顶栅型薄膜晶体管。
参照图6，所述薄膜晶体管500可以包括：衬底100上的沟道层130；所述沟道层130上的栅极110；所述栅极110和所述沟道层130之间的栅极介电层120；以及连接到所述沟道层130的源极140和漏极150。所述源极140和所述漏极150可以彼此水平地间隔开，所述沟道层130可以将所述源极140和所述漏极150彼此连接。所述栅极介电层120可以覆盖所述沟道层130、所述源极140和所述漏极150。所述栅极110可以通过所述栅极介电层120与所述沟道层130分隔开。除所描述的结构差异以外，所述薄膜晶体管500可以与参照图1和2所描述的所述薄膜晶体管500基本相同。
图7是示出根据本发明构思的一些实施例的制造薄膜晶体管的方法的流程图，图8是专门描述图7中步骤S20的流程图。
参照图1和7，可以在所述衬底100上形成所述栅极110(步骤S10)，然后，可以形成覆盖所述栅极110的所述栅极介电层120。此后，可以在所述栅极介电层120上形成所述沟道层130。形成所述沟道层130可以包括在所述衬底100上形成包括SnMO的氧化物半导体层(步骤S20)。M可以包括非金属硫族元素或卤族元素中的至少一种，例如，可以包括硒(Se)、硫(S)、氟(F)、氯(Cl)、溴(Br)或碘(I)中的至少一种。
参照图7和8，形成氧化物半导体层的步骤S20可以包括：通过使用Sn金属靶和SnM化合物靶进行溅射工艺(步骤S22)；在所述溅射工艺中提供氧气。根据一些实施例，还可以在所述溅射工艺中供应惰性气体。形成氧化物半导体层的所述步骤S20还可以包括通过调节在所述溅射工艺中施加于所述SnM化合物靶的功率来调节所述氧化物半导体层中M的量(步骤S26)。所述沟道层130可以形成为通过调节所述氧化物半导体层中M的量来显示所需的表面粗糙度、空穴迁移率(mhall)和空穴载流子密度(nh)。
再次参照图7，形成所述沟道层130还可以包括对所述氧化物半导体层进行热处理(步骤S30)。所述热处理可以在真空气氛中进行，可以防止所述氧化物半导体层中的M挥发或被氧取代。所述源极140和所述漏极150可以在所述沟道层130上形成(步骤S40)，相应地，可以形成图1中的所述薄膜晶体管500。
形成图6中的所述薄膜晶体管500可依次包括：在所述衬底100上形成所述源极140和所述漏极150；形成覆盖所述源极140和所述漏极150的所述沟道层130；在所述沟道层130上形成所述栅极介电层120和所述栅极110。除了描述的顺序不同以外，制造图6中所述薄膜晶体管500的方法可以与参照图1、7和8所描述的制造所述薄膜晶体管500的方法基本相同。
根据本发明的概念，所述薄膜晶体管500中的所述沟道层130可以包括由SnMO表示的锡基氧化物，其中M可以包含或包括非金属硫族元素或卤族元素中的至少一种。所述锡基氧化物SnMO可以具有比氧化锡(SnO)更宽的价带，从而减少空穴有效质量。结果，可以增加所述沟道层130中的空穴迁移率(mhall)和空穴载流子密度(nh)，从而提高所述薄膜晶体管500的电学性能。
此外，所述锡基氧化物SnMO可以包括非晶相，从而降低所述沟道层130的表面粗糙度。
根据本发明构思，可以提高薄膜晶体管的电学性能，并可以降低所述薄膜晶体管中沟道层的表面粗糙度。
上述对本发明构思实施例的描述提供了用于描述本发明构思的说明性示例。因此，本发明构思不限于上述实施例，对本领域技术人员而言显而易见的是，在不脱离所附权利要求限定的本发明的精神和范围的情况下，可以对本发明构思进行各种修改和变更。

Claims (18)

1.一种薄膜晶体管，包括：
源极；
漏极；以及
连接所述源极和所述漏极的沟道层，
其中，所述沟道层包括由SnMxO1-x表示的锡基氧化物，其中x大于0.2且小于0.8，
其中M包括硒(Se)、硫(S)、氟(F)、氯(Cl)、溴(Br)或碘(I)中的至少一种。
2.根据权利要求1所述的薄膜晶体管，
其中，所述沟道层包括由SnMxO1-x表示的锡基氧化物，
其中x大于0.4且小于0.7。
3.根据权利要求1所述的薄膜晶体管，其中，所述锡基氧化物包括非晶相。
4.根据权利要求1所述的薄膜晶体管，其中，所述沟道层还包括用于调节所述锡基氧化物的带隙能量的金属元素。
5.根据权利要求4所述的薄膜晶体管，其中，所述金属元素包括镧(La)、钙(Ca)、锶(Sr)、钇(Y)、钽(Ta)、铪(Hf)、钛(Ti)、钡(Ba)或锆(Zr)中的至少一种。
6.根据权利要求1所述的薄膜晶体管，其中，所述沟道层还包括P型杂质。
7.根据权利要求6所述的薄膜晶体管，其中，所述P型杂质包括氮(N)、磷(P)或砷(As)中的至少一种。
8.根据权利要求1所述的薄膜晶体管，还包括：
栅极；以及
在所述沟道层和所述栅极之间的栅极介电层。
9.一种薄膜晶体管，包括：
源极；
漏极；以及
连接所述源极和所述漏极的P型氧化物半导体层，
其中，所述P型氧化物半导体层包括SnMxO1-x，其中x大于0.2且小于0.8，
其中M包括硒(Se)、硫(S)、氟(F)、氯(Cl)、溴(Br)或碘(I)中的至少一种。
10.根据权利要求9所述的薄膜晶体管，其中，所述P型氧化物半导体层的至少一部分为非晶态的。
11.根据权利要求9所述的薄膜晶体管，其中，所述P型氧化物半导体层包括SnSeO，该SnSeO包括非晶相。
12.根据权利要求11所述的薄膜晶体管，
其中，所述P型氧化物半导体层包括SnSexO1-x，
其中x大于0.2且小于0.8。
13.根据权利要求11所述的薄膜晶体管，
其中，所述P型氧化物半导体层包括SnSexO1-x，
其中x大于0.4且小于0.7。
14.根据权利要求9所述的薄膜晶体管，其中，所述P型氧化物半导体层还包括金属元素。
15.根据权利要求9所述的薄膜晶体管，其中，所述P型氧化物半导体层还包括P型杂质。
16.根据权利要求9所述的薄膜晶体管，还包括：
栅极；以及
在所述P型氧化物半导体层和所述栅极之间的栅极介电层。
17.一种制造薄膜晶体管的方法，所述方法包括：
在衬底上形成氧化物半导体层，以及
对所述氧化物半导体层进行热处理，
其中，所述氧化物半导体层包括SnMxO1-x，其中x大于0.2且小于0.8，
其中M包括硒(Se)、硫(S)、氟(F)、氯(Cl)、溴(Br)或碘(I)中的至少一种。
18.根据权利要求17所述的方法，其中，所述形成氧化物半导体层包括：
通过使用Sn靶和SnM靶来进行溅射工艺；
在所述溅射工艺中提供氧气；以及
通过调节施加于所述SnM靶的功率来调节所述氧化物半导体层中M的量。
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